MCU R&D Strategies for the Smart Society

MCU R&D Strategies for the Smart Society

Renesas Technology & Solution Portfolio
___________________________________________________________________________________________________________________________________ The wealth of technology you see here is a direct result of the fact that Renesas Electronics Corporation was formed on April 1, 2010 as a joint venture between Renesas Technology and NEC Electronics — Renesas Technology having been launched seven years ago by Hitachi, Ltd. and Mitsubishi Electric Corporation. There are four major areas where Renesas offers distinct technology advantage. --The Microcontrollers and Microprocessors are the back bone of the new company. Renesas is the undisputed leader in this area with 31% of W/W market share. --We do have a rich portfolio of Analog and power devices. Renesas has the #1 market share in low voltage MOSFET solutions. --We have a rich portfolio of ASIC solution with an advanced 90nm, 65nm, 40nm and 28nm processes. The key solutions are for the Smart Grid, Integrated Power Management and Networking --ASSP: Industry leader for USB 2.0 and USB 3.0. Solutions for the cell phone market -- Memory: #1 in the Networking Memory market

Smart Society Paradigm
From sporadic to CONTINUOUS measurement Energy is limited INFORMATION OVERLOAD is an opportunity for PATTERN RECOGNITION “Soon the amount of data in the world will QUADRUPLE every day” -IBM More THINGS connected to the internet than PEOPLE PRIVACY is the new ATOMIC BOMB REALTIME is the new PRIME TIME Source: The conversation prism by Brian Solis & LESS3

Data is the Key “Between now and 2020, the amount of digital information created and replicated in the world will grow to an almost inconceivable 35 trillion gigabytes, as all major forms of media -voice, TV, radio, print -complete the journey from analog to digital… This explosive growth means that by 2020, our Digital Universe will be 44 times as big as it was in 2009.” -IDC data is the NEW OIL

Trends of CPU Performance
MIPS 1000 Dual-core 200MHz 32-bit 100 40MHz 80MHz 25MHz 16/32-bit 10 16MHz 10MHz 16-bit 1 Let’s take a look last the performance requirement graph of past 25 years in semiconductor industry. A classic example is the automotive application. [Click] In the early 80’s when MCU are first been used to control the electronics in automotive. There were simple 4/8-bit controllers which could do the job. By 1990, the performance demand increased to 8 fold and more powerful 16-bit controller started making in road to automotive applications like ECU. The decade of 90’s witnessed the fasted growth in MCU performance. By the end of 20th century, 32-bit controllers became common place. During past 8 years, the push is definitely towards the higher performance, but time power consumption requirements becomes very critical. There are two major directions; develop power efficient process and run the MCUs at higher frequency and/or develop a multi-core microprocessors and run at the lower speed to conserve the power 2MHz 8-bit 0.1 0.01 1980 Year 1990 2000 2010

Trends of Embedded Memory Capacity
10 FLASH 2MB 4MB 8MB x8 1 FLASH 256kB 512kB 1MB x8 OTP 32kB FLASH 128kB 64kB 0.1 If we analyze the embedded flash memory trend in past 25 years, it is evident that in each decade the memory requirement has increased 8 times to the previous one. The memory technology that we have chosen for RX family is designed to accommodate high density embedded flash memory. Our plan is to have up to 4MB of on board flash memory on RX products. x8 MASK 2~16kB 0.01 Year 1980 1990 2000 2010

Agenda Renesas’ innovative Microcontroller Technologies Summary & Q/A
Process technology Architecture (Performance and Power consumption) Innovative integration Summary & Q/A By the end of this session you will be able to: Understand the Renesas’ microcontroller technologies and solutions driving the smart society concept [Click] In this presentation I will briefly discussed key tends in microcontroller. After that I will explain how Renesas is addressing these trends with various 8,16 and 32-bit solutions.

Embedded Flash Technology Roadmap
Memory Structure 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 NOR (Split-gate) Max. read freq. Tech. NOR 40MHz Low power op. Low voltage ES MP 130nm 130nm NOR 50MHz Unified flash (RV40F) for RH850 & RX600 MONOS* RC03F (Former Renesas Tech.) MONOS 100MHz 90nm MONOS 120MHz UX6LF (Former NECEL) In the session XXC , RH850 & RL78 - Next Generation of Automotive Microcontrollers., Paul Kanan introduces this high level of the RH850 and RL78 MCU for the Automotive Market <Click> NOTE For Reviewer, the below notes are from the XXC presentation so you can better understand this slide ________________________________________________________________________________________________________________________________ 1.) Renesas is continuing to utilized the VERY low power SuperFlash – SST NOR- The industry leading NOR Flash cell - Characterized by very Low power , very fast erase time, and excellent Data Retention. 2.) For High speed Flash application (Such as Body Computer, Airbag control, Powrtrain…) Renesas utilizes the MONOS flash cell. - Both Former Renesas Tech and Former NEC Electronics employe MONOS Cell and for our next Generation we create an industry lead Flash cell for Memory access and low power. 40nm MONOS 100MHz Large capacity High speed * MONOS: Metal Oxide Nitride Oxide Silicon 90nm Renesas MCUs are the first with 40 nm embedded flash!

World First 40nm Flash MCU
320MHz CPU 120MHz Flash ~ 8MByte Lowest power consumption Transistor / mm2 40nm 55nm Other Option A 65nm Other Option B Previous generation 90nm In the session XXC , RH850 & RL78 - Next Generation of Automotive Microcontrollers., Paul Kanan introduces this high level of the RH850 and RL78 MCU for the Automotive Market <Click> NOTE For Reviewer, the below notes are from the XXC presentation so you can better understand this slide ________________________________________________________________________________________________________________________________ What does this allow RENESAS 1.) 320MHz high end performance 2.) Low power 3.) More dies per wafer 100 80 60 40 Technology node Leading Flash Process for Next Generation Automotive & Industrial

No. 1 MCU Supplier in the World
Firmly maintained the world’s No.1 MCU market share of 27% in CY2011 Dominant position in automotive MCU unchanged with the world’s No.1 share M US$ CY2011 Auto- motive MCU General- purpose MCU * Freescale Infineon Atmel STMicro Microchip TI Samsung Fujitsu NXP WW MCU #1 27% share WW Automotive MCU #1 42% share 8-bit MCU #1: 17% share 16-bit MCU #1: 27% share 32-bit MCU #1: 38% share Deepened relationships with carmakers Collaborating in BCP *General-purpose MCU: MCUs for applications excluding automobiles 　Source: IHS iSuppli, Annual 2011 Semiconductor Market Share

Microcontroller and Microprocessor Line-up
2010 2012 1200 DMIPS, Superscalar 1200 DMIPS, Performance Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby Automotive, 40nm 500µA/MHz, 35µA deep standby 500 DMIPS, Low Power 32-bit Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 165 DMIPS, FPU, DSC 165 DMIPS, FPU, DSC Industrial, 90nm 500µA/MHz, 1.6µA deep standby Industrial, 40nm 200µA/MHz, 0.3µA deep standby Those of you who have attended the last DevCon in 2010, the left side of this slide should look familiar. In 2010, as a result of the merger between Renesas Technology and NEC Electronics, we started offering MCU solutions based on these five cores. The R8C and 78K were mainly focusing on low end 8/16 bit applications in both automotive and industrial applications,. The RX with 32 bit CISC core was mainly offering solutions for Industrial and consumer applications. The high-end V850 and SH cores with 32-bit RISC architecture were very successful in high end automotive and industrial applications. Within 6 months after the merger, we launched a brand new 16-bit product family named RL78, combining the low power flash technology and the CPU core from NEC’s 78K product line and innovative peripherals from Renesas’ R8C product family. The RL78 family is a great example of the synergy effect of this merger. The RL78 is now our main focus product line for cost sensitive low power applications. It consumes only 144uA/MHz power in active mode and only 0.2uA in standby mode. With up to 44DMIPS throughput, it offers much higher performance compared to any other 8/16 microcontrollers in the market place. The RX family continues to be our flagship 32-bit family for Industrial and consumer applications. With 100 MHz single cycle flash, 1.65DMIPS/MHz throughput and packed with connectivity peripherals it is ideal for digital signal controller applications. Since its introduction in 2009, we are rapidly expanding the RX product line. Now we have more than 500 different RX MCUs covering from 32KB to 2MB flash memory options. Similar to the RX, we have recently announced the launch of our next generation high-end 32 bit microcontroller architecture for automotive applications. The new family is called RH850 and provides a next-generation migration path to automotive customers currently using V850 or SH in their application. For Industrial customers currently using V850 or SH, the migration path is the RX product family. Very soon we will launch a 240MHz RX product line which can cover the need of Industrial customers requiring more than 100MHz performance. So, in summary, from 2013 and beyond, we will mainly be focusing on the three CPU cores, RL78, RX, and RH850, to cover the broad spectrum of the industrial and automotive application space, and we will continue to support legacy architectures like R8C, 78K, SH, and V850 for existing customers. 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 44 DMIPS, True Low Power 8/16-bit Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 10 DMIPS, Capacitive Touch Industrial & Automotive, 130nm 350µA/MHz, 1µA standby Wide Format LCDs

2010 2012 1200 DMIPS, Superscalar 1200 DMIPS, Performance Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 32-Bit High Performance, High Scalability & High Reliability Automotive, 40nm 500µA/MHz, 35µA deep standby 500 DMIPS, Low Power 32-bit Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 165 DMIPS, FPU, DSC 165 DMIPS, FPU, DSC Industrial, 90nm 500µA/MHz, 1.6µA deep standby Industrial, 40nm 200µA/MHz, 0.3µA deep standby Those of you who have attended the last DevCon in 2010, the left side of this slide should look familiar. In 2010, as a result of the merger between Renesas Technology and NEC Electronics, we started offering MCU solutions based on these five cores. The R8C and 78K were mainly focusing on low end 8/16 bit applications in both automotive and industrial applications,. The RX with 32 bit CISC core was mainly offering solutions for Industrial and consumer applications. The high-end V850 and SH cores with 32-bit RISC architecture were very successful in high end automotive and industrial applications. Within 6 months after the merger, we launched a brand new 16-bit product family named RL78, combining the low power flash technology and the CPU core from NEC’s 78K product line and innovative peripherals from Renesas’ R8C product family. The RL78 family is a great example of the synergy effect of this merger. The RL78 is now our main focus product line for cost sensitive low power applications. It consumes only 144uA/MHz power in active mode and only 0.2uA in standby mode. With up to 44DMIPS throughput, it offers much higher performance compared to any other 8/16 microcontrollers in the market place. The RX family continues to be our flagship 32-bit family for Industrial and consumer applications. With 100 MHz single cycle flash, 1.65DMIPS/MHz throughput and packed with connectivity peripherals it is ideal for digital signal controller applications. Since its introduction in 2009, we are rapidly expanding the RX product line. Now we have more than 500 different RX MCUs covering from 32KB to 2MB flash memory options. Similar to the RX, we have recently announced the launch of our next generation high-end 32 bit microcontroller architecture for automotive applications. The new family is called RH850 and provides a next-generation migration path to automotive customers currently using V850 or SH in their application. For Industrial customers currently using V850 or SH, the migration path is the RX product family. Very soon we will launch a 240MHz RX product line which can cover the need of Industrial customers requiring more than 100MHz performance. So, in summary, from 2013 and beyond, we will mainly be focusing on the three CPU cores, RL78, RX, and RH850, to cover the broad spectrum of the industrial and automotive application space, and we will continue to support legacy architectures like R8C, 78K, SH, and V850 for existing customers. 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 44 DMIPS, True Low Power 8/16-bit Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 10 DMIPS, Capacitive Touch Industrial & Automotive, 130nm 350µA/MHz, 1µA standby Wide Format LCDs

High-end, 32-bit CPU Roadmap
Succession of “V850 and SH” Architecture High Performance and Low power G3M +FPU(IEEE ) +Branch prediction, +SIMD, +Multi-Core V850E2M +MPU SH2A SH Architecture SH2 SH1 V850E2R +FPU V850E2 * 7-Stage * dual-issue Good Performance and Low Power In the session 1C06B, RH850 & RL78 - Next Generation of Automotive Microcontrollers., Paul Kanan introduces this high level of the RH850 and RL78 MCU for the Automotive Market <Click> NOTE For Reviewer, the below notes are from the XXC presentation so you can better understand this slide ________________________________________________________________________________________________________________________________ Key Points  High performance, high code efficiency by 16/32/48 bit variable instructions 1.) V850 RISC Architecture Building on success of proven V850 Core 7 –Stage pipe FPU Advance SIMD and branch prediction Multi core support. 2.) From we are continuing to develop a Good performance / Low power” core w/ 5 stages pipe focusing on reducing transitor count and reducing pow V850E1 * 5-stage V850 Architecture G3K * 5-stage E2S * 5-stage

RH850 Architecture (Example CPU Core and Pipeline)
Example RH850 CPU 5-STAGE PIPELINE 5 STAGES OF PIPELINE F = FETCH INSTRUCTION D = DECODE INSTRUCTION E = EXECUTE INSTRUCTION M = READ OR WRITE MEMORY W = WRITE BACK TO REGISTER 96 MHz CPU Core 2.x DMIPS/MHz 5-STAGE PIPELINE TICK F D F TICK E D F TICK M E D F TICK W M E D F TICK F W M E D TICK D F W M E TICK E D F W M TICK M E D F W TICK Flash Memory Capable to Flash 120MHz SRAM Memory Protect Unit Interrupt Control On-Chip Debug 32x 32bit General Purpose Registers Inst 128 bit path Instruction Data 39 bit path Operand (Data) HARVARD ARCHITECTURE F D E M W E W M E D F E Que 1 Que 2 32bit Floating Point Unit (Optional) Achieves : One Clock-Per-Instruction (CPI) 32x MAC, b Result HARVARD ARCHITECTURE In the session 1C06B, RH850 & RL78 - Next Generation of Automotive Microcontrollers., Paul Kanan introduces this high level of the RH850 and RL78 MCU for the Automotive Market <Click> NOTE For Reviewer, the below notes are from the XXC presentation so you can better understand this slide Click--- Core running at 96MHz… which is ~2DMIPS /MHz… roughly 190DMIPs Click ---Option FPU for more performance or model based development Click ---32b MAC instruction Click b multiply and divide Click ---Typically, you have some Flash and SRAM which you need to i/f with .. (128 bit instruction path); 39 bit data bus Click --- Let’s fill the pipeline.. Click – by third cycle we have achieved 1 execution per cycle; CLICK; by the 5 stage pipeline is filled. For More performance we also have a 7 stage pipeline in the G3M core… Basically the “fetch stage” is broken up into Fetch; Transfer and instruction pairing state; before the decode. During the IT 32 x 32 DIV or MULT, 32bit or 64bit Result

RH850 Architecture… System Interface
RH850 MCU PIPELINE Buffer RH850 128b instruction 64 bits 128b INST BUFFER 32b DATA 32 bits SRAM, MHz Access Flash Memory, 120MHz Access Bus Master Internal Main Bus 1/ System interconnect 32 bits Bus Bridge Bus Bridge DMAC (bus master) In the session XXC , RH850 & RL78 - Next Generation of Automotive Microcontrollers., Paul Kanan introduces this high level of the RH850 and RL78 MCU for the Automotive Market <Click> NOTE For Reviewer, the below notes are from the XXC presentation so you can better understand this slide ________________________________________________________________________________________________________________________________ Peripheral Busses to Spread Bandwidth Loading Communication (CSI, CAN, SCI,LIN, I2C, Flex Ray) Timers (TAUA, TAU J, OST, CMT) Analog GPIO System Control (DMA, E2P, ICU, LVD, RTC, WDG, CLKS)

RH850: 40nm MCU Series for Vehicle Control
High Mid Low Powertrain 320MHz Dual core w/ Lockstep I/O CPU 240MHz Dual core w/LS I/O processor 160MHz Single core w/LS 240MHz Dual core w/ LS 240MHz Single core w/ LS High Reliability Platform EV/HEV 240MHz Dual core w/ LS x2 240MHz Single core w/ LS 160MHz Single Core Chassis & Safety 240MHz Single core w/ LS Low Power Platform 120/160MHz Single core Low Power 80MHz Single Core Low Power Air Bag 120MHz Multi Core Low Cyclic Power 120MHz Single Core Low Power 80MHz Single Core Low Power Body

RH850/F1x Line-up 8MB 6MB 4MB 3MB 2MB 1.5MB 1MB 768KB 512KB 384KB
RH850/F1U Triple-Core 160MHz 8MB RH850/F1H Dual Core 120MHz 6MB 4MB RH850/F1M Single core 120MHz 3MB 2MB 1.5MB RH850/F1L Single core 80MHz 1MB 768KB 512KB 384KB 256KB 48 64 80 100 144 176 208 272 357 QFP BGA 17

2010 2012 1200 DMIPS, Superscalar 1200 DMIPS, Performance Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 32-Bit High Performance DSP, FPU with High Integration 32-Bit High Efficiency Ultra Low Power and Low Voltage Automotive, 40nm 500µA/MHz, 35µA deep standby 500 DMIPS, Low Power 32-bit Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 165 DMIPS, FPU, DSC 165 DMIPS, FPU, DSC Industrial, 90nm 200µA/MHz, 0.3µA standby Industrial, 40nm 200µA/MHz, 0.3µA standby Those of you who have attended the last DevCon in 2010, the left side of this slide should look familiar. In 2010, as a result of the merger between Renesas Technology and NEC Electronics, we started offering MCU solutions based on these five cores. The R8C and 78K were mainly focusing on low end 8/16 bit applications in both automotive and industrial applications,. The RX with 32 bit CISC core was mainly offering solutions for Industrial and consumer applications. The high-end V850 and SH cores with 32-bit RISC architecture were very successful in high end automotive and industrial applications. Within 6 months after the merger, we launched a brand new 16-bit product family named RL78, combining the low power flash technology and the CPU core from NEC’s 78K product line and innovative peripherals from Renesas’ R8C product family. The RL78 family is a great example of the synergy effect of this merger. The RL78 is now our main focus product line for cost sensitive low power applications. It consumes only 144uA/MHz power in active mode and only 0.2uA in standby mode. With up to 44DMIPS throughput, it offers much higher performance compared to any other 8/16 microcontrollers in the market place. The RX family continues to be our flagship 32-bit family for Industrial and consumer applications. With 100 MHz single cycle flash, 1.65DMIPS/MHz throughput and packed with connectivity peripherals it is ideal for digital signal controller applications. Since its introduction in 2009, we are rapidly expanding the RX product line. Now we have more than 500 different RX MCUs covering from 32KB to 2MB flash memory options. Similar to the RX, we have recently announced the launch of our next generation high-end 32 bit microcontroller architecture for automotive applications. The new family is called RH850 and provides a next-generation migration path to automotive customers currently using V850 or SH in their application. For Industrial customers currently using V850 or SH, the migration path is the RX product family. Very soon we will launch a 240MHz RX product line which can cover the need of Industrial customers requiring more than 100MHz performance. So, in summary, from 2013 and beyond, we will mainly be focusing on the three CPU cores, RL78, RX, and RH850, to cover the broad spectrum of the industrial and automotive application space, and we will continue to support legacy architectures like R8C, 78K, SH, and V850 for existing customers. 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 44 DMIPS, True Low Power 8/16-bit Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 10 DMIPS, Capacitive Touch Industrial & Automotive, 130nm 350µA/MHz, 1µA standby Wide Format LCDs

RX Architecture… CPU Core and Pipeline
RX600 CISC CPU 5-STAGE PIPELINE 5 STAGES OF PIPELINE F = FETCH INSTRUCTION D = DECODE INSTRUCTION E = EXECUTE INSTRUCTION M = READ OR WRITE MEMORY W = WRITE BACK TO REGISTER PRE-FETCH QUEUE (PFQ) Holds 4 to 32 Instructions for Slower Memory Memory Interface 64 32 100MHz CPU Core 1.65 DMIPS/MHz 5-STAGE PIPELINE TICK F D F TICK E D F TICK M E D F TICK W M E D F TICK F W M E D TICK D F W M E TICK E D F W M TICK M E D F W TICK Typically SRAM Typically Flash Memory RX Flash is 10 nsec, or 100 MHz zero-wait RX SRAM is also 10 nsec Memory Protect Unit Interrupt Control On-Chip Debug 16 x 32bit General Purpose Registers 9 x 32bit Control Registers Inst 64bit path Instruction Data 32bit path Operand (Data) ENHANCED HARVARD ARCHITECTURE E F D E M W W M E D F 64bits 32bit Floating Point Unit Achieves One Clock-Per-Instruction (CPI) 16x16 or 32x32 MAC, bit or 80bit Result ENHANCED HARVARD ARCHITECTURE WRITE BUFFER For Slow Memory First lets examine the RX CPU core itself, the pipelined instruction path, and the operand path. At the heart of the RX600 MCU is a 100MHz, 32-bit CISC CPU core seen here, capable of 1.65 DMIPS/MHz. The CPU has 16 general purpose 32-bit registers, striking an optimum balance between performance and cost. <click> There’s also a full single precision floating point unit tightly coupled to the CPU core <click> A multiply accumulate unit producing either a 48-bit result in one-cycle, or an automatically repeated MAC producing an 80-bit result for efficient DSP operations <click> A hardware multiply and divide unit <click> Plus fast interrupt control, an on-chip JTAG debugger with high-speed trace, and a Memory Protection Unit <click> Now let’s examine the paths between the CPU core and memory. The RX is based on an enhanced Harvard architecture, with a 64-bit wide dedicated bus for instructions, and a 32-bit wide dedicated bus for operands, or data. This is an extremely optimum arrangement. The longest RX instruction is 64 bits, and the native data size is 32-bits. Typically the instruction bus is connected to Flash memory, and the data bus to SRAM. But as we’ll see later it does not always have to be this way because RX has enhanced Harvard architecture. <click> Notice that the Flash can be read at 100MHz, the same frequency as the CPU. This means the CPU will not stall while waiting to read instructions from Flash at 100MHz, even when the instruction is 64 bits wide. Also notice that the SRAM can be read, and written, at 100MHz to give the CPU full speed access for data. <click> Now moving to the instruction pipeline. A pipelined architecture is absolutely necessary for any high performance CPU to reach that ultimate goal of executing one instruction in just one CPU clock cycle. The RX has a 5-stage pipeline, breaking up instructions into many smaller parallel tasks. A 5-stage pipeline enables the RX CPU core to clocked extremely fast, in fact, increasing to 200MHz in the future. The five pipeline stages are; Fetch, Decode, Execute, Memory access, and register Write-back <click> As you can see, on each CPU clock the instruction pipeline is filled <click> And by the 4th clock cycle, it’s already possible to achieve on clock per instruction, or one CPI. <click> Looking closer at one individual cycle in the pipe <click> you can see that the CPU can command both an instruction fetch <click> And simultaneously an access to data in this same CPU clock cycle. If not for Harvard architecture, this concurrent activity would not be possible, causing a pipeline stall. <click> So far we’ve discusses CPU access to extremely fast local Flash and SRM memory, but the RX core can access slower memories and peripherals too. <click> In this case there is a small pre-fetch queue to look ahead and prefetch instructions during idle bus times when executing instructions from slower memory, such as external memory. This prefetch queue is 4 stage deep, each stage being 64-bits wide. This means there can be as many as 32, 8-bit instructions in the queue. The prefetch queue helps to keep a steady flow of instructions flowing to the CPU without stalls when instruction addresses are sequential, but it also reduces stalls when the CPU takes a branch in instruction flow. If the target branch instruction is in the queue, there is no delay. If the target is not in the queue, the queue must be flushed and reloaded. The actual delay depend on the speed of the memory access. And finally, there is a write buffer to prevent the CPU from stalling after writing to a slow external memory, or a peripheral device. This buffer allows the CPU to carry on at full speed and not to wait for the write operation to complete. Now let’s examine how the RX CPU core fits into the entire system 32 x 32 DIV or MULT, 32bit or 64bit Result Buffer Only for Writes

Advanced Bus Architecture for High Data Throughput
Here is Internal Main Bus 2. It has three bus masters, each one can arbitrate for bus ownership, they are the Ethernet DMA controller, the general DMA controller, and the Data Transfer Controller. Each of these DMA controllers offload the CPU while moving data from peripheral to peripheral, peripheral to memory, and memory to memory. The Internal Main Bus 2 can also access the external bus pins, as well as a bridge to the on-chip peripheral bus. <click> The Ethernet DMA controller is dedicated to the Ethernet MAC interface for extremely fast transfers of data to and from the SRAM with minimal impact on the CPU. The Ethernet MAC itself has a 2KB FIFO for transmitting data, as well as a 2KB FIFO for receiving data, further reducing bottlenecks and maximizing Ethernet throughput. <click> RX has a very unique feature in the External DMA controller, or EXDMA. This DMA controller can take possession of the external CPU bus pins and orchestrate the movement of data from one external device to another external device, with the data never entering the RX MCU,. This is very efficient in that loading on the RX CPU is minimal even when high bandwidth data transfers are being conducted outside the chip. For example, EXDMA easily supports moving RGB image data from an external frame buffer RAM to an external TFT-LCD panel. <click> There are as many as six individual internal peripheral busses in some RX devices, grouping on-chip peripherals to optimize data flow. For example, the USB interface resides on it’s own bus to minimized interference from slower peripheral devices. Here you can see the large number of system functions on the RX for connectivity, analog, timers, and system functions. The blocks of peripherals shown here are grouped logically to simplify this drawing, but do not necessarily reflect how they are physically grouped on the device itself. <click> Now let’s look at an example of how this vast bus structure can be exploited for maximum throughput. Here you see that the CPU can fetch instructions from Flash memory shown by the red arrow <click> At the same time the CPU can be writing to the USB interface to transmit USB data as shown by the green arrow <click> While the Ethernet DMA controller is moving data frames out on the Ethernet bus from SRAM as shown by the purple arrow <click> While the EXDAM is moving data on the external data bus from one external device to another as shown by the orange arrow. This could be a graphic frame buffer and a color TFT-LCD panel. Notice that all four of these tranfers are happening simultaneously, each one on separate physical busses with no interference to each other. <click> But it’s still possible to move even more data while this is occurring <click> The blue arrow shows that the general DMA controller can move data from a peripheral, like the ADC, into SRAM, by arbitratin access of SRAM with the Ethernet DMA controler. There is plenty of bandwidthe on Internal Main Bus 2 because it’s 32 bits wide and operates at 50Mhz. This interleaved access of SRAM has very little impact on either the Ethernet or the ADC transfers. <click> And finally, good thing because I’m running out of different colors, the yellow arrow shows how the Data Tranfer Controller can move data from a timer over to a DAC output, by using the peripheral busses. Again, there is minor arbitration needed between the DAC and the ADC, but the bandwidth of these busses is more than sufficient to minimize interference. So in the end, here are 4 completely independent high-speed transferes occuring, plus to more interleaved transfers, show the use of all five bus masters in the RX: the CPU, Ethernet DMAC, DMAC, DTC, and EXDMA. <click>

RX vs. M4: Performance, Power & Peripherals

RX600 Series: High Performance Roadmap
100 MHz, Single Cycle Flash 90 nm Process Up to 120 MHz 40 nm Process

RX200 Series: Low Power Roadmap
Comparator ＥＬＣ 50MHz 128BK-512KB RX210 Comparator ＥＬＣ 50MHz 64KB- 256KB RX210 Comparator ＥＬＣ 50MHz 1MB General Purpose RX220 Comparator ＥＬＣ 32MHz 256KB RX211 Comparator ＥＬＣ 50MHz USB RX211 24 bit ADC AES 50MHz 512KB The 16-bit RL78 MCU family from Renesas is positioned to be the premier low power/low cost, but scalable controller platform MCU family for the foreseeable future. Renesas will greatly expand the RL78 series in the next 2 years. <click> For embedded control applications needing low cost, but strong performance and low power consumption, there is an RL78 derivative for every application need like Appliances, HVAC, sensor, Industrial automation, consumer, medical and other cost-sensitive applications . For example, the current RL78/G1x series includes mainstream general purpose products, like the G12 and G13; as well as the new RL78 G14 series which features increased functionality via High-function timers, enhanced data control blocks and comparators etc. And the G1A, which has an Enhanced analog functions like 12bit ADC. Other, soon to be released RL78/G1x general purpose lines will be augmented by additional features, such as small footprint, low pin count versions (less than 20pins) , USB connectivity and other advanced HW features. For the segmented LCD market, which could include the same application areas, there will be a series of RL78/L1x MCUs with LCD boost circuit to drive segmented STN LCD panels. The RL78 L12 is currently the standard MCU in this series. Often the LCD panel applications are either battery operated and battery-backed, and the RL78 MCU core with it’s system features are well positioned to handle the low power, low voltage applications in portable instrumentation or sensors. Future RL78/ L1x variants, which are currently well into the planning stages will feature extended functionality including expanded memory and pin packages, USB-enabled devices and enhanced Analog (12bit ADC and comparators, Etc). For Application Specific Standard Products (ASSPs), there are several RL78 MCU products currently available, and many more are on the way to address any number of application needs including Auto Body control, Auto Dashboard, and Lighting control, followed up by Metering, Capacitive Touch, and Wireless (RF4CE) devices planned for later development. Advanced Analog, Security 2011 2012 2013

RX: Scalable Lineup

Next Generation RX

RX CPU Architecture Roadmap
High Performance Low Power Small Code Size 2015 Smaller gate count Smaller code size Higher Performance/MHz 4.0 Coremark/MHz MHz～ 2012 RX-v2 (240MHz～) 3.30 Coremark/MHz 0.78 Automark/MHz RX64x Next RX-v1 (200MHz～) RX600, RX200, RX100 2.76 Coremark/MHz 0.68 Automark/MHz 2009

RX Family Roadmap: Next Generation
240MHz 100/120MHz Up to 8MB Dual Ethernet, DSP, LCD 50MHz Up to 4MB DSC, FPU, Connectivity 32MHz Low power, Up to 1MB Flash, 1.62 to 5.5v, 24-bit ADC, Security Lowest Power 32-bit platform in the Industry

Industry Leading Low Power 32-bit Platform
32-bit Performance Integration Eco-System Higher power consumption <1$ price point Lowest Power Fast wake up Analog integration Scalability RX-L (32-bit) 1.56 DMIPS/MHz performance 155uA/DMIPS in active & 0.1uA in standby <$1 price point RX scalability Similar eco-system

RX-L: Lowest Power 32-bit Family
Best in class Performance Best in class Power efficiency 1.56DMIPS/MHz 155µA/DMIPS RX-L RX-L Cortex M4 1.25DMIPS/MHz 200µA/DMIPS Company B Cortex M0 Cortex M3 1.25DMIPS/MHz 300µA/DMIPS Company A Cortex M3 Cortex M0 0.9DMIPS/MHz

RX100: Unique Differentiators
Sampling NOW Lowest Power 32-bit MCU Lowest DC off set, lowest power at 1 MHz, faster wake up (<5us), <155uA/DMIPS active, 0.1uA standby Memory & Package 8KB to 2MB Flash memory, Smaller 3x3mm QFN/WPP package for space critical applications Innovative integration ELC, Asynchronous Timers to reduce power consumption Safety features IEC60730 are critical for medical and Industrial Flexibility of layout PMC to offer maximum number of I/O, Semi- programmability of I/Os and reduction of external noise circuitry Bridge between Digital and Analog world 12-bit, 24-bit A/Ds, 10-bit D/As, Op-Amps, Comparators, Temp sense, Capacitive touch etc.

RX700: 40nm, 240MHz Industrial Applications
Sampling Q1’13 High Performance 120MHz/240Mhz operation with 120MHz single cycle Flash Innovative Integration 4MB Flash, 512KB RAM, IEE1588 Dual Ethernet, Trusted ELC, 2MSPS ADC, Data Capture Unit, SDIO, MMC etc. Safety Features IEC60730, AES security, CRC, DOC , CSD etc. Flexibility of layout PMC to offer maximum number of I/O, Semi-programmability of I/Os and reduction of external noise circuitry, Event Link Controller Flexible package size 64 pin to 256 pin package variants Bridge between digital and Analog world 12-bit, 24-bit A/Ds, 10-bit D/As, Op-Amps, Comparators, Temp sense, etc.

2010 2012 1200 DMIPS, Superscalar 1200 DMIPS, Performance Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 8/16-Bit True Low Power High Efficiency & Integration Automotive, 40nm 500µA/MHz, 35µA deep standby 500 DMIPS, Low Power 32-bit Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 165 DMIPS, FPU, DSC 165 DMIPS, FPU, DSC Industrial, 90nm 200µA/MHz, 0.3µA standby Industrial, 40nm 200µA/MHz, 0.3µA standby Those of you who have attended the last DevCon in 2010, the left side of this slide should look familiar. In 2010, as a result of the merger between Renesas Technology and NEC Electronics, we started offering MCU solutions based on these five cores. The R8C and 78K were mainly focusing on low end 8/16 bit applications in both automotive and industrial applications,. The RX with 32 bit CISC core was mainly offering solutions for Industrial and consumer applications. The high-end V850 and SH cores with 32-bit RISC architecture were very successful in high end automotive and industrial applications. Within 6 months after the merger, we launched a brand new 16-bit product family named RL78, combining the low power flash technology and the CPU core from NEC’s 78K product line and innovative peripherals from Renesas’ R8C product family. The RL78 family is a great example of the synergy effect of this merger. The RL78 is now our main focus product line for cost sensitive low power applications. It consumes only 144uA/MHz power in active mode and only 0.2uA in standby mode. With up to 44DMIPS throughput, it offers much higher performance compared to any other 8/16 microcontrollers in the market place. The RX family continues to be our flagship 32-bit family for Industrial and consumer applications. With 100 MHz single cycle flash, 1.65DMIPS/MHz throughput and packed with connectivity peripherals it is ideal for digital signal controller applications. Since its introduction in 2009, we are rapidly expanding the RX product line. Now we have more than 500 different RX MCUs covering from 32KB to 2MB flash memory options. Similar to the RX, we have recently announced the launch of our next generation high-end 32 bit microcontroller architecture for automotive applications. The new family is called RH850 and provides a next-generation migration path to automotive customers currently using V850 or SH in their application. For Industrial customers currently using V850 or SH, the migration path is the RX product family. Very soon we will launch a 240MHz RX product line which can cover the need of Industrial customers requiring more than 100MHz performance. So, in summary, from 2013 and beyond, we will mainly be focusing on the three CPU cores, RL78, RX, and RH850, to cover the broad spectrum of the industrial and automotive application space, and we will continue to support legacy architectures like R8C, 78K, SH, and V850 for existing customers. 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 44 DMIPS, True Low Power 8/16-bit Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 10 DMIPS, Capacitive Touch Industrial & Automotive, 130nm 350µA/MHz, 1µA standby Wide Format LCDs

Low-end CPU Core Roadmap
RL78 Renesas New Low end core performs up to 40.6DMIPS RL78/G14 core hits 44DMIPS with DSP instructions RL78 Architecture R8C Architecture RL78/G14 core 16bit, 44DMIPS RL78 16bit, 40.6DMIPS MAC/MUL/DIV instructions R8C 10 DMIPS Compact 78K Architecture Renesas New Low end core 78K0R 16bit, 31.2DMIPS 78K0 8bit, 2.9DMIPS 78K0S 8bit,1.1DMIPS

RL78 CPU Core ES CS SP PC PSW Context Switching for Fast
Interrupt Response Register Banks 0-3: 16-bit (Register Pair) Special Compiler Support 16x16 MAC (3 cycles) Internal Buses Bank 3 16x16 MUL (2 cycles) System Bus Interface Addr./ Data Bus Bank 2 Bank 1 Address Bus ES MUL/MAC /DIV. ALU Bank 0 CS Control Signals This 78K Architecture diagram covers both 8bit (K0 and K0S) and 16bit K0R MCUs, which is a traditional Von Neuman type architecture - The 78K0, and 78K0S 8bit MCU families have an 8bit bus and 8bit ALU - The 78K0R 16bit MCU families have a full 16bit bus and 16bit ALU. - 78K0R 16bit architecture has a 3-stage pipeline which allows 85% of K0R instructions to complete in 1 or 2 cycles. [Click] The 78K architecture is an accumulator based architecture, where the accumulator can be accessed in either 8bit or 16bit size. K0S has a single Bank (0) of General purpose registers, whereas 8bit K0 and 16bit K0R have 4 banks of General Purpose registers, allowing for fast context switch response of Interrupt service routines and C function calls. [Click] Although 8bit K0S and K0 have a 64KB address space, the 16bit K0R has a linear 1MB address space without requiring address bank switching. To support the 1MB linear address space, the CPU relies on ES and CS segment registers for 4 additional addressing bits. These registers are prefixed to 16bit Gen Purpose register address pointers, but only when instructions in the space above the first 64KB memory space is invoked. The C-compiler automatically places ES or CS register addressing prefixes when needed, and omits them when un-needed. Thus, Instruction code space is efficiently conserved. The PSW (Program Status Word) holds 8 status bits: 2 bits to select the current operating General Purpose Register Bank 2 bits of In-Service-Priority to show the current Function call or Interrupt Service Routine priority Level Master Interrupt Enable bit Zero, Carry, and Auxiliary Carry Flags The Interrupt Controller has a very low 9 CPU cycles minimum to 14 CPU cycles maximum response time for Maskable Interrupts, and allows each interrupt source to be set to one of four priority levels for maximum system flexibility Special MCU single-chip controller operations: There is a bit manipulation instruction coupled with CPU HW to allow single bit MOV, AND, OR, Set, Clear, EXOR operation on any bit in RAM or Special Function Register memory that is a Write-able Address. [Click] A 16-bit Barrel shifter enables a full 16bit register or RAM shift operation (n= 1 to 15 bit positions) in a single CPU cycle SW and HW multiply and divide: 8bit K0 CPU has an 8x8 multiply instruction in SW 16bit K0R CPU has HW multiply/divide in HW blocks: 16x16 multiply >>32bit result in one CPU cycle 32/32 divide >> 32bit result, 32bit remainder in 16 CPU cycles 16-Bit Barrel Shifter N=1 to 15 (1 cycle) Bit SP PC Interrupt Controller PSW RL78/G14 only

RL78 CPU Low Power Technique
RL78 CPU stops the unused decoder or the operator circuitry per every instruction Automatically Adjusted Decode + Address operation MEM operation + Write 3-stage pipe line Fetch ID MEM Current reduction! Ex) ADD A, [HL] - Instruction : 1byte - Address Operation : HL - Data Operation : ADD Instruction Decoder Address Operator Data Operator 25% 50% Fetch 1st- Byte BR$ Add Write Selected “Path” Bit HL +Byte Let’s begin with CPU. This is an internal technique that user do not usually notice. As you can in this page RL78 has a system with 3–stage piplines. To reduce the CPU core power consumption, there is a system that detect the instruction length and Operation itself. Then by judging those, CUP only turns on the required module and the instruction, and goes through them. With the benefit of this sytems, 25% for decoder and 50% of the Operator current can be reduced and finally achieve the 66uA/MHz low power CPU operation current. 2nd- Byte Mul RAM Decoder Operator … 66uA/MHz at basic operation (NOP) Judge 1 or 2 instruction bytes 2nd-byte decoder turned on, only when the instruction is judged as 2 bytes instruction Only the operator which will be used in a instruction will be turned on.

Flash Operation Modes Flash modes realize an optimal power consumption
MCU current HS (High-speed) mode: 32MHz (VDD = 2.7 to 5.5V) 16MHz (VDD = 2.4 to 5.5V) 2.1V (Active, Halt) & 1.8V(STOP) regulator LS (Low-speed) mode: 8MHz (VDD = 1.8 to 5.5V) 1.8V regulator LV (Low-voltage) mode: 4MHz (VDD = 1.6 to 5.5V) 30% down 40% down 1.7mA 1.7mA 1.3mA 1.2mA 1.2mA 0.8mA HS 8MHz LS 8MHz HS 4MHz LS 4MHz LV 4MHz Regulator System Halt current (0.33mA) (0.27mA) (0.29mA) (0.24mA) (0.43mA) Shift the gear and change the circuit capability according to the mode User selects once based on the max Frequency and min VDD in the system Next one is the Flash memory low power technique, Flash memory can be in the suitable mode based the Operation mode and Low power modes, change the Flash memory gear change. This can remove the needless power consumption for Flash memory as well. Next one is the Operation modes. This mode is actually open to the customers and customer is supposed to set one of the modes based on the max Frequency and min VDD in the customer system. LS mode is the best power consumption mode so if customer system meets the spec mentioned here, then this mode should be selected. If customer needs above 8MHz, then HS mode will be selected. If customer is system requires less than 1.8V, then LV mode should be selected. Please keep in mind LV mode is higher current mode than LS mode due to the activation of the low voltage operation. Another thing related to this mode is Regulator out put voltage, as you may know RL78 has internal regulator for internal system, to minimize the power consumption, the regulator voltage is defined by this mode showed here. Interesting thing here is even HS mode during the standby state, regulator voltage is change 1.8V automatically to reduce the power consumption VDD RL78 Reg I/O Etc. CPU, Peripherals VSS 37 37 37

Active Current Advantage to Competition
RL78 marks low power consumption for both typical values and maximum values even against the most competitive Company A MCUs Typ. Value Max. Value Competition Competition RL78 RL78

Fast Wake-up is Good, but doesn’t Always Have an Effect
Fast wake-up is critical when active time is <30uS Assuming current consumption during wake up is the same as during the Active Active mode: 8MHz, 3V 42 mAusec 72 mAusec 35usec 204 mAusec 150 100usec No good Better 1.2mA RL78 25usec 22 mAusec A MCU-3 2.0mA This picture shows power consumption during wake up time and also after wake up time both together. If the active mode is 10 usec after wake up time, MSP430 is better than RL78 due to high speed wake-up. But when it comes to 35usec active after wake-up, the situation is totally the same. For example 100usec case, RL78 is better. Longer active mode, RL78 better. Let’s think about what you can do during less than 35usec. Just increment timer interrupt count or Sensing Analog input once or something like that. Most real application needs more than 35 usec like… ... First wake up is good, but that is only when customer has to wake up for Simple Monitoring which needs less than 35usec If customer needs something real application function which needs over 35 usec, low power active mode current has higher impact. Please understand and explain to the customer RL78 performs better in many cases even with longer wake-up time. (Please propose alternative method of Simple monitoring: Battery monitor ADC -> LVD, Port check -> INTP, Time count -> RTC) 1usec Wake up time Active Time Condition 10usec 30usec 100usec Real Application functions Glass Break detector :35usec Smock detector : 400usec Health care applications : msec to sec Remote controller : 100msec UART bps = msec EEPROM storage ; msec order Simple Monitoring - Simple Status check (1 ADC, Port check etc.) Increment Standard Timer for Real Time

RL78: Roadmap Product Category ASSP SEG LCD GENERAL ~ CY 2012 CY 2013~
F12 (Auto Body) Metering ASSP D1x (Auto Dashboard) RF4CE I1A (Lighting) L1x (USB, Enhanced Analog) Product Category SEG LCD L1x (High Function) L12 (LCD Standard) 32-64 pin, 8-32 KB The 16-bit RL78 MCU family from Renesas is positioned to be the premier low power/low cost, but scalable controller platform MCU family for the foreseeable future. Renesas will greatly expand the RL78 series in the next 2 years. <click> For embedded control applications needing low cost, but strong performance and low power consumption, there is an RL78 derivative for every application need like Appliances, HVAC, sensor, Industrial automation, consumer, medical and other cost-sensitive applications . For example, the current RL78/G1x series includes mainstream general purpose products, like the G12 and G13; as well as the new RL78 G14 series which features increased functionality via High-function timers, enhanced data control blocks and comparators etc. And the G1A, which has an Enhanced analog functions like 12bit ADC. Other, soon to be released RL78/G1x general purpose lines will be augmented by additional features, such as small footprint, low pin count versions (less than 20pins) , USB connectivity and other advanced HW features. For the segmented LCD market, which could include the same application areas, there will be a series of RL78/L1x MCUs with LCD boost circuit to drive segmented STN LCD panels. The RL78 L12 is currently the standard MCU in this series. Often the LCD panel applications are either battery operated and battery-backed, and the RL78 MCU core with it’s system features are well positioned to handle the low power, low voltage applications in portable instrumentation or sensors. Future RL78/ L1x variants, which are currently well into the planning stages will feature extended functionality including expanded memory and pin packages, USB-enabled devices and enhanced Analog (12bit ADC and comparators, Etc). For Application Specific Standard Products (ASSPs), there are several RL78 MCU products currently available, and many more are on the way to address any number of application needs including Auto Body control, Auto Dashboard, and Lighting control, followed up by Metering, Capacitive Touch, and Wireless (RF4CE) devices planned for later development. G14 (High Function) pin, KB Capacitive Touch G13 (Standard) pin, KB GENERAL G1A (Enhanced Analog) 25-64 pin, KB G1x (USB) G12 (Lite) 20-30 pin, 2-16 KB G1x (Entry) Sub 20 pins Schedule is preliminary and subject to change ~ CY 2012 CY 2013~

Scalability: RL78 Line-up (Over 300 products from 2KB to 512KB of flash memory)
G14 offers additional RAM

RL78: Next Generation Concept

SMART15 Concept Smart Power Analog SMART Integration
Asynchronous Architecture SMART Snooze (in combination with more peripherals) Intelligent-Wake-up (Quick wake-up + lowest current) Analog Intelligent connection between Analog-to-Analog & Analog-to-Digital) 16/24-bit ADC & 12-bit DAC Fast Comp, Op-Amps SMART Integration SMART Data Transfer Controller SMART integration: RF, Touch, Eink Display, BAN Super SAFE: DOC, CAC, MPU

RL78/SMART15: Roadmap Concept
Next Generation Process 130um process Remote WCP Lighting Application Specific ASSP sub Ghz Meter RL78 Core G15 GP with LCD HMI GP-Next ( pin) W/ Touch W/LCD G12 G13 General Purpose G14 GP-L next 10-20-pin G10

Summary What should engineers care about?

Questions?

‘Enabling The Smart Society’
Challenge: Digital revolution is fuelling the exponential demand to manage the society more smarter and in a eco friendly way. Solution: In order to address the complex requirements of the Smart Society a scalable microcontroller portfolio which is supported by a rich eco system would be the most important selection criteria. This is where our session, <enter your session ID and name here>, is focused within the ‘Big picture of Renesas Products’, Microcontroller and Microprocessors. <Click> NOTE For Reviewer, the below notes are from the 110C presentation so you can better understand this slide” ________________________________________________________________________________________________________________________________ Let me first introduce our rich portfolio of microcontrollers and microprocessors solution which includes 8,16 and 32 bit CPU cores.

MCU R&D Strategies for the Smart Society

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