1. NOTE: To change the image on this slide, select the picture and delete it. Then click the Pictures icon in the placeholder to insert your own image. NON VOLATILE MEMORIES Mrutyunjay

2. Overview  SSD: Solid State Driver  PCM: Phase Change Memory (NVRAM: Non Volatile RAM)  Comparison: SSD vs PCM  Others: Spin-transfer torque (SSTRAM), Magneto resistive random-access memory (MRAM)

3. SSD: Solid State Driver  Host Interface Logic  SSD Controller  RAM Buffer  Flash Memory Package

4. Flash Memory

5. SSD Architecture

6. Read, Write and Erase  Reads are aligned on page size: It is not possible to read less than one page at once. One can of course only request just one byte from the operating system, but a full page will be retrieved in the SSD, forcing a lot more data to be read than necessary.  Writes are aligned on page size: When writing to an SSD, writes happen by increments of the page size. So even if a write operation affects only one byte, a whole page will be written anyway. Writing more data than necessary is known as write amplification  Pages cannot be overwritten: A NAND-flash page can be written to only if it is in the “free” state. When data is changed, the content of the page is copied into an internal register, the data is updated, and the new version is stored in a “free” page, an operation called “read- modify-write”.  Erases are aligned on block size: Pages cannot be overwritten, and once they become stale, the only way to make them free again is to erase them. However, it is not possible to erase individual pages, and it is only possible to erase whole blocks at once.

7. Example of Write: Buffer small writes: To maximize throughput, whenever possible keep small writes into a buffer in RAM and when the buffer is full, perform a single large write to batch all the small writes Align writes: Align writes on the page size, and write chunks of data that are multiple of the page size.

8. Example of Write:

9. Why Erase and Write? Hardware limitation  SSD Cannot overwrite pages. A freshly erased,  Blank page of NAND flash has no charges stored in any of its floating gates; it stores all 1s.  1s can be turned into 0s at the page level, but it's a one-way process.  Turning 0s back into 1s is a potentially dangerous operation because it uses high voltages.  It's difficult to confine the effect only to the cells that need to be altered; the high voltages can cause changes to adjacent cells.

10. PCM: Phase Change Memory

11.  In basic terms, when electrical current is applied to a top and bottom electrode, heat is generated; and in the presence of heat, the chalcogenide changes phase.  If the heat is removed rapidly, the chalcogenide alloy remains in an amorphous phase—where the atoms are highly unorganized, non-reflective, and highly resistive. (RESET:0)  If the heat is removed slowly, the chalcogenide changes into a polycrystalline phase—where the atoms are highly organized and reflective with low resistance. Both phases are used to store information (SET:1).

12. Advantages  Non-volatile: Phase change RAM is a non-volatile form of memory, i.e. it does not require power to retain its information. This enables it to compete directly with flash memory  Bit alterable: Similar to RAM or EEPROM, P-RAM / PCM is what is termed bit-alterable. This means that information can be written directly to it without the need for an erase process. This gives it a significant advantage over flash which requires an erase cycle before new data can be written to it.  Write/erase performance: The write erase performance of P-Ram is very good having faster speeds and lower latency than NAND flash. As no erase cycle is required this delivers an overall significant improvement over flash.

13. PCM: Write & Read  Write:  SET (store 1)and RESET(store 0) are the write operation.  SET  150ns, cooling or heat is removed slowly. RESET  40ns  Less Write Endurance  Read:  The bitline is precharged to the read voltage.  If a selected cell is in a crystalline state, the bitline is discharged with current flowing through the storage element and access transistor.  Otherwise, the cell is in an amorphous state, preventing or limiting bitline current

14. PCM Array Model (2D Array Model)

15. Two-Step write model  Can’t finish write operation within a single step  Two step write operations  SET before RESET  ERASE before RESET  For example, writing “0101” in a row

16. Comparison SSD vs PCM vs RAM

17. Commercial PCM or PRAM (Still Prototypes) Companies like Samsung, Intel are working towards releasing the commercial PCM soon. Currently no commercial PCM is available. Most the research/publication are based on using the simulator, which use DRAM ( DRAMSim2 ).

18. Questions?