1. Pipeline And Vector Processing

2. Parallel Processing The purpose of parallel processing is to speed up the computer processing capability and increase its throughput, that is, the amount of processing that can be accomplished during a given interval of time. Execution of Concurrent Events in the computing process to achieve faster Computational Speed The amount of hardware increases with parallel processing, and with it, the cost of the system increases. However, technological developments have reduced hardware costs to the point where parallel processing techniques are economically feasible.

3. Parallel processing according to levels of complexity Multiplicity of functional units that performer identical or different operations simultaneously. Serial Shift register VS parallel load registers At the lower level At the higher level

4. Parallel Computers

5. SISD COMPUTER SYSTEMS

6. Von Neumann Architecture

7. MISD COMPUTER SYSTEMS

8. SIMD COMPUTER SYSTEMS

9. MIMD COMPUTER SYSTEMS

10. PIPELINING A technique of decomposing a sequential process into suboperations, with each subprocess being executed in a partial dedicated segment that operates concurrently with all other segments. A pipeline can be visualized as a collection of processing segments through which binary information flows. The name “pipeline” implies a flow of information analogous to an industrial assembly line.

11. Example of the Pipeline Organization

12. OPERATIONS IN EACH PIPELINE STAGE

13. GENERAL PIPELINE

14. Cont.

15. Speedup ratio of pipeline

16. Cont.

17. PIPELINE AND MULTIPLE FUNCTION UNITS

18. Cont.

19. ARITHMETIC PIPELINE

20. Cont. See the example in P. 310

21. INSTRUCTION CYCLE

22. INSTRUCTION PIPELINE

23. INSTRUCTION EXECUTION IN A 4-STAGE PIPELINE

24. Pipeline

25. Space time diagram

26. Structural hazards (Resource Conflicts): Hardware resources required by the instructions simultaneous overlapped execution cannot be met. MAJOR HAZARDS IN PIPELINED EXECUTION Data hazards (Data Dependency Conflicts): An instruction scheduled to be executed in the pipeline requires the result of a previous instruction, which is not yet available. Control hazards (Branch difficulties): Branches and other instructions that change the PC make the fetch of the next instruction to be delayed.

27. Data hazards Control hazards

28. STRUCTURAL HAZARDS Occur when some resource has not been duplicated enough to allow all combinations of instructions in the pipeline to execute. Example: With one memory-port, a data and an instruction fetch cannot be initiated in the same clock. The Pipeline is stalled for a structural hazard <- Two Loads with one port memory -> Two-port memory will serve without stall

29. DATA HAZARDS

30. FORWARDING HARDWARE

31. INSTRUCTION SCHEDULING

32. CONTROL HAZARDS

35. VECTOR PROCESSING There is a class of computational problems that are beyond the capabilities of conventional computer. These problems are characterized by the fact that they require a vast number of computations that will take a conventional computer days or even weeks to complete.

36. VECTOR PROCESSING

37. VECTOR PROGRAMMING

38. VECTOR INSTRUCTIONS

39. Matrix Multiplication The multiplication of two nxn matrices consists of n 2 inner products or n 3 multiply-add operations. In general, the inner product consists of the sum of k product terms of the form C = A 1 B 1 +A 2 B 2 +A 3 B 3 +…+A k B k This requires 3 multiplications and 3 additions. The total number of multiply-add required to compute the matrix product is 9x3=27. c 11 = a 11 b 11 +a 12 b 21 +a 13 b 31 Example : Product of two 3x3 matrices

40. C = A 1 B 1 +A 5 B 5 +A 9 B 9 +A 13 B 13 +… +A 2 B 2 +A 6 B 6 +A 10 B 10 +A 14 B 14 +… +A 3 B 3 +A 7 B 7 +A 11 B 11 +A 15 B 15 +… +A 4 B 4 +A 8 B 8 +A 12 B 12 +A 16 B 16 +…

41. VECTOR INSTRUCTION FORMAT

42. MULTIPLE MEMORY MODULE AND INTERLEAVING

45. ARRAY PROCESSOR

46. attached array processor with host computer

47. SIMD array processor Organization

48. Don’t forget, try to solve the questions of the chapter