1. 學生 : 蕭耕然 馮楷倫 蘇承道 指導教授 : 李泰成老師
台大－鈺創前瞻晶片設計研究第一次會議
學生 : 蕭耕然 馮楷倫 蘇承道
指導教授 : 李泰成老師

2. Outline Introduction of a Delay Locked Loop(DLL) Issues
Current Techniques

3. DDR System
Skew Calibration.
Multi-Phase Generation.

4. Conventional DLL Why DLL Lower Jitter Stable 1st-Order System
This slide shows a conventional DLL and it’s timing diagram.
A conventional DLL usually contains a phase detector which compares the phase difference between the reference clock and the delayed output clock, a charge pump or a voltage to current converter which drives the loop filter, a loop filter that memorizes the phase relationship extracts from the PD, and a voltage-controlled delay line which are also called VCDL for short.
The VCDL delays the reference clock and generates multiple phases.
The PD senses the phase difference between the reference clock and the last output clock and align them together.
If all delay cells in the VCDL are identical, all output clocks are equally phase-spacing.
But the variation in fabrication process results mismatches in delay cells, the equally phase-spaced clocks are not available.
Why DLL
Lower Jitter
Stable 1st-Order System
Reference.

5. Phase Mismatch
Mismatch in Transistor
Mismatch in Loading Capacitance

6. Noise in a Delay Cell Jitter from the Delay Cell Noise power
Signal slew rate

7. Jitter Accumulation Jitter accumulates along the delay line.
Longer delay line = Larger noise.

8. Resistor Averaging Resistor rings reduce the phase mismatch.
J.-M. Chou, Y.-T. Hsieh, and J.-T. Wu, “A 125MHz 8b Digital-to-Phase Converter”, IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Papers, Feb., 2003.

9. DLL with Phase Calibration Circuit
Delay cell tuning.
Federico Baronti, Diego Lunardini, Roberto Roncella, and Roberto Saletti, “A Self-Calibrating Delay-Locked Delay Line with Shunt-Capacitor Circuit Scheme”, IEEE Journal of Solid-State Circuits, Feb., 2004.

10. DLL with Phase Calibration Circuit
Output buffer tuning.
H.-H. Chang, J.-Y. Chang, C.-Y. Kuo, and S.-I. Liu, “A GHz Self-Calibrated Multiphase Delay-Locked Loop”, IEEE Journal of Solid-State Circuits, May, 2006.

11. Tuning Techniques Analog Tuning Area, Noise Digital Tuning
Area, Accuracy
Lin Wu, and William C. Black Jr., “A Low-Jitter Skew-Calibrated Multi-Phase Clock Generator for Time-Interleaved Applications”, IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Papers, Feb., 2001.
H.-H. Chang, J.-Y. Chang, C.-Y. Kuo, and S.-I. Liu, “A GHz Self-Calibrated Multiphase Delay-Locked Loop”, IEEE Journal of Solid-State Circuits, May, 2006.