1. © 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction  Purpose  This Part-A course discusses techniques that are used to reduce noise problems in the design of large scale integration (LSI) devices.  Objectives  Understand the requirement for electromagnetic noise countermeasures.  Learn approaches and design methods for minimizing the electromagnetic interference (EMI) emitted by LSI devices.  Gain insight into how Renesas applies these techniques for handling noise problems in its microcomputer products.  Content  16 pages  Learning Time  20 minutes

2. © 2008, Renesas Technology America, Inc., All Rights Reserved 2  Two types of noise:  Electromagnetic Compatibility (EMC) issues encompass both types  Noise reduction approaches:  Techniques for reducing EMI (Electromagnetic Interference) — Cutting the noise emitted by a specific system, circuit or device that causes other devices/circuits to operate incorrectly  Techniques for decreasing EMS (Electromagnetic Susceptibility) — minimizing the effect that external noise has on the operation of a system, circuit or device  Noise reduction: a goal common to both microcontroller (MCU) designers and the system engineers who apply those devices Noise = “Unwanted electrical signals that produce undesirable effects in the circuits of control systems in which they occur.” Noise Can Cause Big Problems

3. © 2008, Renesas Technology America, Inc., All Rights Reserved 3 Example of “real-world” effects: EMI can cause problems in the AV equipment and CIS products in an automobile Battery Audio-visual equipment, CIS products MCU Wiring harness (power line) LSI device Noise is emitted by MCU and harness, causing EMI Antenna picks up EMI noise, which degrades radio reception Why Is EMI Reduction Important?

4. © 2008, Renesas Technology America, Inc., All Rights Reserved 4 No source of noise should be overlooked! If measures are taken to deal only with elements of primary importance … 60 50 40 30 Effect: -3dB Secondary Sources Primary Sources of EMI Total EMI Secondary Sources Primary Sources Total EMI -10dB Action: 10 dB reduction EMI level (dB) BeforeAfter If measures are taken to deal with all important noise elements 60 50 40 30 Effect: -5dB Secondary Sources Primary Sources of EMI Total EMI Secondary Primary Sources Total EMI EMI level (dB) BeforeAfter If measures are taken to deal only with secondary elements … 60 50 40 30 -10dB Effect: -0.2dB Before countermeasure Secondary SourcesPrimary Sources of EMI Total EMI Secondary Total EMI Primary Sources EMI level (dB) After countermeasure Action: 10 dB reduction EMI reduction requires a comprehensive design approach and attention to detail Minimize ALL Sources of EMI

5. © 2008, Renesas Technology America, Inc., All Rights Reserved 5 EMC Electromagnetic Compatibility EMIElectromagnetic Interference EMSElectromagnetic Susceptibility SSCGSpread-Spectrum Clock Generator WDT Watchdog Timer PLL Phase Locked Loop I/O Input/Output Port Core A microcontroller chip is composed of a core, I/O ports, and power supply circuitry. The core consists of the CPU, ROM, RAM, and blocks implementing timers, communication, and analog functions. Power supply Two power supplies are applied to the LSI: Vcc and Vss. The core power supply internal to the LSI is V CL (internal step-down). The Vss-based power supply routed through the LSI is V SL. Driver buffer Output circuit transistors as well as output circuits for driving signals with large load capacitance and I/O port output transistors. Clock/bus driver, signals between blocks, etc. OSC CPG Clock Pulse Generator Oscillator POR/LVDPower-On Reset/Low-Voltage Detect functions Harness Cables (wires) connecting a board and power supply or connecting one unit in a system to another. Explanation of Terms

6. © 2008, Renesas Technology America, Inc., All Rights Reserved 6  Microcontroller pin assignments should provide power supply and signal pin placements that closely match those of external LSI devices  Allows short interconnections  Helps prevent crossed wires  Improves noise control  Facilitates crosstalk countermeasures  Reduces parasitic loads Renesas microcontroller Vss Vcc Vss Vcc External LSI Pin Assignments Help Reduce EMI

7. © 2008, Renesas Technology America, Inc., All Rights Reserved 7 Tantalum bypass capacitor Oscillation capacitors Capacitor for Reset Oscillation capacitors Ceramic bypass capacitor Key pins are concentrated in a single location Effects of electrical potential differences are minimized BYTE CNVSS XCIN XCOUT /RESET XOUT VSS XIN VCC /NMI To Reset IC GNDV CC GND Pin arrangement makes it easy to mount bypass capacitors between power supply lines and ground lines. Arrangement of Key Pins  Pins should be arranged in an electrical potential gradient  Pin layout should concentrate key pins in one area  Arrangement should make it easy to mount bypass capacitors for noise countermeasures  Standardized layouts promote design consistency

8. © 2008, Renesas Technology America, Inc., All Rights Reserved 8  Placing power supply pins in pairs near each other makes it easy to mount bypass capacitors where they can be effective Vcce Vsse Vcl (Vdd) Vcc Vss CORE-1 power supply pin CORE-2 power supply pin I/O PORT-1 power supply pin I/O PORT-2 power supply pin Vsscore I/O PORT-1 I/O PORT-2 CORE-2CORE-1 C 1, C 2, C 3, C 4 = Power supply bypass capacitors C2C2 C1C1 C3C3 C4C4 CACA Vcl (Vdd) Vsscore CBCB C A, C B = Step-down power supply (Vdd) stabilization capacitors Power Supply Pin Assignments

9. © 2008, Renesas Technology America, Inc., All Rights Reserved 9 AVCC Analog signal pins AVSSAVREF  The following types of digital signal pins should not be placed in these locations: –High-current ports –Clock-related ports –High-speed telecom ports Analog vs. Digital Signal Pins  For best analog circuit performance, some types of digital signal pins must not be located close to the analog signal pins

10. © 2008, Renesas Technology America, Inc., All Rights Reserved 10 Vcc = 5.0V Vdd (core voltage) = 1.2V Step-down voltage None Low EMI High Reduced Vcc Vss Vcl Vsl or Vss Layout of internal step-down circuit (conceptual) Step-down circuit 5V I/O Core: CPU ROM RAM TIMERS SCI Etc. A/D, D/A External step-down power supply circuit stabilization capacitor A low Vdd reduces power consumption, too. Power Supply Circuit  Internal step-down power supply circuit runs off 5V, produces precise lower voltage (Vdd) for core  The lower the core voltage, the greater the EMI reduction  A slower slew rate cuts EMI

11. © 2008, Renesas Technology America, Inc., All Rights Reserved 11 Core power supply voltage (Vdd), typ. [V] Process generation 0.8µm 0.5µm (with internal step-down voltage specification) 0.18µm 1.0 2.0 3.0 4.0 5.0 Core voltage aimed at preventing EMI Process limitations I/O = 5V Ultralow-noise version Ultralow-noise version 0.5µm0.35µm 3.0V 1.8V 1.2V Further reductions in core voltage Step-down Power Supply Voltage  Step-down voltage is used at the 0.5µm process generation and below to reduce EMI  Process limitations at 0.35µm and 0.5µm process generations and below mandate lower core voltages  Further decreases in Vdd are expected, allowing additional EMI reductions and power savings

12. © 2008, Renesas Technology America, Inc., All Rights Reserved 12 Vcc Vss Internal step-down circuit Parasitic resistance of internal power supply lines CORE Parasitic capacitances Electromagnetic filter circuit To external stabilization capacitor Vdd EMI Filter in Step-down Supply  π - type R-C filter is located between step-down circuit and core  Uses parasitic capacitances of step-down transistors and core and parasitic resistance of internal power supply lines

13. © 2008, Renesas Technology America, Inc., All Rights Reserved 13 Core-A power supply Core-B power supply I/O-B Power supply I/O-A power supply Vcc Vss CORE -A Vcc Vss CORE -B Vcc Vss Vcc Vss I/O-A I/O-B Wiring for Power Supply Lines  In devices with multiple power supply pins, Vcc and Vss should be...  Supplied in pairs  Located near each other  This design approach ensures that the chip’s internal power supply lines do not cross

14. © 2008, Renesas Technology America, Inc., All Rights Reserved 14 Bonding pads I/O circuits Vcc CORE Vss Vcc Vss Primary core supply lines CORE ROM RAM CPU TIMER SCI CPG Main Power Supply Lines in Core  Power supply lines to I/O and core are separated  Mesh configuration is used for supply lines to core

15. © 2008, Renesas Technology America, Inc., All Rights Reserved 15 A/D, D/A 5V-I/O Step-down circuit Embedded Capacitor Capacitors in Power Supply Lines  Capacitors can be placed in various locations within the LSI device  They deliver supplemental charge needed for driving digital-circuit switching  Without embedded capacitors, ripple component of power supply waveform is large  With capacitors, ripple component is small and EMI is reduced

16. © 2008, Renesas Technology America, Inc., All Rights Reserved 16 Course Summary  Types of noise (EMI and EMS) in microcomputers  Importance of EMC  Reducing EMI by using optimum methods for pin assignments, step-down power supply design, and on-chip power wiring For more information on specific devices and related support products and material, please visit our Web site: http://america.renesas.com