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Silberschatz, Galvin and Gagne  2002 13.1 Operating System Concepts Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem.

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Presentation on theme: "Silberschatz, Galvin and Gagne  2002 13.1 Operating System Concepts Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem."— Presentation transcript:

1 Silberschatz, Galvin and Gagne  2002 13.1 Operating System Concepts Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations Streams Performance

2 Silberschatz, Galvin and Gagne  2002 13.2 Operating System Concepts I/O Hardware Incredible variety of I/O devices Common concepts  Port  Bus (daisy chain or shared direct access)  Controller (host adapter) I/O instructions control devices Devices have addresses, used by  Direct I/O instructions  Memory-mapped I/O

3 Silberschatz, Galvin and Gagne  2002 13.3 Operating System Concepts A Typical PC Bus Structure

4 Silberschatz, Galvin and Gagne  2002 13.4 Operating System Concepts Device I/O Port Locations on PCs (partial)

5 Silberschatz, Galvin and Gagne  2002 13.5 Operating System Concepts Polling Determines state of device F command-ready F busy F Error Busy-wait cycle to wait for I/O from device

6 Silberschatz, Galvin and Gagne  2002 13.6 Operating System Concepts Interrupts CPU Interrupt request line triggered by I/O device Interrupt handler receives interrupts Maskable to ignore or delay some interrupts Interrupt vector to dispatch interrupt to correct handler  Based on priority  Some unmaskable Interrupt mechanism also used for exceptions

7 Silberschatz, Galvin and Gagne  2002 13.7 Operating System Concepts Interrupt-Driven I/O Cycle

8 Silberschatz, Galvin and Gagne  2002 13.8 Operating System Concepts Intel Pentium Processor Event-Vector Table

9 Silberschatz, Galvin and Gagne  2002 13.9 Operating System Concepts Direct Memory Access Used to avoid programmed I/O for large data movement Requires DMA controller Bypasses CPU to transfer data directly between I/O device and memory


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