1. CS/COE0447 Computer Organization & Assembly Language
Chapter 3

2. Topics Negative binary integers Signed versus unsigned operations
Sign magnitude, 1’s complement, 2’s complement
Sign extension, ranges, arithmetic
Signed versus unsigned operations
Overflow (signed and unsigned)
Branch instructions: branching backwards
Implementations of addition, multiplication, division
Floating point numbers
Binary fractions
IEEE 754 floating point standard
Operations
underflow
Implementations of addition and multiplication (less detail than for integers)
Floating-point instructions in MIPS
Guard and Round bits

3. Arithmetic So far we have studied
Instruction set basics
Assembly & machine language
We will now cover binary arithmetic algorithms and their implementations
Binary arithmetic will provide the basis for the CPU’s “datapath” implementation

4. Binary Number Representation
We looked at unsigned numbers before
B31B30…B2B1B0
B31231+B30230+…+B222+B121+B020
Now we want to deal with more complicated cases
Negative integers
Real numbers (a.k.a. floating-point numbers)
We’ll start with negative integers
Bit patterns and what they represent…
We’ll see 3 schemes; the 3rd (2’s complement) is used in most computers

5. Case 1: Sign Magnitude {sign bit, absolute value (magnitude)}
“0” – positive number
“1” – negative number
EX. (assume 4-bit representation)
0000: 0
0011: 3
1001: -1
1111: -7
1000: -0
Properties
two representations of zero
equal number of positive and negative numbers

6. Case 2: One’s Complement
((2N-1) – number): To multiply a 1’s Complement number by -1, subtract the number from (2N-1)_unsigned. Or, equivalently (and easily!), simply flip the bits
1CRepOf(A) + 1CRepOf(-A) = 2N-1_unsigned (interesting tidbit)
Let’s assume a 4-bit representation (to make it easy to work with)
Examples:
0011: 3
0110: 6
1001: – or just flip the bits of 0110
1111: – or just flip the bits of 0000
1000: – or just flip the bits of 0111
Properties
Two representations of zero
Equal number of positive and negative numbers

7. Case 3: Two’s Complement
(2N – number): To multiply a 2’s Complement number by -1, subtract the number from 2N_unsigned. Or, equivalently (and easily!), simply flip the bits and add 1.
2CRepOf(A) + 2CRepOf(-A) = 2N_unsigned (interesting tidbit)
Let’s assume a 4-bit representation (to make it easy to work with)
Examples:
0011: 3
0110: 6
1010: – or just flip the bits of 0110 and add 1
1111: – or just flip the bits of 0001 and add 1
1001: – or just flip the bits of 0111 and add 1
1000: – or just flip the bits of 1000 and add 1
Properties
One representation of zero: 0000
An extra negative number: (this is -8, not -0)

8. Ranges of numbers Range (min to max) in N bits:
SM and 1C: -2^(N-1) -1 to +2^(N-1) -1
2C: -2^(N-1) to +2^(N-1) -1

9. Sign Extension #s are often cast into vars with more capacity
Sign extension (in all 3 representations): extend the sign bit to the left, and everything works out
la $t0,0x
addi $t1,$t0, 7
addi $t2,$t0, -7
R[rt] = R[rs] + SignExtImm
SignExtImm = {16{immediate[15]},immediate}

10. Summary Issues # of zeros Balance (and thus range)
Code
Sign-Magnitude
1’s Complement
2’s Complement
000 +0
001 +1
010 +2
011 +3
100 -0 -3 -4
101 -1 -2
110
111
Issues
# of zeros
Balance (and thus range)
Operations’ implementation

11. 2’s Complement Examples
32-bit signed numbers
= 0
= +1
= +2 …
= +2,147,483,646
= +2,147,483,647
= - 2,147,483,648 -2^31
= - 2,147,483,647
= - 2,147,483,646
= -3
= -2
= -1

12. Addition We can do binary addition just as we do decimal arithmetic
Examples in lecture
Can be simpler with 2’s complement (1C as well)
We don’t need to worry about the signs of the operands!

13. Subtraction Notice that subtraction can be done using addition Add 1
A – B = A + (-B)
We know how to negate a number
The hardware used for addition can be used for subtraction with a negating unit at one input
Add 1
Invert (“flip”) the bits

14. Signed versus Unsigned Operations
“unsigned” operations view the operands as positive numbers, even if the most significant bit is 1
Example: 1100 is 12_unsigned but -4_2C
Example: slt versus sltu
li $t0,-4
li $t1,10
slt $t3,$t0,$t $t3 = 1
sltu $t4,$t0,$t $t4 = 0 !!

15. Signed Overflow
Because we use a limited number of bits to represent a number, the result of an operation may not fit  “overflow”
No overflow when
We add two numbers with different signs
We subtract a number with the same sign
Overflow when
Adding two positive numbers yields a negative number
Adding two negative numbers yields a positive number
How about subtraction?

16. Overflow On an overflow, the CPU can In MIPS on green card:
Generate an exception
Set a flag in a status register
Do nothing
In MIPS on green card:
add, addi, sub: footnote (1) May cause overflow exception

17. Overflow with Unsigned Operations
addu, addiu, subu
Footnote (1) is not listed for these instructions on the green card
This tells us that, In MIPS, nothing is done on unsigned overflow
How could it be detected for, e.g., add?
Carry out of the most significant position (in some architectures, a condition code is set on unsigned overflow, which IS the carry out from the top position)

18. Branch Instructions: Branching Backwards
# $t3 = ; $t4 =
li $t0,0 li $t3,1 li $t4, 1
loop: addi $t3,$t3,2
addi $t4,$t4,3
addi $t0,$t0,1
slti $t5,$t0,4
bne $t5,$zero,loop machine code: 0x15a0fffc
BranchAddr = {14{imm[15]}, imm, 2’b0}

19. 1-bit Adder With a fully functional single-bit adder 3 inputs
We can build a wider adder by linking many one-bit adders
3 inputs
A: input A
B: input B
Cin: input C (carry in)
2 outputs
S: sum
Cout: carry out

20. Implementing an Adder
Solve how S can be represented by way of A, B, and Cin
Also solve for Cout
Input
Output A B
Cin S
Cout 1

21. Boolean Logic formulas
Input
Output A B
Cin S
Cout 1
S = A’B’Cin+A’BCin’+AB’Cin’+ABCin
Cout = AB+BCin+ACin
Can implement the adder using logic gates

22. Logic Gates 2-input AND Y=A&B Y=A|B 2-input OR 2-input NAND Y=~(A&B)
2-input NOR
Y=~(A|B) Y B

23. Implementation in logic gates
Cout = AB+BCin+ACin
We’ll see more boolean logic and circuit implementation when we get to Appendix B
OR GATES
AND GATES

24. N-bit Adder An N-bit adder can be constructed with N one-bit adders
(0)
An N-bit adder can be constructed with N one-bit adders
A carry generated in one stage is propagated to the next (“ripple carry adder”)
3 inputs
A: N-bit input A
B: N-bit input B
Cin: input C (carry in)
2 outputs
S: N-bit sum
Cout: carry out

25. N-bit Ripple-Carry Adder
(0)
(0)
(1) 1 …

26. Multiplication
More complicated operation, so more complicated circuits
Outline
Human longhand, to remind ourselves of the steps involved
Multiplication hardware
Text has 3 versions, showing evolution to help you better understand how the circuits work

27. Multiplication Here – see what book says
More complicated than addition
A straightforward implementation will involve shifts and adds
More complex operation can lead to
More area (on silicon) and/or
More time (multiple cycles or longer clock cycle time)
Let’s begin from a simple, straightforward method

28. Straightforward Algorithm
(multiplicand) x
(multiplier)

29. Implementation 1

30. Implementation 2

31. Implementation 3

32. Example Let’s do 0010 x 0110 (2 x 6), unsigned Iteration Multiplicand
Implementation 3
Step
Product
0010
initial values 1
1: 0 -> no op
2: shift right 2
1: 1 -> product = product + multiplicand 3 4

33. Binary Division Dividend = Divider  Quotient + Remainder
Even more complicated
Still, it can be implemented by way of shifts and addition/subtraction
We will study a method based on the paper-and-pencil method
We confine our discussions to unsigned numbers only

34. Implementation – Figure 3.10

35. Algorithm (figure 3.11) Size of dividend is 2 * size of divisor
Initialization:
quotient register = 0
remainder register = dividend
divisor register = divisor in left half

36. Algorithm continued Repeat for 33 iterations (size divisor + 1):
Subtract the divisor register from the remainder register and place the result in the remainder register
If Remainder >= 0:
Shift quotient register left, placing 1 in bit 0
Else:
Undo the subtraction; shift quotient register left, placing 0 in bit 0
Shift divisor register right 1 bit
Example in lecture and figure 3.12

37. Floating-Point (FP) Numbers
Computers need to deal with real numbers
Fraction (e.g., )
Very small number (e.g., )
Very large number (e.g., 1011)
Components: sign, exponent, mantissa
(-1)signmantissa2exponent
More bits for mantissa gives more accuracy
More bits for exponent gives wider range
A case for FP representation standard
Portability issues
Improved implementations
 IEEE754 standard

38. Binary Fractions for Humans
Lecture: binary fractions and their decimal equivalents
Lecture: translating decimal fractions into binary
Lecture: idea of normalized representation
Then we’ll go on with IEEE standard floating point representation

39. IEEE 754 A standard for FP representation in computers
Single precision (32 bits): 8-bit exponent, 23-bit mantissa
Double precision (64 bits): 11-bit exponent, 52-bit mantissa
Leading “1” in mantissa is implicit (since the mantissa is normalized, the first digit is always a 1…why waste a bit storing it?)
Exponent is “biased” for easier sorting of FP numbers
sign
exponent
Fraction (or mantissa)
M-1
N-1
N-2 M

40. “Biased” Representation
We’ve looked at different binary number representations so far
Sign-magnitude
1’s complement
2’s complement
Now one more representation: biased representation
000…000 is the smallest number
111…111 is the largest number
To get the real value, subtract the “bias” from the bit pattern, interpreting bit pattern as an unsigned number
Representation = Value + Bias
Bias for “exponent” field in IEEE 754
127 (single precision)
1023 (double precision)

41. IEEE 754 A standard for FP representation in computers
Single precision (32 bits): 8-bit exponent, 23-bit mantissa
Double precision (64 bits): 11-bit exponent, 52-bit mantissa
Leading “1” in mantissa is implicit
Exponent is “biased” for easier sorting of FP numbers
All 0s is the smallest, all 1s is the largest
Bias of 127 for single precision and 1023 for double precision
Getting the actual value: (-1)sign(1+significand)2(exponent-bias)
sign
exponent
significand (or mantissa)
M-1
N-1
N-2 M

42. IEEE 754 Example -0.75ten Same as -3/4 In binary -11/100 = -0.11
In normalized binary -1.1twox2-1
In IEEE 754 format
sign bit is 1 (number is negative!)
mantissa is 0.1 (1 is implicit!)
exponent is -1 (or 126 in biased representation)
sign
8-bit exponent
23-bit significand (or mantissa) 22 31 30 23 1 …

43. IEEE 754 Encoding Revisited
Single Precision
Double Precision
Represented Object
Exponent
Fraction
non-zero
+/- denormalized number
1~254
anything
1~2046
+/- floating-point numbers
255
2047
+/- infinity
NaN (Not a Number)

44. FP Operations Notes Operations are more complex We have “underflow”
We should correctly handle sign, exponent, significand
We have “underflow”
Accuracy can be a big problem
IEEE 754 defines two extra bits to keep temporary results accurately: guard bit and round bit
Four rounding modes
Positive divided by zero yields “infinity”
Zero divided by zero yields “Not a Number” (NaN)
Implementing the standard can be tricky
Not using the standard can become even worse
See text for 80x86 and Pentium bug!

45. Floating-Point Addition
1. Shift smaller
number to make
exponents match
2. Add the significands
3. Normalize sum
Overflow or underflow? Yes: exception
no:
Round the significand
If not still normalized,
Go back to step 3
0.5ten – ten
=1.000two2-1 – 1.110two2-2

46. Floating-Point Multiplication
(1.000two2-1)(-1.110two2-2)
1. Add exponents and
subtract bias
2. Multiply the significands
3. Normalize the product
4: overflow? If yes,
raise exception
5. Round the significant to
appropriate # of bits
6. If not still normalized, go
back to step 3
7. Set the sign of the result

47. Floating Point Instructions in MIPS
.data
nums: .float 0.75,15.25,7.625
.text
la $t0,nums
lwc1 $f0,0($t0)
lwc1 $f1,4($t0)
add.s $f2,$f0,$f1
# = 16.0 = binary = 1.0 * 2^4
#f2: = 0x
swc1 $f2,12($t0)
# c now contains that number
# Click on coproc1 in Mars to see the $f registers

48. Another Example .data nums: .float 0.75,15.25,7.625 .text
loop: la $t0,nums
lwc1 $f0,0($t0)
lwc1 $f1,4($t0)
c.eq.s $f0,$f # cond = 0
bc1t label # no branch
c.lt.s $f0,$f # cond = 1
bc1t label # does branch
add.s $f3,$f0,$f1
label: add.s $f2,$f0,$f1
c.eq.s $f2,$f0
bc1f loop # branch (infinite loop)
#bottom of the coproc1 display shows condition bits

49. nums: .double 0.75,15.25,7.625,0.75
#0.75 = .11-bin. exponent is -1 (1022 biased). significand is
# = 0x3fe
la $t0,nums
lwc1 $f0,0($t0)
lwc1 $f1,4($t0)
lwc1 $f2,8($t0)
lwc1 $f3,12($t0)
add.d $f4,$f0,$f2
#{$f5,$f4} = {$f1,$f0} + {$f2,$f1}; = 16 = 1.0-bin * 2^4
# = 0x
# value value value value+c
# 0x x3fe x x402e8000
# float double
# $f0 0x x3fe
# $f x3fe80000
# $f2 0x x402e
# $f3 0x402e8000
# $f x x
# $f5 0x

50. Guard and Round bits To round accurately, hardware needs extra bits
IEEE 274 keeps extra bits on the right during intermediate additions
guard and round bits

51. Example (in decimal) With Guard and Round bits
2.56 * 10^ * 10^2
Assume 3 significant digits
* 10^ * 10^2
[guard=5; round=6]
Round step 1: 2.366
Round step 2: 2.37

52. Example (in decimal) Without Guard and Round bits
2.56 * 10^ * 10^2
* 10^ * 10^2
But with 3 sig digits and no extra bits:
= 2.36
So, we are off by 1 in the last digit