1. Computer Architecture
Chapter 5
Memory Hierarchy Design
Prof. Jerry Breecher
CSCI 240
Fall 2003

2. Chapter Overview 5.1 Introduction 5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
Chap. 5 - Memory

3. The Big Picture: Where are We Now?
Introduction
The Big Picture: Where are We Now?
5.1 Introduction
5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
The Five Classic Components of a Computer
Control
Datapath
Memory
Processor
Input
Output
Topics In This Chapter:
SRAM Memory Technology
DRAM Memory Technology
Memory Organization
Chap. 5 - Memory

4. The Big Picture: Where are We Now?
Introduction
The Big Picture: Where are We Now?
Capacity Speed (latency)
Logic: 2x in 3 years 2x in 3 years
DRAM: 4x in 3 years 2x in 10 years
Disk: 4x in 3 years 2x in 10 years
Technology Trends
DRAM
Year Size Cycle Time
Kb 250 ns
Kb 220 ns
Mb 190 ns
Mb 165 ns
Mb 145 ns
Mb 120 ns
Here is a table showing you quantitatively what I mean by high density.
In 1980, the biggest DRAM chip you can buy has around 64Kb on it and their cycle time is around 250ns.
This year you can buy 64 Mb DRAMs chips, that is an order of magnitude bigger than those back in with a speed that is twice as fast.
The general rule for DRAM has been quadruple in size every 3 years.
We will talk about DRAM cycle time later today. For now, I want you to point out an important point: The logic speed of your processor is doubling every 3 years but the DRAM speed only gets 40% improvement every 10 years.
This mean DRAM speed relative to your processor is getting slower every day.
That is why we believe Memory System design will become more and more important in the future because getting to your DRAM will become one of the biggest bottlenecks.
+2 = 28 min. (Y:08)
1000:1!
2:1!
Chap. 5 - Memory

5. Who Cares About the Memory Hierarchy?
Introduction
The Big Picture: Where are We Now?
Processor-DRAM Memory Gap (latency)
Who Cares About the Memory Hierarchy?
µProc
60%/yr.
(2X/1.5yr)
DRAM
9%/yr.
(2X/10 yrs) 1 10
100
1000
1980
1981
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
CPU
1982
Processor-Memory
Performance Gap: (grows 50% / year)
Performance
Time
“Moore’s Law”
Y-axis is performance
X-axis is time
Latency
Cliché:
Not e that x86 didn’t have cache on chip until 1989
Chap. 5 - Memory

6. Today’s Situation: Microprocessor
Introduction
The Big Picture: Where are We Now?
Today’s Situation: Microprocessor
Rely on caches to bridge gap
Microprocessor-DRAM performance gap
time of a full cache miss in instructions executed
1st Alpha (7000): 340 ns/5.0 ns =  68 clks x 2 or 136 instructions
2nd Alpha (8400): 266 ns/3.3 ns =  80 clks x 4 or 320 instructions
3rd Alpha (t.b.d.): 180 ns/1.7 ns =108 clks x 6 or 648 instructions
1/2X latency x 3X clock rate x 3X Instr/clock  ­5X
1st generation
Latency 1/2
but Clock rate 3X and IPC is 3X
Now move to other 1/2 of industry
Chap. 5 - Memory

7. Levels of the Memory Hierarchy
Introduction
The Big Picture: Where are We Now?
Levels of the Memory Hierarchy
CPU Registers
100s Bytes
1s ns
Cache
K Bytes
4 ns
1-0.1 cents/bit
Main Memory
M Bytes
100ns- 300ns
$ cents /bit
Disk
G Bytes, 10 ms (10,000,000 ns)
cents/bit -5 -6
Capacity
Access Time
Cost
Tape
infinite
sec-min 10 -8
Registers
Memory
Instr. Operands
Blocks
Pages
Files
Staging
Xfer Unit
prog./compiler
1-8 bytes
cache cntl
8-128 bytes OS
512-4K bytes
user/operator
Mbytes
Upper Level
Lower Level
faster
Larger
Chap. 5 - Memory

8. The ABCs of Caches In this section we will:
5.1 Introduction
5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
In this section we will:
Learn lots of definitions about caches – you can’t talk about something until you understand it (this is true in computer science at least!)
Answer some fundamental questions about caches:
Q1: Where can a block be placed in the upper level? (Block placement)
Q2: How is a block found if it is in the upper level? (Block identification)
Q3: Which block should be replaced on a miss? (Block replacement)
Q4: What happens on a write? (Write strategy)
Chap. 5 - Memory

9. The Principle of Locality
The ABCs of Caches
Definitions
The Principle of Locality
The Principle of Locality:
Program access a relatively small portion of the address space at any instant of time.
Two Different Types of Locality:
Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon (e.g., loops, reuse)
Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon (e.g., straightline code, array access)
Last 15 years, HW relied on locality for speed
The principle of locality states that programs access a relatively small portion of the address space at any instant of time.
This is kind of like in real life, we all have a lot of friends. But at any given time most of us can only keep in touch with a small group of them.
There are two different types of locality: Temporal and Spatial. Temporal locality is the locality in time which says if an item is referenced, it will tend to be referenced again soon.
This is like saying if you just talk to one of your friends, it is likely that you will talk to him or her again soon.
This makes sense. For example, if you just have lunch with a friend, you may say, let’s go to the ball game this Sunday. So you will talk to him again soon.
Spatial locality is the locality in space. It says if an item is referenced, items whose addresses are close by tend to be referenced soon.
Once again, using our analogy. We can usually divide our friends into groups. Like friends from high school, friends from work, friends from home.
Let’s say you just talk to one of your friends from high school and she may say something like: “So did you hear so and so just won the lottery.”
You probably will say NO, I better give him a call and find out more.
So this is an example of spatial locality. You just talked to a friend from your high school days. As a result, you end up talking to another high school friend. Or at least in this case, you hope he still remember you are his friend.
+3 = 10 min. (X:50)
Chap. 5 - Memory

10. Memory Hierarchy: Terminology
The ABCs of Caches
Definitions
Memory Hierarchy: Terminology
Hit: data appears in some block in the upper level (example: Block X)
Hit Rate: the fraction of memory access found in the upper level
Hit Time: Time to access the upper level which consists of
RAM access time + Time to determine hit/miss
Miss: data needs to be retrieve from a block in the lower level (Block Y)
Miss Rate = 1 - (Hit Rate)
Miss Penalty: Time to replace a block in the upper level +
Time to deliver the block the processor
Hit Time << Miss Penalty (500 instructions on 21264!)
A HIT is when the data the processor wants to access is found in the upper level (Blk X).
The fraction of the memory access that are HIT is defined as HIT rate.
HIT Time is the time to access the Upper Level where the data is found (X). It consists of:
(a) Time to access this level.
(b) AND the time to determine if this is a Hit or Miss.
If the data the processor wants cannot be found in the Upper level. Then we have a miss and we need to retrieve the data (Blk Y) from the lower level.
By definition (definition of Hit: Fraction), the miss rate is just 1 minus the hit rate.
This miss penalty also consists of two parts:
(a) The time it takes to replace a block (Blk Y to BlkX) in the upper level.
(b) And then the time it takes to deliver this new block to the processor.
It is very important that your Hit Time to be much much smaller than your miss penalty. Otherwise, there will be no reason to build a memory hierarchy.
+2 = 14 min. (X:54)
Lower Level
Memory
To Processor
Upper Level
Memory
Blk X
From Processor
Blk Y
Chap. 5 - Memory

11. The ABCs of Caches Definitions Cache Measures
Hit rate: fraction found in that level
So high that usually talk about Miss rate
Miss rate fallacy: as MIPS to CPU performance, miss rate to average memory access time in memory
Average memory-access time = Hit time + Miss rate x Miss penalty (ns or clocks)
Miss penalty: time to replace a block from lower level, including time to replace in CPU
access time: time to lower level
= f(latency to lower level)
transfer time: time to transfer block
=f(Bandwidth between upper & lower levels)
Chap. 5 - Memory

12. Simplest Cache: Direct Mapped
The ABCs of Caches
Definitions
Memory Address
Memory
Simplest Cache: Direct Mapped
4 Byte Direct Mapped Cache 1
Cache Index 2 3 1 4 2 5 3 6 7 8
Location 0 can be occupied by data from:
Memory location 0, 4, 8, ... etc.
In general: any memory location whose 2 LSBs of the address are 0s
Address<1:0> => cache index
Which one should we place in the cache?
How can we tell which one is in the cache? 9 A
Let’s look at the simplest cache one can build. A direct mapped cache that only has 4 bytes.
In this direct mapped cache with only 4 bytes, location 0 of the cache can be occupied by data form memory location 0, 4, 8, C, ... and so on.
While location 1 of the cache can be occupied by data from memory location 1, 5, 9, ... etc.
So in general, the cache location where a memory location can map to is uniquely determined by the 2 least significant bits of the address (Cache Index).
For example here, any memory location whose two least significant bits of the address are 0s can go to cache location zero.
With so many memory locations to chose from, which one should we place in the cache?
Of course, the one we have read or write most recently because by the principle of temporal locality, the one we just touch is most likely to be the one we will need again soon.
Of all the possible memory locations that can be placed in cache Location 0, how can we tell which one is in the cache?
+2 = 22 min. (Y:02) B C D E F
Chap. 5 - Memory

13. 1 KB Direct Mapped Cache, 32B blocks
The ABCs of Caches
Definitions
1 KB Direct Mapped Cache, 32B blocks
For a 2 ** N byte cache:
The uppermost (32 - N) bits are always the Cache Tag
The lowest M bits are the Byte Select (Block Size = 2 ** M)
Cache Index 1 2 3 :
Cache Data
Byte 0 4 31
Cache Tag
Example: 0x50
Ex: 0x01
0x50
Stored as part
of the cache “state”
Valid Bit
Byte 1
Byte 31
Byte 32
Byte 33
Byte 63
Byte 992
Byte 1023
Byte Select
Ex: 0x00 9
Let’s use a specific example with realistic numbers: assume we have a 1 KB direct mapped cache with block size equals to 32 bytes.
In other words, each block associated with the cache tag will have 32 bytes in it (Row 1).
With Block Size equals to 32 bytes, the 5 least significant bits of the address will be used as byte select within the cache block.
Since the cache size is 1K byte, the upper 32 minus 10 bits, or 22 bits of the address will be stored as cache tag.
The rest of the address bits in the middle, that is bit 5 through 9, will be used as Cache Index to select the proper cache entry.
+2 = 30 min. (Y:10)
Chap. 5 - Memory

14. Simplest Cache: Direct Mapped
The ABCs of Caches
Definitions
Memory Address
Memory
Simplest Cache: Direct Mapped
16K Byte Direct Mapped Cache 1
Cache Index 2
~~~~~~~~~~~~~ 1
16384 ~ 5
511 6 31 14 13 5 4
~~~~~~~~~~~~~
16384
00000
32768 9 31 14 13 5 4 A
Let’s look at the simplest cache one can build. A direct mapped cache that only has 4 bytes.
In this direct mapped cache with only 4 bytes, location 0 of the cache can be occupied by data form memory location 0, 4, 8, C, ... and so on.
While location 1 of the cache can be occupied by data from memory location 1, 5, 9, ... etc.
So in general, the cache location where a memory location can map to is uniquely determined by the 2 least significant bits of the address (Cache Index).
For example here, any memory location whose two least significant bits of the address are 0s can go to cache location zero.
With so many memory locations to chose from, which one should we place in the cache?
Of course, the one we have read or write most recently because by the principle of temporal locality, the one we just touch is most likely to be the one we will need again soon.
Of all the possible memory locations that can be placed in cache Location 0, how can we tell which one is in the cache?
+2 = 22 min. (Y:02)
~~~~~~~~~~~~~
16415
11111
49152 D 31 14 13 5 4 E
16416
00000
~~~~~~~~~~~~~
Chap. 5 - Memory

15. Simplest Cache: Direct Mapped
The ABCs of Caches
Definitions
Memory Address
Memory
Simplest Cache: Direct Mapped 31 14 13 5 4 1
16384
00000 2
~~~~~~~~~~~~~ 31 14 13 5 4
16384 5
32768
00000 6
~~~~~~~~~~~~~ 31 14 13 5 4
32768
49152
00000 9 A
Let’s look at the simplest cache one can build. A direct mapped cache that only has 4 bytes.
In this direct mapped cache with only 4 bytes, location 0 of the cache can be occupied by data form memory location 0, 4, 8, C, ... and so on.
While location 1 of the cache can be occupied by data from memory location 1, 5, 9, ... etc.
So in general, the cache location where a memory location can map to is uniquely determined by the 2 least significant bits of the address (Cache Index).
For example here, any memory location whose two least significant bits of the address are 0s can go to cache location zero.
With so many memory locations to chose from, which one should we place in the cache?
Of course, the one we have read or write most recently because by the principle of temporal locality, the one we just touch is most likely to be the one we will need again soon.
Of all the possible memory locations that can be placed in cache Location 0, how can we tell which one is in the cache?
+2 = 22 min. (Y:02)
~~~~~~~~~~~~~
Tag
Loc. In
Cache
Line
49152
Index D E
~~~~~~~~~~~~~
Chap. 5 - Memory

16. The ABCs of Caches Definitions Memory Address Memory Set Associative
4 Byte 2-way Set Associative Cache 1
Cache Index 2 3 1 4 2 5 3 6 7 8
Location 0 can be occupied by data from:
Memory location 0, 2, 4, 6, 8, ... etc.
In general: any memory location whose 1 LSBs of the address are 0s
Address<0> => cache index
Which one should we place in the cache?
How can we tell which one is in the cache? 9 A
Let’s look at the simplest cache one can build. A direct mapped cache that only has 4 bytes.
In this direct mapped cache with only 4 bytes, location 0 of the cache can be occupied by data form memory location 0, 4, 8, C, ... and so on.
While location 1 of the cache can be occupied by data from memory location 1, 5, 9, ... etc.
So in general, the cache location where a memory location can map to is uniquely determined by the 2 least significant bits of the address (Cache Index).
For example here, any memory location whose two least significant bits of the address are 0s can go to cache location zero.
With so many memory locations to chose from, which one should we place in the cache?
Of course, the one we have read or write most recently because by the principle of temporal locality, the one we just touch is most likely to be the one we will need again soon.
Of all the possible memory locations that can be placed in cache Location 0, how can we tell which one is in the cache?
+2 = 22 min. (Y:02) B C D E F
Chap. 5 - Memory

17. The ABCs of Caches Definitions Memory Address Memory
Set Associative Cache
16K Byte 4-way Set Associative Cache
~~~~~~~~~~~~~
Cache Index
4096
~~~~~~~~~~~~~ 1
Why???
8192 ~
128
12288 31 14 13 5 4
16384
00000
16384
Direct Mapped
20480
Let’s look at the simplest cache one can build. A direct mapped cache that only has 4 bytes.
In this direct mapped cache with only 4 bytes, location 0 of the cache can be occupied by data form memory location 0, 4, 8, C, ... and so on.
While location 1 of the cache can be occupied by data from memory location 1, 5, 9, ... etc.
So in general, the cache location where a memory location can map to is uniquely determined by the 2 least significant bits of the address (Cache Index).
For example here, any memory location whose two least significant bits of the address are 0s can go to cache location zero.
With so many memory locations to chose from, which one should we place in the cache?
Of course, the one we have read or write most recently because by the principle of temporal locality, the one we just touch is most likely to be the one we will need again soon.
Of all the possible memory locations that can be placed in cache Location 0, how can we tell which one is in the cache?
+2 = 22 min. (Y:02)
24576 31 12 11 5 4
16384
00000
~~~~~~~~~~~~~
4-Way Set Associative
Chap. 5 - Memory

18. 4 -Way Set Associative Cache
The ABCs of Caches
Definitions
Memory Address
Memory
4 -Way Set Associative Cache 31 12 11 5 4
~~~~~~~~~~~~~
16384
4096
00000
~~~~~~~~~~~~~ 31 12 11 5 4
8192
16415
11111
12288 31 12 11 5 4
8192
00000
16384 31 12 11 5 4
20480
Let’s look at the simplest cache one can build. A direct mapped cache that only has 4 bytes.
In this direct mapped cache with only 4 bytes, location 0 of the cache can be occupied by data form memory location 0, 4, 8, C, ... and so on.
While location 1 of the cache can be occupied by data from memory location 1, 5, 9, ... etc.
So in general, the cache location where a memory location can map to is uniquely determined by the 2 least significant bits of the address (Cache Index).
For example here, any memory location whose two least significant bits of the address are 0s can go to cache location zero.
With so many memory locations to chose from, which one should we place in the cache?
Of course, the one we have read or write most recently because by the principle of temporal locality, the one we just touch is most likely to be the one we will need again soon.
Of all the possible memory locations that can be placed in cache Location 0, how can we tell which one is in the cache?
+2 = 22 min. (Y:02)
12288
00000
24576 31 12 11 5 4
16416
00000
~~~~~~~~~~~~~
4-Way Set Associative
Chap. 5 - Memory

19. Q1: Where Can A Block Be Placed In A Cache?
The ABCs of Caches
Q1: Where Can A Block Be Placed In A Cache?
Block 12 placed in 8 block cache:
Fully associative, direct mapped, 2-way set associative
S.A. Mapping = Block Number Modulo Number Sets
Memory
Chap. 5 - Memory

20. Two-way Set Associative Cache
The ABCs of Caches
Definitions
Two-way Set Associative Cache
N-way set associative: N entries for each Cache Index
N direct mapped caches operates in parallel (N typically 2 to 4)
Example: Two-way set associative cache
Cache Index selects a “set” from the cache
The two tags in the set are compared in parallel
Data is selected based on the tag result
Cache Data
Cache Block 0
Cache Tag
Valid :
Cache Index
Mux 1
Sel1
Sel0
Cache Block
Compare
Adr Tag OR
Hit
This is called a 2-way set associative cache because there are two cache entries for each cache index. Essentially, you have two direct mapped cache works in parallel.
This is how it works: the cache index selects a set from the cache. The two tags in the set are compared in parallel with the upper bits of the memory address.
If neither tag matches the incoming address tag, we have a cache miss.
Otherwise, we have a cache hit and we will select the data on the side where the tag matches occur.
This is simple enough. What is its disadvantages?
+1 = 36 min. (Y:16)
Chap. 5 - Memory

21. Disadvantage of Set Associative Cache
The ABCs of Caches
Definitions
Disadvantage of Set Associative Cache
N-way Set Associative Cache v. Direct Mapped Cache:
N comparators vs. 1
Extra MUX delay for the data
Data comes AFTER Hit/Miss
In a direct mapped cache, Cache Block is available BEFORE Hit/Miss:
Possible to assume a hit and continue. Recover later if miss.
Cache Data
Cache Block 0
Cache Tag
Valid :
Cache Index
Mux 1
Sel1
Sel0
Cache Block
Compare
Adr Tag OR
Hit
First of all, a N-way set associative cache will need N comparators instead of just one comparator (use the right side of the diagram for direct mapped cache).
A N-way set associative cache will also be slower than a direct mapped cache because of this extra multiplexer delay.
Finally, for a N-way set associative cache, the data will be available AFTER the hit/miss signal becomes valid because the hit/mis is needed to control the data MUX.
For a direct mapped cache, that is everything before the MUX on the right or left side, the cache block will be available BEFORE the hit/miss signal (AND gate output) because the data does not have to go through the comparator.
This can be an important consideration because the processor can now go ahead and use the data without knowing if it is a Hit or Miss. Just assume it is a hit.
Since cache hit rate is in the upper 90% range, you will be ahead of the game 90% of the time and for those 10% of the time that you are wrong, just make sure you can recover.
You cannot play this speculation game with a N-way set-associatvie cache because as I said earlier, the data will not be available to you until the hit/miss signal is valid.
+2 = 38 min. (Y:18)
Chap. 5 - Memory

22. Q2: How is a block found if it is in the cache?
The ABCs of Caches
Q2: How is a block found if it is in the cache?
Tag on each block
No need to check index or block offset
Increasing associativity shrinks index,
expands tag
Block Address
Block Offset
Tag
Index
This is Figure 5.3
Chap. 5 - Memory

23. Q3: Which block should be replaced on a cache miss?
The ABCs of Caches
Q3: Which block should be replaced on a cache miss?
Easy for Direct Mapped
Set Associative or Fully Associative:
Random
LRU (Least Recently Used)
Associativity: 2-way 4-way 8-way
Size LRU Random LRU Random LRU Random
16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0%
64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5%
256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12%
This is Figure 5.4
Chap. 5 - Memory

24. Q4: What happens on a write?
The ABCs of Caches
Q4: What happens on a write?
Write through—The information is written to both the block in the cache and to the block in the lower-level memory.
Write back—The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced.
is block clean or dirty?
Pros and Cons of each?
WT: read misses cannot result in writes
WB: no repeated writes to same location
WT always combined with write buffers so that don’t wait for lower level memory
Chap. 5 - Memory

25. Q4: What happens on a write?
The ABCs of Caches
Q4: What happens on a write?
Cache
Processor
DRAM
Write Buffer
A Write Buffer is needed between the Cache and Memory
Processor: writes data into the cache and the write buffer
Memory controller: write contents of the buffer to memory
Write buffer is just a FIFO:
Typical number of entries: 4
Works fine if: Store frequency (w.r.t. time) << 1 / DRAM write cycle
Memory system designer’s nightmare:
Store frequency (w.r.t. time) -> 1 / DRAM write cycle
Write buffer saturation
You are right, memory is too slow. We really didn't writ e to the memory directly. We are writing to a write buffer.
Once the data is written into the write buffer and assuming a cache hit, the CPU is done with the write. The memory controller will then move the write buffer’s contents to the real memory behind the scene.
The write buffer works as long as the frequency of store is not too high. Notice here, I am referring to the frequency with respect to time, not with respect to number of instructions.
Remember the DRAM cycle time we talked about last time. It sets the upper limit on how frequent you can write to the main memory.
If the store are too close together or the CPU time is so much faster than the DRAM cycle time, you can end up overflowing the write buffer and the CPU must stop and wait.
+2 = 60 min. (Y:40)
Chap. 5 - Memory

26. Write-miss Policy: Write Allocate versus Not Allocate
The ABCs of Caches
Q5:What happens on a write?
Write-miss Policy: Write Allocate versus Not Allocate
Assume: a 16-bit write to memory location 0x0 and causes a miss
Do we read in the block?
Yes: Write Allocate
No: Write Not Allocate
Cache Index 1 2 3 :
Cache Data
Byte 0 4 31
Cache Tag
Example: 0x00
Ex: 0x00
0x50
Valid Bit
Byte 1
Byte 31
Byte 32
Byte 33
Byte 63
Byte 992
Byte 1023
Byte Select 9
Let’s look at our 1KB direct mapped cache again.
Assume we do a 16-bit write to memory location 0x and causes a cache miss in our 1KB direct mapped cache that has 32-byte block select.
After we write the cache tag into the cache and write the 16-bit data into Byte 0 and Byte 1, do we have to read the rest of the block (Byte 2, 3, ... Byte 31) from memory?
If we do read the rest of the block in, it is called write allocate. But stop and think for a second. Is it really necessary to bring in the rest of the block on a write miss?
True, the principle of spatial locality implies that we are likely to access them soon.
But the type of access we are going to do is likely to be another write.
So if even if we do read in the data, we may end up overwriting them anyway so it is a common practice to NOT read in the rest of the block on a write miss.
If you don’t bring in the rest of the block, or use the more technical term, Write Not Allocate, you better have some way to tell the processor the rest of the block is no longer valid.
This bring us to the topic of sub-blocking.
+2 = 64 min. (Y:44)
Chap. 5 - Memory

27. The ABCs of Caches Cache Performance Suppose a processor executes at
Clock Rate = 1000 MHz (1 ns per cycle)
CPI = 1.0
50% arithmetic/logic, 30% load/store, 20% control
Suppose that 10% of memory operations get 100 cycle miss penalty
CPI = ideal CPI + average stalls time per instruction = 1.0(cycle)
+( 0.30 (data-operations/instruction) x 0.10 (miss/data-op) x 100 (cycle/miss) ) = 1.0 cycle cycle = 4.0 cycle
75 % of the time the processor is stalled waiting for memory!
a 1% instruction miss rate would add an additional 1.0 cycles to the CPI!
Ideal CPI
1.0
Data Miss
1.5
Inst Miss
0.5
Chap. 5 - Memory

28. The ABCs of Caches Cache Performance Example Pages 384-5
Which has a lower miss rate:
A 16-KB instruction cache with a 16-KB data cache, or
A 32-KB unified cache?
Assume a hit takes 1 clock cycle and the miss penalty is 50 cycles.
Assume a load or store takes 1 extra clock cycle on a unified cache since there is only one cache port.
Assume 75% of memory accesses are instruction references.
(75% X 0.64%) + (25% X 6.47%) = 2.10%
Average memory access time (split)
= 75% X ( % X 50) + 25% X ( % X 50) = = 2.05
Average memory access time(unified)
= 75% X ( % X 50) + 25% X ( % X 50)
= = 2.24
Size
Instruction Cache
Data Cache
Unified Cache
8 KB
1.10%
10.19%
4.57%
16KB
0.64%
6.47%
2.87%
32 KB
0.39%
4.82%
1.99%
64KB
0.15%
3.77%
1.35%
Chap. 5 - Memory

29. Improving Cache Performance
The ABCs of Caches
Improving Cache Performance
The next few sections look at ways to improve cache and memory access times.
Average Memory Access Time = Hit Time + Miss Rate * Miss Penalty
Does this equation
make sense??
Section 5.5
Section 5.3
Section 5.4
Chap. 5 - Memory

30. Classifying Misses: 3 Cs
Reducing Cache Misses
Classifying Misses: 3 Cs
5.1 Introduction
5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
Compulsory—The first access to a block is not in the cache, so the block must be brought into the cache. Also called cold start misses or first reference misses. (Misses in even an Infinite Cache)
Capacity—If the cache cannot contain all the blocks needed during execution of a program, capacity misses will occur due to blocks being discarded and later retrieved. (Misses in Fully Associative Size X Cache)
Conflict—If block-placement strategy is set associative or direct mapped, conflict misses (in addition to compulsory & capacity misses) will occur because a block can be discarded and later retrieved if too many blocks map to its set. Also called collision misses or interference misses. (Misses in N-way Associative, Size X Cache)
Chap. 5 - Memory

31. 3Cs Absolute Miss Rate (SPEC92)
Reducing Cache Misses
Classifying Misses: 3 Cs
3Cs Absolute Miss Rate (SPEC92)
Conflict
Compulsory vanishingly
small
Chap. 5 - Memory

32. Classifying Misses: 3 Cs
Reducing Cache Misses
Classifying Misses: 3 Cs
2:1 Cache Rule
miss rate 1-way associative cache size X = miss rate 2-way associative cache size X/2
Conflict
Chap. 5 - Memory

33. Classifying Misses: 3 Cs
Reducing Cache Misses
Classifying Misses: 3 Cs
3Cs Relative Miss Rate
Conflict
Flaws: for fixed block size
Good: insight => invention
Chap. 5 - Memory

34. Reducing Cache Misses 1. Larger Block Size
Using the principle of locality.
The larger the block, the greater the
chance parts of it will be used again.
Size of Cache
Chap. 5 - Memory

35. Reducing Cache Misses 2. Higher Associativity 2:1 Cache Rule:
Miss Rate Direct Mapped cache size N
= Miss Rate 2-way cache size N/2
But Beware: Execution time is the only final measure we can believe!
Will Clock Cycle time increase as a result of having a more complicated cache?
Hill [1988] suggested hit time for 2-way vs. 1-way is: external cache +10%, internal + 2%
Chap. 5 - Memory

36. Example: Avg. Memory Access Time vs. Miss Rate
Reducing Cache Misses
2. Higher Associativity
Example: Avg. Memory Access Time vs. Miss Rate
The time to access memory has several components. The equation is:
Average Memory Access Time = Hit Time + Miss Rate X Miss Penalty
The miss penalty is 50 cycles.
See data on next page.
Associativity
Clock Cycle Time 1
1.00 2
1.10 3
1.12 8
1.14
Result
Chap. 5 - Memory

37. Example: Avg. Memory Access Time vs. Miss Rate
Reducing Cache Misses
2. Higher Associativity
Example: Avg. Memory Access Time vs. Miss Rate
Chap. 5 - Memory

38. Reducing Cache Misses 3. Victim Caches
How to combine fast hit time of direct mapped yet still avoid conflict misses?
Add buffer to place data discarded from cache
A 4-entry victim cache removed 20% to 95% of conflicts for a 4 KB direct mapped data cache
Used in Alpha, HP machines.
In effect, this gives the same behavior as associativity, but only on those cache lines that really need it.
Chap. 5 - Memory

39. Reducing Cache Miss Penalty
5.1 Introduction
5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
Time to handle a miss is becoming more and more the controlling factor. This is because of the great improvement in speed of processors as compared to the speed of memory.
Average Memory Access Time
= Hit Time + Miss Rate * Miss Penalty
Chap. 5 - Memory

40. Reducing Cache Miss Penalty
Prioritization of Read Misses over Writes
Write through with write buffers offer RAW conflicts with main memory reads on cache misses
If simply wait for write buffer to empty, might increase read miss penalty (old MIPS 1000 by 50% )
Check write buffer contents before read; if no conflicts, let the memory access continue
Write Back?
Read miss replacing dirty block
Normal: Write dirty block to memory, and then do the read
Instead copy the dirty block to a write buffer, then do the read, and then do the write
CPU stall less since restarts as soon as do read
Chap. 5 - Memory

41. Reducing Cache Miss Penalty
Sub Block Placement for Reduced Miss Penalty
Don’t have to load full block on a miss
Have valid bits per subblock to indicate valid
(Originally invented to reduce tag storage)
Subblocks
Valid Bits
Chap. 5 - Memory

42. Reducing Cache Miss Penalty
Early Restart and Critical Word First
Don’t wait for full block to be loaded before restarting CPU
Early restart—As soon as the requested word of the block arrives, send it to the CPU and let the CPU continue execution
Critical Word First—Request the missed word first from memory and send it to the CPU as soon as it arrives; let the CPU continue execution while filling the rest of the words in the block. Also called wrapped fetch and requested word first
Generally useful only in large blocks,
Spatial locality a problem; tend to want next sequential word, so not clear if benefit by early restart
block
Chap. 5 - Memory

43. Reducing Cache Miss Penalty
Second Level Caches
L2 Equations
Average Memory Access Time = Hit TimeL1 + Miss RateL1 x Miss PenaltyL1
Miss PenaltyL1 = Hit TimeL2 + Miss RateL2 x Miss PenaltyL2
Average Memory Access Time = Hit TimeL1
+ Miss RateL1 x (Hit TimeL2 + Miss RateL2 + Miss PenaltyL2)
Definitions:
Local miss rate— misses in this cache divided by the total number of memory accesses to this cache (Miss rateL2)
Global miss rate—misses in this cache divided by the total number of memory accesses generated by the CPU (Miss RateL1 x Miss RateL2)
Global Miss Rate is what matters
Chap. 5 - Memory

44. Comparing Local and Global Miss Rates
Reducing Cache Miss Penalty
Second Level Caches
Comparing Local and Global Miss Rates
32 KByte 1st level cache; Increasing 2nd level cache
Global miss rate close to single level cache rate provided L2 >> L1
Don’t use local miss rate
L2 not tied to CPU clock cycle!
Cost & A.M.A.T.
Generally Fast Hit Times and fewer misses
Since hits are few, target miss reduction
Linear Scale
Cache Size
Log Scale
Cache Size
Chap. 5 - Memory

45. Average Memory Access Time = Hit Time + Miss Rate * Miss Penalty
Reducing Hit Time
5.1 Introduction
5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
This is about how to reduce time to access data that IS in the cache.
What techniques are useful for quickly and efficiently finding out if data is in the cache, and if it is, getting that data out of the cache.
Average Memory Access Time
= Hit Time + Miss Rate * Miss Penalty
Chap. 5 - Memory

46. Small and Simple Caches
Reducing Hit Time
Small and Simple Caches
Why Alpha has 8KB Instruction and 8KB data cache + 96KB second level cache?
Small data cache and clock rate
Direct Mapped, on chip
Since most data DOES hit the cache, saving a cycle on data access in the cache is a significant result.
Chap. 5 - Memory

47. Avoid Address Translation During Indexing of Cache
Reducing Hit Time
Avoid Address Translation During Indexing of Cache
Send virtual address to cache? Called Virtually Addressed Cache or just Virtual Cache vs. Physical Cache
Every time process is switched logically must flush the cache; otherwise get false hits
Cost is time to flush + “compulsory” misses from empty cache
Dealing with aliases (sometimes called synonyms); Two different virtual addresses map to same physical address
I/O must interact with cache, so need virtual address
Solution to aliases
HW guarantees that every cache block has unique physical address
SW guarantee : lower n bits must have same address; as long as covers index field & direct mapped, they must be unique; called page coloring
Solution to cache flush
Add process identifier tag that identifies process as well as address within process: can’t get a hit if wrong process
Chap. 5 - Memory

48. How to do parallel operations with Virtually Addressed Caches
Reducing Hit Time
Avoid Address Translation During Indexing of Cache
How to do parallel operations with Virtually Addressed Caches
CPU TB $
MEM VA PA
Conventional
Organization
Virtually Addressed Cache
Translate only on miss
Synonym Problem
Tags
Overlap $ access
with VA translation:
requires $ index to
remain invariant
across translation
L2 $
Chap. 5 - Memory

49. Fast Cache Hits by Avoiding Translation: Process ID impact
Reducing Hit Time
Avoid Address Translation During Indexing of Cache
Fast Cache Hits by Avoiding Translation: Process ID impact
Black is uni-process
Light Gray is multi-process when flushing cache
Dark Gray is multi-process when using Process ID tag
Y axis: Miss Rates up to 20%
X axis: Cache size from 2 KB to 1024 KB
Chap. 5 - Memory

50. Pipelining Writes for Fast Write Hits
Reducing Hit Time
Pipelining Writes for Fast Write Hits
Pipeline Tag Check and Update Cache as separate stages; current write tag check & previous write cache update
Only STORES in the pipeline; empty during a miss Store r2, (r1) Check r1 Add -- Sub -- Store r4, (r3) M[r1]<-r2&
In shade is “Delayed Write Buffer”; must be checked on reads; either complete write or read from buffer
Check r3
Chap. 5 - Memory

51. Cache Optimization Summary
Technique MR MP HT Complexity
Larger Block Size + – 0 Higher Associativity + – 1 Victim Caches Pseudo-Associative Caches HW Prefetching of Instr/Data Compiler Controlled Prefetching Compiler Reduce Misses + 0
Priority to Read Misses Subblock Placement Early Restart & Critical Word 1st Non-Blocking Caches Second Level Caches + 2
Small & Simple Caches – + 0 Avoiding Address Translation Pipelining Writes + 1
miss rate
penalty
miss
hit time
Chap. 5 - Memory

52. Main Memory Performance of Main Memory:
Latency: Cache Miss Penalty
Access Time: time between request and word arrives
Cycle Time: time between requests
Bandwidth: I/O & Large Block Miss Penalty (L2)
Main Memory is DRAM: Dynamic Random Access Memory
Dynamic since needs to be refreshed periodically (8 ms, 1% time)
Addresses divided into 2 halves (Memory as a 2D matrix):
RAS or Row Access Strobe
CAS or Column Access Strobe
Cache uses SRAM: Static Random Access Memory
No refresh (6 transistors/bit vs. 1 transistor /bit, area is 10X)
Address not divided: Full addreess
Size: DRAM/SRAM ­ 4-8,
Cost/Cycle time: SRAM/DRAM ­ 8-16
Main Memory
5.1 Introduction
5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
Chap. 5 - Memory

53. Memory Technology & Organization
Main Memory
Memory Technology & Organization
Core Memory
“Out-of-Core”, “In-Core,” “Core Dump”?
“Core memory”?
Non-volatile, magnetic
Lost to 4 Kbit DRAM (today using 64Kbit DRAM)
Access time 750 ns, cycle time ns
Chap. 5 - Memory

54. DRAM logical organization (4 Mbit)
Main Memory
Memory Technology & Organization
DRAM logical organization (4 Mbit)
Column Decoder … 1 1
Sense
Amps & I/O
Data In
Memory
Array
A0…A1
Data Out
(2,048 x 2,048)
Address Buffer
Storage W
ord Line
Cell
Row Decoder
Square root of bits per RAS/CAS
Chap. 5 - Memory

55. DRAM logical organization (4 Mbit)
Main Memory
Memory Technology & Organization
DRAM logical organization (4 Mbit)
Block
Row Dec.
9 : 512
Row
Column
Addr
ess …
Block 0
Block 3
I/O D Q 2
8 I/Os
Column
Address
Row
Address
Chap. 5 - Memory

56. Memory Technology & Organization
Main Memory
Memory Technology & Organization
DRAM Performance
A 60 ns (tRAC) DRAM can
perform a row access only every 110 ns (tRC)
perform column access (tCAC) in 15 ns, but time between column accesses is at least 35 ns (tPC).
In practice, external address delays and turning around buses make it 40 to 50 ns
These times do not include the time to drive the addresses off the microprocessor nor the memory controller overhead!
Chap. 5 - Memory

57. Main Memory Performance
Simple:
CPU, Cache, Bus, Memory same width (32 or 64 bits)
Wide:
CPU/Mux 1 word; Mux/Cache, Bus, Memory N words (Alpha: 64 bits & 256 bits; UtraSPARC 512)
Interleaved:
CPU, Cache, Bus 1 word: Memory N Modules (4 Modules); example is word interleaved
Chap. 5 - Memory

58. Main Memory Performance
Timing model (word size is 32 bits)
1 to send address,
6 access time, 1 to send data
Cache Block is 4 words
Simple M.P = 4 x (1+6+1) = 32
Wide M.P = = 8
Interleaved M.P. = x1 = 11
Chap. 5 - Memory

59. Independent Memory Banks
Main Memory
Independent Memory Banks
Memory banks for independent accesses vs. faster sequential accesses
Multiprocessor
I/O
CPU with Hit under n Misses, Non-blocking Cache
Superbank: all memory active on one block transfer (or Bank)
Bank: portion within a superbank that is word interleaved …
Superbank
Bank
Chap. 5 - Memory

60. Virtual Memory
Permits a program's memory to be physically noncontiguous so it can be allocated from wherever available. This avoids fragmentation and compaction.
5.1 Introduction
5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
WHY VIRTUAL MEMORY?
We've previously required the entire logical space of the process to be in memory before the process could run. We will now look at alternatives to this.
Most code/data isn't needed at any instant, or even within a finite time - we can bring it in only as needed.
VIRTUES
Gives a higher level of multiprogramming
The program size isn't constrained (thus the term 'virtual memory'). Virtual memory allows very large logical address spaces.
Swap sizes smaller.
Chap. 5 - Memory

61. Virtual Memory Definitions
Virtual memory The conceptual separation of user logical memory from physical memory. Thus we can have large virtual memory on a small physical memory.
Individual Pages
Disk
Physical
Memory
Virtual
Memory
Memory
Map
Chap. 5 - Memory

62. Virtual Memory Paging Chap. 5 - Memory
Permits a program's memory to be physically noncontiguous so it can be allocated from wherever available. This avoids fragmentation and compaction.
Frames = physical blocks
Pages = logical blocks
Size of frames/pages is defined by hardware (power of 2 to ease calculations)
HARDWARE
An address is determined by:
page number ( index into table ) + offset
---> mapping into --->
base address ( from table ) + offset.
Chap. 5 - Memory

63. Virtual Memory
Paging
 Paging Example - 32-byte memory with 4-byte pages I j k l
0 a
1 b
2 c
3 d m n o p
4 e
5 f
6 g
7 h 12 16
Page Table
8 I
9 j
10 k
11 l a b c d
24 e f g h
12 m
13 n
14 o
15 p
Physical Memory 28
Logical Memory
Chap. 5 - Memory

64. IMPLEMENTATION OF THE PAGE TABLE
Virtual Memory
Paging
TLB
IMPLEMENTATION OF THE PAGE TABLE
A 32 bit machine can address 4 gigabytes which is 4 million pages (at 1024 bytes/page). WHO says how big a page is, anyway?
Could use dedicated registers (OK only with small tables.)
Could use a register pointing to table in memory (slow access.)
Cache or associative memory (TLB = Translation Lookaside Buffer): simultaneous search is fast and uses only a few registers.
TLB Hit
TLB Miss
Chap. 5 - Memory

65. Virtual Memory Paging Chap. 5 - Memory
IMPLEMENTATION OF THE PAGE TABLE
 Issues include:
key and value
hit rate % with 100 registers
add entry if not found
Effective access time = %fast * time_fast %slow * time_slow
Relevant times:
20 nanoseconds to search associative memory – the TLB.
200 nanoseconds to access memory and bring it into TLB for next time.
Calculate time of access:
hit = 1 search + 1 memory reference
miss = 1 search + 1 mem reference(of page table) + 1 mem reference.
Chap. 5 - Memory

66. Virtual Memory Paging Chap. 5 - Memory SHARED PAGES
Data occupying one physical page, but pointed to by multiple logical pages.
Useful for common code - must be write protected. (NO write-able data mixed with code.)
Extremely useful for read/write communication between processes.
Chap. 5 - Memory

67. Virtual Memory Paging Chap. 5 - Memory INVERTED PAGE TABLE:
One entry for each real page of memory.
Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page.
Essential when you need to do work on the page and must find out what process owns it.
Use hash table to limit the search to one - or at most a few - page table entries.
Chap. 5 - Memory

68. Virtual Memory Paging MULTILEVEL PAGE TABLE Chap. 5 - Memory
A means of using page tables for large address spaces.
Chap. 5 - Memory

69. Virtual Memory Paging < +
HARDWARE -- Must map a dyad (segment / offset) into one-dimensional address.
Segment Table
Limit Base
CPU
S D
MEMORY
Logical
Address
Yes
< +
Physical
Address No
Chap. 5 - Memory

70. Basic Issues in VM System Design
Virtual Memory
Questions about Memory
Basic Issues in VM System Design
Size of information blocks that are transferred from secondary to main storage (M)
Block of information brought into M, and M is full, then some region of M must be released to make room for the new block  replacement policy
Which region of M is to hold the new block --> placement policy
Missing item fetched from secondary memory only on the occurrence of a fault --> demand load policy
pages
reg
cache
mem
disk
frame
Chap. 5 - Memory

71. Questions about Memory
Virtual Memory
Questions about Memory
4 Questions for Virtual Memory
Q1: Where can a block be placed in the upper level? Fully Associative, Set Associative, Direct Mapped
Q2: How is a block found if it is in the upper level? Tag/Block
Q3: Which block should be replaced on a miss? Random, LRU
Q4: What happens on a write? Write Back or Write Through (with Write Buffer)
Chap. 5 - Memory

72. Virtual Address and a Cache
Virtual Memory
Techniques for Fast Address Translation
Virtual Address and a Cache VA PA
miss
Trans-
lation
Cache
Main
Memory
CPU
hit
data
It takes an extra memory access to translate VA to PA
This makes cache access very expensive, and this is the "innermost loop" that you want to go as fast as possible
Chap. 5 - Memory

73. Techniques for Fast Address Translation
Virtual Memory
Techniques for Fast Address Translation
A Brief Detour
Why access cache with PA at all? VA caches have a problem!
synonym / alias problem: two different virtual addresses map to same physical address => two different cache entries holding data for the same physical address!
For update: must update all cache entries with same
physical address or memory becomes inconsistent
Determining this requires significant hardware, essentially an
associative lookup on the physical address tags to see if you
have multiple hits; or
Software enforced alias boundary: same least significant bit of VA & PA > cache size
Chap. 5 - Memory

74. Techniques for Fast Address Translation
Virtual Memory
Techniques for Fast Address Translation
TLBs
A way to speed up translation is to use a special cache of recently
used page table entries -- this has many names, but the most
frequently used is Translation Lookaside Buffer or TLB
Virtual Address Physical Address Dirty Ref Valid Access
Really just a cache on the page table mappings
TLB access time comparable to cache access time
(much less than main memory access time)
Chap. 5 - Memory

75. Techniques for Fast Address Translation
Virtual Memory
Techniques for Fast Address Translation
TLBs
Just like any other cache, the TLB can be organized as fully associative, set associative, or direct mapped
TLBs are usually small, typically not more than entries even on high end machines. This permits fully associative lookup on these machines. Most mid-range machines use small n-way set associative organizations.
CPU
TLB
Lookup
Cache
Main
Memory VA PA
miss
hit
data
Trans-
lation
20 t t
1/2 t
Translation
with a TLB
Chap. 5 - Memory

76. Techniques for Fast Address Translation
Virtual Memory
Techniques for Fast Address Translation
TLBs
Machines with TLBs go one step further to reduce # cycles/cache access
They overlap the cache access with the TLB access:
high order bits of the VA are used to look in the TLB while low order bits are used as index into cache
Chap. 5 - Memory

77. Overlapped Cache & TLB Access
Virtual Memory
Techniques for Fast Address Translation
Overlapped Cache & TLB Access
TLB
Cache 10 2 00
4 bytes
index
1 K
page #
disp 20 12
assoc
lookup 32 PA
Hit/
Miss
Data =
IF cache hit AND (cache tag = PA) then deliver data to CPU
ELSE IF [cache miss OR (cache tag = PA)] and TLB hit THEN
access memory with the PA from the TLB
ELSE do standard VA translation
Chap. 5 - Memory

78. Problems With Overlapped TLB Access
Virtual Memory
Techniques for Fast Address Translation
Problems With Overlapped TLB Access
Overlapped access only works as long as the address bits used to
index into the cache do not change as the result of VA translation
This usually limits things to small caches, large page sizes, or high
n-way set associative caches if you want a large cache
Example: suppose everything the same except that the cache is
increased to 8 K bytes instead of 4 K: 11 2
cache
index 00
This bit is changed
by VA translation, but
is needed for cache
lookup 20 12
virt page #
disp
Solutions:
go to 8K byte page sizes;
go to 2 way set associative cache; or
SW guarantee VA[13]=PA[13] 1K
2 way set assoc cache 10
Chap. 5 - Memory 4 4

79. Protection and Examples
5.1 Introduction
5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
The Goal:
One process should not interfere with another
Process model
privileged kernel
independent user processes
Privileges vs policy
architecture provided primitives
OS implements policy
problems arise when h/w implements policy
Chap. 5 - Memory

80. Protection and Examples
Issues
Protection and Examples
Protection Primitives
user vs kernel
at least one privileged mode
special case of rings
usually implemented as mode bits
how do we switch to kernel mode?
protected ``gates''
change mode and continue at pre­determined address
h/w to compare mode bits to access rights
only access certain resources in kernel mode
Chap. 5 - Memory

81. Protection and Examples
Issues
Protection and Examples
Protection Primitives
base and bounds
privileged registers
base <= address <= bounds
segmentation
multiple base and bound registers
protection bits for each segment
page­level protection
protection bits in page entry table
cache them in TLB for speed
Chap. 5 - Memory

82. Protection and Examples
Protection on the Pentium
Pentium contains:
Four segments – a program can run in any of them.
Four segments – a program may or may not be able to touch data in a particular segment.
How would a user and an operating system use these features?
Chap. 5 - Memory

83. Protection and Examples
Protection on the Pentium
Segment register contains:
Base
Limit
Present
Readable
Writable
Chap. 5 - Memory

84. Summary 5.1 Introduction 5.2 The ABCs of Caches
5.3 Reducing Cache Misses
5.4 Reducing Cache Miss Penalty
5.5 Reducing Hit Time
5.6 Main Memory
5.7 Virtual Memory
5.8 Protection and Examples of Virtual Memory
Chap. 5 - Memory