1. Digital Logic Design Sequential circuits
Dr. Eng. Ahmed H. Madian
Dr. Eng. Ahmed H. Madian

2. Outlines Finite State Machine (FSM) Design of FSMs Analysis of FSMs
Registers
Dr. Eng. Ahmed H. Madian

3. Design of Sequential Circuits
The procedure of designing synchronous sequential circuits can be summarized as follows:
From the word description and specs of the desired operation, derive a state diagram for the circuit
Assign binary values to the states.
Obtain the binary-coded state table
Choose the type of flip-flops to be used.
Derive the simplified flip-flop input and output equations.
Draw the logic diagram.
Dr. Eng. Ahmed H. Madian

4. State tables
Table is another way to represent an FSM with an emphasis on exploring all Event/State combinations
Similar to the truth table
Doesn’t contain the system clock when specifying its transitions (it is implicit that transitions occur only when allowed by clock)
Unless different stated, all the transitions are occurring on the positive edge of the clock
Present State
Inputs
Next State
Outputs
Dr. Eng. Ahmed H. Madian

5. State Transition Diagrams
Used to visually represent any FSM
Emphasis is on identifying states and possible transitions
Circles represent States
Arrows represent Transitions
Transitions
1/0
Initial State S0 S1
Input/Output
0/0
0/0
1/0
0/0 S3
1/1 S2
State
Dr. Eng. Ahmed H. Madian

6. Design Example
Design a FSM that detects 3 or more consecutive ones from a serial input x.
3 ones detector Y X
Steps:
1. Understand the statement of the Specification
2. Obtain a state diagram of the FSM from the specification
3. Perform state assignment
4. Determine the number of flip flop (to represent 4 states => 2 flip flops)
5. Choose type of flip-flop if not given (for example we will choose D-FF)
Dr. Eng. Ahmed H. Madian

7. Our system will stop at S0 if the input to the system is always ‘0’
1. Derive state diagram S0 00
1/0 S1 01
0/0
Input/Output
We will begin with assumption that no input entered to system, we will give this state name S0
Our system will stop at S0 if the input to the system is always ‘0’
If the system has ‘1’ input a new states created which represent the state that you have only 1 we will call it S1
Dr. Eng. Ahmed H. Madian

8. 0/0
0/0 S0 00
1/0 S1 01
1/0 S2 10
0/0
0/0
1/1 S3 11
1/1
If the system was in state S1 and a ‘0’ entered the system, it must be returned to S0 as we are searching for 3 consecutive ones.
Else if another ‘1’ entered the system it will go to new state that represent existing of two ones consecutive we will call it S2.
If the system was in state S2 and ‘0’ entered the system it will return to S0.
Else if ‘1’ entered to the system it will move to a new state that represent the existing of three consecutive ones S3 and the output would be equal to y=‘1’.
If the system has more ones as an input it will continue at S3 and output y=‘1’
Finally, if we have input X=‘0’ to the system, it will goes to the starting state S0
Dr. Eng. Ahmed H. Madian

9. 2. Construct the state table
Present State
Input
Next State
Out FF Inputs A B X y DA DB 1
D–FF
Excitation Table
Q(t)
Q(t+1) D 1
Dr. Eng. Ahmed H. Madian

10. 3. Drive simplified State Equations
Note: Output here depends on the present state (A(t)) and input (x)
Dr. Eng. Ahmed H. Madian

11. 4: Implement the FSM
Dr. Eng. Ahmed H. Madian

12. FSM Circuit Analysis Start with schematic diagram
Need to determine how circuit works
Trace schematic, determine equations of operation
FF input equations
sequential circuit output equations
Create State transition table
Sequential circuit inputs, FFs are comb. logic inputs
Organize truth table as current state (FFs) and inputs
Create FF input, seq. Circuit output columns
From FF char. Tables, determine FF next state values
Dr. Eng. Ahmed H. Madian

13. Sequential Circuit Analysis (cont.)
Generate State Diagram
Circles (nodes) represent current or present state values
Lines (arcs) represent how state and output values change
Given the current state and current inputs, the next state and output values are indicated by the associated arc
State diagram can have different forms depending on the type of sequential circuit output.
Next
State
Value
Inputs/outputs
Present
State
Value
Dr. Eng. Ahmed H. Madian

14. Example Analyze the following sequential circuit
How to analyze any sequential circuit
You need to know :
State equation
State diagram
State table
Dr. Eng. Ahmed H. Madian

15. 1- Determine State equation
From the circuit get the logic equations of the input of flip-flops A(t+1) & B(t+1) and output y(t)
A(t+1)
(t)
FF input equations
A(t+1) = A(t)X(t)+B(t)X(t)
B(t+1) = A’(t)X(t)
Output equation
Y(t) = X’(t)(B(t)+A(t))
B(t+1)
(t)
(t)
Dr. Eng. Ahmed H. Madian

16. 2-Create State table
From logic equation & characteristics table of flip-flop create State table
FF input equations
A(t+1) = AX+BX
B(t+1) = A’X
Output equation
Y = X’(B+A)
D flip-flop characteristic table
Dr. Eng. Ahmed H. Madian

17. 3-Construct the state diagram
0/0
1/0
0/1 00 10
Input/Output
0/1
1/0
0/1
1/0 01 11
1/0
Dr. Eng. Ahmed H. Madian

18. Registers
There are also another applications for Flip-flops like Registers
“Register” is a small amount of storage available on the CPU whose contents can be accessed more quickly than storage available elsewhere. Typically, this specialized storage is not considered part of the normal memory range for the machine.
Registers are normally measured by the number of bits they can hold (ex. 8-bits or 32-bits register)
They have been implemented using individual flip-flops
Dr. Eng. Ahmed H. Madian

19. What’s the main structure of the register from inside
What’s the main structure of the register from inside? And what’s the types of registers?
Dr. Eng. Ahmed H. Madian

20. Registers
An n-bit register consists of a group n flip -flops capable of storing n bits of binary info.
All Flip-flops are connected to one clock source
Each flip-flop can store one bit of Info.
Clear signal during normal operation is set to high
The clear input is useful for clearing all the content of the register to all 0’s
Problem: Typically don’t want to load every clock
Solution: use a external signal to control the operation of the load
Dr. Eng. Ahmed H. Madian

21. Registers with Parallel Load1 1 1
Dr. Eng. Ahmed H. Madian

22. Shift Registers 1 Qb Qc Qa
A register capable of shifting its binary information in one or both direction is called a shift register
A chain of flip-flops in cascade 1 Qb Qc Qa SI
CLK Qa Qb
etc
Dr. Eng. Ahmed H. Madian

23. Universal Shift Registers
No Change
Shift Right
Shift Left
Parallel Load
Need a Clear and Clock S1 S2
Action
No Change 1
Shift Right
Shift Left
Parallel
Load
Dr. Eng. Ahmed H. Madian

24. Quiz 2 check the website for date and locations
Assignment 3 on the web site deadline will be next Wednesday
Dr. Eng. Ahmed H. Madian