1. ParaScale : Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling Sibin Mohan 1 Frank Mueller 1,William Hawkins 2, Michael Root 3, Christopher Healy 3, David Whalley 4 1 : North Carolina State University, Centre for Embedded Systems Research 2 : University of Illinois, Urbana-Champaign, 3 : Furman University, 4 : Florida State University

2. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 2 Outline  Motivation  Static Timing Analysis  Parametric Timing Analysis  Using Parametric Timing Analysis  Framework  Experiments and Results  Conclusion

3. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 3 Motivation  Worst-case execution time (wcet) obtained by Static timing analysis Dynamic timing methods (proven unsafe)  Static Timing Analysis Upper limits on loop bounds known at compile time Results in large overestimations Provides single numeric value  Places limits on real-time designers Type of code that may be used in tasks

4. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 4 Static Timing Analysis for( i = 0 ; i < n ; ++i ) Loop Body ; Consider the following piece of code… Value must be known at compile time Result : WCET = 1000 cycles (say)

5. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 5 Parametric Timing Analysis  Calculate : formula /closed form for WCET  Formula depends on number of loop iterations  Evaluated at run-time  Results used for… scheduling decisions power savings etc.

6. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 6 Parametric Timing Analysis (contd.) For the previous example… for( i = 0 ; i < n ; ++i ) Loop Body ; Result : WCET = 102 * n (say) Number of cycles to execute Loop Body for above example Value must be known prior to loop entry

7. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 7 Parametric Timing Analysis (contd.) In practice… for( i = 0 ; i < n ; ++i ) Loop Body ; Call IntraTaskScheduler(evaluate_loop_k(n)) ; int evaluate_loop_k( int loop_bound){ return ( 102 * loop_bound ) ; }

8. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 8 Flow of Parametric Timing Analysis C source file Parametric Timing Analyzer C source file annotated with Parametric Evaluation functions Has Parametric formula changed? YES Send Annotated C source file to Parametric Timing Analyzer NO Use Annotated C source file for execution on Simulator

9. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 9 Insert Parametric Formulae into Task Code Timing analysis of function with parametric loopLoop analyzed and parametric evaluation function generated Numerical Analysis of generated function completeTiming analysis if function with parametric loop complete

10. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 10 Use of Parametric Timing Analysis  Evaluate parametric expressions at run-time Based on actual loop bounds at run-time  Transfer control to dynamic scheduler  Newly-calculated WCET sent to scheduler Calculate savings in execution time  Savings exploited by scheduler to… admit additional tasks reduce operating frequency/voltage  save power

11. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 11 Unique advantages of our work  Exploit early knowledge of execution of tasks Especially knowledge about future execution of loops  Tightly bound execution for remainder of task  Intra-task DVS algorithm slows down processor As execution proceeds processor slowed down further Saves power!  Other DVS algorithms: Task execution sped up as deadlines approach

12. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 12 Framework C Source Files gcc PISA Compiler Numeric WCET Bound Numeric Timing Analyzer Instruction/data info p-compiler assembly Parametric Timing Analyzer C Source Files & Parametric Functions Scheduler Energy/power values Wattch Power Model SimpleScalar Simulator

13. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 13 Framework (contd.)  p-compiler Works on assembly files as input Extracts information about instructions and data  Timing Analyzers Numeric : provides constant, numeric WCET bound Parametric : provides parametric formulae as WCET  Schedulers Frequency/Voltage lowered during execution Set to levels for last executing task instance  SimpleScalar simulation framework Capable of handling multiple threads of execution Can be configured for simple processor, SMT, CMP, etc.

14. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 14 Experiments  Energy measurement techniques… Perfect Clock Gating (PCG) Perfect Clock Gating with Leakage (PCGL)  ParaScale Our combined intra-task and static inter-task DVS ParameterRange of Values Utilization20%, 50%, 80% Ratio WCET/PET * 1x, 2x, 5x, 10x, 15x, 20x Base DVS AlgorithmsStatic DVS Parametric ParaScale * Parametric Execution Time

15. Dec 5-8, 2005 15 Energy Consumption : 2x, PCG Energy consumptions, assuming no leakage, for various utilizations DVS Schemes Least consumption: ParaScale (for all cases)

16. Dec 5-8, 2005 16 Energy Consumption : 2x, PCGL Energy consumptions, leakage considered, for various utilizations DVS Schemes Least consumption: ParaScale (for all cases)

17. Dec 5-8, 2005 17 Energy Consumption: 10x, PCG Energy consumptions, assuming no leakage, for various utilizations and DVS Schemes for 10x Least Consumption : ParaScale Overall savings are lower due to greater slack

18. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 18 Energy Consumption: 10x, PCGL Energy consumptions, leakage considered, for various utilizations and DVS Schemes for 10x Least Consumption : ParaScale Overall savings are lower due to greater slack

19. Dec 5-8, 2005 19 Energy Consumption trends (PCG) Energy consumption (hence savings) for ParaScale: Drops as ratio of WCET/PET is increased Due to greater slack available in the system

20. Dec 5-8, 2005 20 Energy Consumption trends (PCGL) Energy consumption affected by Leakage power prevalent in system Relative savings lower

21. Dec 5-8, 2005 21 Scheduler Overhead: Utilization 50%  Scheduler overheads greatest for ParaScale  Power savings still significant Due to lowering of voltage/frequency for schedulers

22. 22 Conclusion  Fixed-point approach To embed parametric formulae Bounds WCET of application + parametric code  Provide lower WCET bounds during execution Prior to entry into loops  Quantify savings in terms of Power savings ParaScale: combined inter and intra-task DVS  Savings of 66-80% ! Power savings over DVS-oblivious techniques.  Mainly due to knowledge about: Past execution Future execution due to parametric formulae

23. Dec 5-8, 2005 Sibin Mohan : Real-Time Systems Symposium 2005 23 Thank You ! Questions ?