1. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally MEMORYMANAGEMNT

2. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally The OS is responsible for the following activities in connection with memory management: Keep track of which parts of memory are currently being used and by whom. Decide which processes are to be loaded into memory when memory space becomes available. Allocate and deallocate memory space as needed. Memory Management

3. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Memory can be classified into two categories: Primary memory (cache, RAM) Secondary memory (magnetic disk, disk, etc.) Memory Manager :- The part of OS that perform memory management. Memory Management

4. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally The entire program or application is divided into instructions and data sets such that when one instruction set is needed it is loaded in memory and after its execution is over, the space is released. A program based on overlay scheme mainly consists of: A “root” piece which is always memory resident Set of overlays Overlays

5. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Overlays continue… Read() Function1() Function2() Display() 20K 50K 70K 40K Without Overlay (180K) Read() Display() 20K 40K With Overlay (Max.130K) Function2() Function1() Overlay A (50 K) Overlay B (70 K)

6. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Swapping is an approach for memory management by bringing each process in entirely, running it and then putting it back on the disk, so that another program may be loaded into that space. Lower priority user processes are swapped to disk when they are waiting for I/O or some other event like arrival of higher priority processes. This is Roll-out Swapping. Swapping

7. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Swapping the process back into store when some event occurs or when needed is known as Roll-in Swapping. Swapping continue… Operating System User Process/Application Process P1 Process P2 Roll-out Roll-in

8. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Benefits: Allows higher degree multiprogramming Allows dynamic relocation Better memory utilization Less wastage of CPU time on compaction Can easily be applied on priority-based scheduling algorithms to improve performance Swapping continue…

9. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Logical Address – An address generated by the CPU Physical Address– Actual address where the process is loaded Logical address is also referred to as virtual address. Logical address space – set of all logical addresses generated by a program Physical address space – set of all physical addresses corresponding to these logical addresses Logical & Physical Address Space

10. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Hardware device used for the run time mapping from logical to physical address Memory Management Unit CPU + 14000 memory relocation register register logicaladdress physicaladdress 346 14346

11. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally The main memory must accommodate both the OS and the various user processes. The main memory is usually divided into two partitions: one for the resident OS, and one for the user processes. Usually OS will be in the low memory. Contiguous Memory Allocation

12. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally The OS will be in the lower part of the memory and other user processes in the upper part. Protecting the OS from user processes and protecting user processes from one another with use of Relocation Register and Limit Register. The relocation-register scheme provides an effective way to allow the OS size to change dynamically. Single-Partition System

13. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Memory Protection CPU + relocation register registermemory logicaladdress physicaladdress < yes limit no

14. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Dividing the memory into several partitions. In multiple- partition method, when a partition is free, a process is selected from the input queue and is loaded into the free partition. When the process terminates, the partition becomes available for another process. Available memory is called hole. Multiple-Partition System

15. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally This is known as static partitioning. Divide memory into n (possibly unequal) fixed sized partitions, each of which can hold exactly one process. The degree of multiprogramming is dependent on the number of partitions. Wastage of memory within partitions is known as Internal Fragmentation. Multiple-Partition System: Fixed-sized partition

16. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally The strategies used to select a hole from the set of available holes: First fit: Best fit: Worst fit: Multiple-Partition System: Fixed-sized partition continue…

17. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally The strategies used to select a hole from the set of available holes: First fit: Allocate the first hole that is big enough. Best fit: Worst fit: Multiple-Partition System: Fixed-sized partition continue…

18. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally The strategies used to select a hole from the set of available holes: First fit: Allocate the first hole that is big enough. Best fit: Allocate the smallest hole that is big enough. Worst fit: Multiple-Partition System: Fixed-sized partition continue…

19. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally The strategies used to select a hole from the set of available holes: First fit: Allocate the first hole that is big enough. Best fit: Allocate the smallest hole that is big enough. Worst fit: Allocate the largest hole. Multiple-Partition System: Fixed-sized partition continue…

20. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally This is also known as dynamic partitioning. Partition boundaries are not fixed. Process accommodate memory according to their requirement. There is no wastage as partition size is exactly same as the size of the user process. Wastage of memory which is external to partition is known as external fragmentation. Multiple-Partition System: Variable-sized partition

21. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Internal Fragmentation: Wastage within partition. External Fragmentation: Wastage external to partition. Compaction: Solution to the problem of external fragmentation. Fragmentation

22. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Paging is a memory-management scheme that permits the physical- address space of a process to be noncontiguous. In paging, the physical memory is divided into fixed-sized blocks called page frames and logical memory is also divided into fixed- size blocks called pages which are of same size as that of page frames. When a process is to be executed, its pages can be loaded into any unallocated frames (not necessarily contiguous) from the disk. PAGING

23. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally When the CPU generates a logical address, it is divided into two parts: A page number (p) [high-order bits] and A page offset (d) [low-order bits] Where d specifies the address of the instruction within the page p. Since the logical address is a power of 2, the page size is always chosen as a power of 2 so that the logical address can be converted easily into page number and page offset. PAGING

24. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Consider the size of logical address space is 2 m. Now, if we choose a page size of 2 n., then n bits will specify the page offset and m-n bits will specify the page number. Consider a system that generates logical address of 16 bits and page size is 4 KB. How many bits would specify the page number and page offset? PAGING

25. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Logical address = 16 bits Therefore, the size of logical address space = 2 16 bytes Page size = 4 KB = 4 x 1024 bytes = 2 12 bytes Thus, Page offset = 12 bits Page Number = 16 – 12 = 4 bits PAGING

26. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally How a logical address is translated into a physical address: In paging, address translation is performed using a mapping table, called Page Table. The operating system maintains a page table for each process to keep track of which page frame is allocated to which page. It stores the frame number allocated to each page and the page number is used as index to the page table. PAGING

27. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally How a logical address is translated into a physical address: PAGING

28. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally PAGING

29. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Consider a paged memory system with eight pages of 8 KB page size each and 16 page frames in memory. Using the following page table, compute the physical address for the logical address 18325. PAGING 1010 0100 0000 0111 1101 1011 1110 0101 7 6 5 4 3 2 1 0

30. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Since, total number of pages=8, that is, 2 3 and each page size=8KB, that is, 2 13 bytes, the logical address will be of 16 bits. Out of these 16 bits, the three high-end order bits represent the page number and the 13 low-end order bits represent offset within the page. In addition, there are 16, 2 4 page frames in memory, thus the physical address will be of 17 bits. PAGING

31. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Given logical address = 18325 which is = 0100011110010101. Page number = 010 = 2; Page offset = 0011110010101. From page table page number 2 is in page frame 1011. Therefore, physical address = 10110011110010101 = 92053. PAGING

32. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally A page table can be implemented in several ways. The simplest way is to use registers to store the page table entries indexed by page number. Though this method is faster and does not require any memory reference, its disadvantage is that it is not feasible in case of large page table as registers are expensive. Moreover, in context switching all the registers to be changed and reloaded. Hardware Implementation of Page Table

33. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Alternatively, keep the entire page table in main memory and the pointer to page table stored in a register called Page Table Base Register (PTBR). Using this method, page table can be changed by reloading only one register, thus reduces context switch time. The disadvantage of this scheme is that it requires two memory references to access a memory location. To access page table using PTBR to find the page frame number. To access the desired memory location. Hardware Implementation of Page Table

34. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally This can be solved with the use of a special hardware device called Translation Look-aside Buffer (TLB). The TLB is inside MMU and contains a limited number of page table entries. When CPU generates a logical address and presents it to the MMU, it is compared with the page numbers present in the TLB. If a match is found in TLB (called TLB hit), the corresponding page frame number is used to access the physical memory. Hardware Implementation of Page Table

35. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally In case a match is not found in TLB (called TLB miss), memory is referenced for the page table. Further, this page number and the corresponding frame number are added to the TLB so that next time if this page is required, it can be referenced quickly. Since the size of TLB is limited so when it is full, one entry needs to be replaced. Hardware Implementation of Page Table

36. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Hardware Implementation of Page Table

37. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Hardware Implementation of Page Table TLB can contain entries for more than one process at the same time, so there is a possibility that two processes map the same page number to different frames. To resolve this ambiguity, a process identifier (PID) can be added with each entry of TLB. For each memory access, the PID present in the TLB is matched with the value in a special register that holds the PID of the currently executing process. If it matches, the page number is searched to find the page frame number, otherwise it is treated as a TLB miss.

38. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation A user views a program as a collection of segments such as main program, routines, variables and so on. All of these segments are variable in size. Each segment is identified by a name called Segment Number and the elements within a segment are identified by their Offset from the starting of the segment. User view of Program

39. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation Segmentation is a memory management scheme that implements the user view of a program. In this scheme, the entire logical address space is considered as collection of segments with each segment having a number and a length. The user specifies each logical address consisting of a segment number (s) and an offset (d). This differentiate segmentation from paging.

40. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation To keep track of each segment, a segment table is maintained by the operating system. Each entry in the segment table consists of two fields: Segment Base and Segment Limit.

41. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation To keep track of each segment, a segment table is maintained by the operating system. Each entry in the segment table consists of two fields: Segment Base and Segment Limit. The segment base specifies the starting address of the segment in the physical memory.

42. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation To keep track of each segment, a segment table is maintained by the operating system. Each entry in the segment table consists of two fields: Segment Base and Segment Limit. The segment Limit specifies the length of the segment.

43. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation To keep track of each segment, a segment table is maintained by the operating system. Each entry in the segment table consists of two fields: Segment Base and Segment Limit. The segment number is used as an index to the segment table.

44. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation Segment 0 main program stackstack variablesvariables routineroutine constantsconstants Segment 1 Segment 2 Segment 3 Segment 4 Logical Address Space 6400500 47001100 16001000 5800600 34001300 0 1 2 3 4 Segment Table baselimit Segment 0 Segment 3 Segment 1 Segment 4 Segment 2 Physical Memory 6900 6400 5800 4700 3400 2600 1600

45. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation When CPU generates a logical address, that address is sent to MMU. The MMU uses the segment number of logical address as an index to the segment table. The offset is compared with the segment limit and if it is greater, invalid-address error is generated. Otherwise, the offset is added to the segment base to form the physical address.

46. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation

47. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation Using the following segment table, compute the physical address for the logical address consisting of segment and offset as follows: a) Segment 2 and offset 247 b) Segment 4 and offset 439 5432350 115100 2200780 42351100 1650400 0 1 2 3 4 Segment Table baselimit

48. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation a) Segment = 2, Offset = 247 From the segment table, limit of segment 2 = 780 and segment base = 2200 Since the offset is less than the limit, Physical address = Offset + Segment base = 247 + 2200 = 2447

49. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation b) Segment = 4, Offset = 439 From the segment table, limit of segment 4 = 400 and segment base = 1650 Since the offset is greater than the limit, invalid-address error is generated.

50. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation with Paging The idea behind the segmentation with paging is to combine the advantage of both paging and segmentation together into a single scheme. In this scheme, each segment is divided into a number of pages. To keep track of these pages, a page table is maintained for each segment.

51. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation with Paging The segment offset in the logical address is further divided into a page number and a page offset. Each entry of the segment table contains the segment limit and page table base.

52. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation with Paging

53. SOCSAMS e-learning Dept. of Computer Applications, MES College Marampally Segmentation with Paging MMU uses the segment number as an index to segment table to find the address of page table. Then the page number of the logical address is attached to the high-order end of the page table address and used as an index to page table to find the page table entry. Finally, the physical address is formed by attaching the frame number obtained from the page table entry to the high-order end of the page offset.