1. Chapter 2 Instructions: Language of the Computer

2. Chapter 2 — Instructions: Language of the Computer — 2 Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers had very simple instruction sets Simplified implementation Many modern computers also have simple instruction sets §2.1 Introduction

3. Chapter 2 — Instructions: Language of the Computer — 3 The MIPS Instruction Set Used as the example throughout the book Stanford MIPS commercialized by MIPS Technologies (www.mips.com)www.mips.com Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, … Typical of many modern ISAs See MIPS Reference Data tear-out card, and Appendixes B and E

4. Chapter 2 — Instructions: Language of the Computer — 4 The ARM Instruction Set Used as the example in chapters 2 and 3 Most popular 32-bit instruction set in the world (www.arm.com) 4 Billion shipped in 2008 Large share of embedded core market Applications include mobile phones, consumer electronics, network/storage equipment, cameras, printers, … Typical of many modern RISC ISAs See ARM Assembler instructions, their encoding and instruction cycle timings in appendixes B1,B2 and B3 (CD-ROM)

5. 5 Why study instruction sets? Interface of hardware and software Efficient mapping: –Software in high level language  software in assembly language (instruction set) (Chapter 2) Impact SW cost/performance –Instruction set  hardware implementation (Chapter 3 & 4) Impact HW cost/performance SW in high level language SW in assembly language (instruction set) HW implementation

6. 6 Electronic System Design Laboratory GOAL: –Training of students who are able to master the hardware/software co-design, co-simulation, co-verification. C, C++, SystemC, etc. Assembly programming Verilog/VHDL

7. 7 What is “Computer Architecture”? I/O systemInstr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware Coordination of many levels of abstraction Under a rapidly changing set of forces Design, Measurement, and Evaluation Datapath & Control Layout

8. 8  2004 Morgan Kaufmann Publishers Instructions: Language of the Machine We’ll be working with the MIPS instruction set architecture –similar to other architectures developed since the 1980's –Almost 100 million MIPS processors manufactured in 2002 –used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, …

9. Chapter 2 — Instructions: Language of the Computer — 9 Arithmetic Operations Add and subtract, three operands Two sources and one destination add a, b, c # a gets b + c All arithmetic operations have this form Design Principle 1: Simplicity favours regularity Regularity makes implementation simpler Simplicity enables higher performance at lower cost §2.2 Operations of the Computer Hardware

10. Chapter 2 — Instructions: Language of the Computer — 10 Arithmetic Example (MIPS) C code: f = (g + h) - (i + j); Compiled MIPS code: add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 - t1

11. Chapter 2 — Instructions: Language of the Computer — 11 Arithmetic Example (ARM) C code: f = (g + h) - (i + j); Compiled ARM code: ADD t0, g, h ; temp t0 = g + h ADD t1, i, j ; temp t1 = i + j SUB f, t0, t1 ; f = t0 - t1

12. Chapter 2 — Instructions: Language of the Computer — 12 Register Operands (MIPS) Arithmetic instructions use register operands MIPS has a 32 × 32-bit register file Use for frequently accessed data Numbered 0 to 31 32-bit data called a “word” Assembler names $t0, $t1, …, $t9 for temporary values $s0, $s1, …, $s7 for saved variables Design Principle 2: Smaller is faster c.f. main memory: millions of locations §2.3 Operands of the Computer Hardware

13. Chapter 2 — Instructions: Language of the Computer — 13 Register Operands (ARM) Arithmetic instructions use register operands ARM has a 16 × 32-bit register file Use for frequently accessed data Registers numbered 0 to 15 (r0 to r15) 32-bit data called a “word” Design Principle 2: Smaller is faster c.f. main memory: millions of locations §2.3 Operands of the Computer Hardware

14. 14 Registers vs. Memory ProcessorI/O Control Datapath Memory Input Output Arithmetic instructions operands must be registers, — only 32 (MIPS) or 16 (ARM) registers provided Compiler associates variables with registers What about programs with lots of variables? RegistersMemory CapacitySmallLarge Access Speed FastSlow Registers

15. Chapter 2 — Instructions: Language of the Computer — 15 Register Operand Example (MIPS) C code: f = (g + h) - (i + j); f, …, j in $s0, …, $s4 Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1

16. Chapter 2 — Instructions: Language of the Computer — 16 Register Operand Example (ARM) C code: f = (g + h) - (i + j); f, …, j in registers r0, …,r4 r5 and r6 are temporary registers Compiled ARM code: ADD r5,r0,r1 ;register r5 contains g + h ADD r6,r2,r3 ;register r6 contains i + j SUB r4,r5,r6 ;r4 gets r5-r6

17. 17 Memory Organization Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory. 0 1 2 3 4 5 6... 8 bits of data

18. 18 Memory Organization Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes. 2 32 bytes with byte addresses from 0 to 2 32 -1 2 30 words with byte addresses 0, 4, 8,... 2 32 -4 Words are aligned i.e., what are the least 2 significant bits of a word address? 0 4 8 12... 32 bits of data Registers hold 32 bits of data

19. Chapter 2 — Instructions: Language of the Computer — 19 Memory Operands Main memory used for composite data Arrays, structures, dynamic data To apply arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies an 8-bit byte Words are aligned in memory Address must be a multiple of 4 MIPS is Big Endian Most-significant byte at least address of a word c.f. Little Endian: least-significant byte at least address

20. Placing a 32-bit word into memory in bytes Big Endian Chapter 2 — Instructions: Language of the Computer — 20 0 1 2 3 4 5 6... Most significant : : Least significant Little Endian 0 1 2 3 4 5 6... Least significant : : Most significant

21. Chapter 2 — Instructions: Language of the Computer — 21 Memory Operand Example 1 (MIPS) C code: g = h + A[8]; g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 4 bytes per word lw $t0, 32($s3) # $t0 <-m[$s3+32] add $s1, $s2, $t0 offset base register

22. Chapter 2 — Instructions: Language of the Computer — 22 Memory Operand Example 1 (ARM) C code: g = h + A[8]; g in r1, h in r2, base address of A in r3 r5 is temporary register Compiled ARM code: Index 8 requires offset of 32 4 bytes per word LDR r5,[r3,#32] ; reg r5 gets A[8] ADD r1, r2, r5 ; g = h + A[8] offset base register

23. Chapter 2 — Instructions: Language of the Computer — 23 Memory Operand Example 2 (MIPS) C code: A[12] = h + A[8]; h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 lw $t0, 32($s3) # load word add $t0, $s2, $t0 sw $t0, 48($s3) # store word

24. Chapter 2 — Instructions: Language of the Computer — 24 Memory Operand Example 2 (ARM) C code: A[12] = h + A[8]; h in r2, base address of A in r3 r5 is temporary register Compiled ARM code: Index 8 requires offset of 32 LDR r5,[r3,#32] ; reg r5 gets A[8] ADD r5, r2, r5 ; reg r5 gets h+A[8] STR r5,[r3,#48] ; Stores h+A[8]into A[12]

25. 25 Instructions (MIPS) Load and store instructions Example: C code: A[12] = h + A[8]; MIPS code: lw $t0, 32($s3); $s3=A, 32=8*4 add $t0, $s2, $t0 sw $t0, 48($s3) Store word has destination last Remember: – Operands of arithmetic/logic instructions are registers, not memory! –Load/store instructions have one memory operand. Note: –Temporary register: $t0; –Array name: a register $s3; –Displacement: 32, not 8! 48, not 12!

26. 26 Our First Example (MIPS) Can we figure out the code? swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2; $s2= addr.of v[k] lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31; Return addr. is saved in $s31

27. 27 Our First Example (ARM) Can we figure out the code? swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: ; ARM assembly ADD r5, r0, r1, LSL #2 ; r5=addr. of v[k] ; r5 = r0 + r1<<2 ; r0 = v; r1 = k LDR r4, [r5, #0] ; r4 = v[k] LDR r6, [r5, #4] ; r6 = v[k+1] STR r6, [r5, #0] ; v[k] = r6 STR r4, [r5, #4] ; v[k=1] = r5 MOV pc, lr ; return to caller swap: ; MIPS assembly muli $2, $5, 4 add $2, $4, $2 ; $s2= addr.of v[k] lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 ; Return addr. is saved in $s31

28. Chapter 2 — Instructions: Language of the Computer — 28 Registers vs. Memory Registers are faster to access than memory Operating on memory data requires loads and stores More instructions to be executed Compiler must use registers for variables as much as possible Only spill to memory for less frequently used variables Register optimization is important!

29. Chapter 2 — Instructions: Language of the Computer — 29 Immediate Operands (MIPS) Constant data specified in an instruction addi $s3, $s3, 4 No subtract immediate instruction Just use a negative constant addi $s2, $s1, -1 Design Principle 3: Make the common case fast Small constants are common Immediate operand avoids a load instruction

30. Chapter 2 — Instructions: Language of the Computer — 30 Immediate Operands (ARM) Constant data specified in an instruction ADD r3,r3,#4 ; r3 = r3 + 4 Design Principle 3: Make the common case fast Small constants are common Immediate operand avoids a load instruction

31. Chapter 2 — Instructions: Language of the Computer — 31 The Constant Zero MIPS register 0 ($zero) is the constant 0 Cannot be overwritten Useful for common operations E.g., move between registers add $t2, $s1, $zero

32. Chapter 2 — Instructions: Language of the Computer — 32 Unsigned Binary Integers Given an n-bit number Range: 0 to +2 n – 1 Example 0000 0000 0000 0000 0000 0000 0000 1011 2 = 0 + … + 1×2 3 + 0×2 2 +1×2 1 +1×2 0 = 0 + … + 8 + 0 + 2 + 1 = 11 10 Using 32 bits 0 to +4,294,967,295 §2.4 Signed and Unsigned Numbers

33. Chapter 2 — Instructions: Language of the Computer — 33 2s-Complement Signed Integers Given an n-bit number Range: –2 n – 1 to +2 n – 1 – 1 Example 1111 1111 1111 1111 1111 1111 1111 1100 2 = –1×2 31 + 1×2 30 + … + 1×2 2 +0×2 1 +0×2 0 = –2,147,483,648 + 2,147,483,644 = –4 10 Using 32 bits –2,147,483,648 to +2,147,483,647

34. Chapter 2 — Instructions: Language of the Computer — 34 2s-Complement Signed Integers Bit 31 is sign bit 1 for negative numbers 0 for non-negative numbers –(–2 n – 1 ) can’t be represented Non-negative numbers have the same unsigned and 2s-complement representation Some specific numbers 0:0000 0000 … 0000 –1:1111 1111 … 1111 Most-negative:1000 0000 … 0000 Most-positive:0111 1111 … 1111

35. Chapter 2 — Instructions: Language of the Computer — 35 Signed Negation Complement and add 1 Complement means 1 → 0, 0 → 1 Example: negate +2 +2 = 0000 0000 … 0010 2 –2 = 1111 1111 … 1101 2 + 1 = 1111 1111 … 1110 2

36. Chapter 2 — Instructions: Language of the Computer — 36 Sign Extension (MIPS) Representing a number using more bits Preserve the numeric value In MIPS instruction set addi : extend immediate value lb, lh : extend loaded byte/halfword beq, bne : extend the displacement Replicate the sign bit to the left c.f. unsigned values: extend with 0s Examples: 8-bit to 16-bit +2: 0000 0010 => 0000 0000 0000 0010 –2: 1111 1110 => 1111 1111 1111 1110

37. Chapter 2 — Instructions: Language of the Computer — 37 Sign Extension (ARM) Representing a number using more bits Preserve the numeric value In ARM instruction set LDRSB,LDRSH: extend loaded byte/halfword Replicate the sign bit to the left c.f. unsigned values: extend with 0s Examples: 8-bit to 16-bit +2: 0000 0010 => 0000 0000 0000 0010 –2: 1111 1110 => 1111 1111 1111 1110

38. Chapter 2 — Instructions: Language of the Computer — 38 Representing Instructions (MIPS) Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … Regularity! Register numbers $t0 – $t7 are reg’s 8 – 15 $t8 – $t9 are reg’s 24 – 25 $s0 – $s7 are reg’s 16 – 23 §2.5 Representing Instructions in the Computer

39. Chapter 2 — Instructions: Language of the Computer — 39 Representing Instructions (ARM) Instructions are encoded in binary Called machine code ARM instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … Regularity! Register numbers – r0 to r15 §2.5 Representing Instructions in the Computer

40. Chapter 2 — Instructions: Language of the Computer — 40 R-format Instructions (MIPS) Instruction fields op: operation code (opcode) rs: first source register number rt: second source register number rd: destination register number shamt: shift amount (00000 for now) funct: function code (extends opcode) oprsrtrdshamtfunct 6 bits 5 bits

41. Chapter 2 — Instructions: Language of the Computer — 41 R-format Example (MIPS) add $t0, $s1, $s2 special$s1$s2$t00add 017188032 00000010001100100100000000100000 00000010001100100100000000100000 2 = 02324020 16 oprsrtrdshamtfunct 6 bits 5 bits

42. Chapter 2 — Instructions: Language of the Computer — 42 Data Processing (DP) Instructions (ARM) Instruction fields Opcode : Basic operation of the instruction Rd: The destination register operand Rn: The first register source operand Operand2: The second source operand I:Immediate. If I is 0, the second source operand is a register, else the second source is a 12-bit immediate. S: Set Condition Code Cond: Condition F: Instruction Format. CondFIOpcodeSRn 4 bits 2 bits1 bits4 bits1 bits RdOperand2 4 bits12 bits

43. Chapter 2 — Instructions: Language of the Computer — 43 DP Instruction Example (ARM) ADD r5,r1,r2 ; r5 = r1 + r2 11100000100000010101000000000010 2 1400401 4 bits 2 bits1 bits4 bits1 bits 52 4 bits12 bits CondFIOpcodeSRn 4 bits 2 bits1 bits4 bits1 bits RdOperand2 4 bits12 bits

44. 44 Instructions, like registers and words of data, are also 32 bits long –Example: add $t0, $s1, $s2 –registers have numbers, $t0=8, $s1=17, $s2=18 Instruction Format: 00000010001100100100000000100000 op rs rt rdshamtfunct Can you guess what the field names stand for? Machine Language: add/sub (arithmetic) (MIPS)

45. 45 Now include the load/store instructions into the same instruction format (regularity principle): –Example: lw $s1, 32($s2) –registers have numbers, $s1=2, $s2=18 Using the same Instruction Format as arithmetic operations: 10001110010xxxxx0001000000100000 op rs rt rdshamtHshamtL Can you see any problem? Machine Language: load/store (MIPS)

46. 46 Consider the load-word and store-word instructions, –What would the regularity principle have us do? –New principle: Good design demands a compromise Introduce a new type of instruction format –I-type for data transfer instructions –other format was R-type for register Example: lw $t0, 32($s2) 35 18 2 32 op rs rt 16 bit number Where's the compromise? Machine Language: load/store instructions (MIPS)

47. 47 Machine Language PROBLEM: How to access an array element with displacement > 2^16? Displacement > 2^16? X=A[100000]+……. Assume t1 is a temporary 32-bit register. m[1024] the memory location which has a large value. Its address is calculated by 0($s). t3 is a register contain the base address of array A. t4 is a temporary 32 bits register. 100000 A[ ] →t1 t3→ ← m[1024] ﹜ Displacement >2^16 ←→t5 A[100000] lw $t1, 0($s2); //load immediate to $t1. add $t4, $t3, $t1; //calculate the displacement. lw $t5, 0($t4); //load the displacement to t5.

48. 48 Machine Language (corrected) PROBLEM: How to access an array element with displacement > 2^16? Displacement > 2^16? X=A[100000]+……. Assume t1 is a temporary 32-bit register. m[1024] the memory location which has a large value. Its address is calculated by 0($s). t3 is a register contain the base address of array A. t4 is a temporary 32 bits register. 400000 A[ ] →t1 t3→ ← m[1024] ﹜ Displacement >2^16 ←→t5 A[100000] lw $t1, 0($s2); //load immediate to $t1. add $t4, $t3, $t1; //calculate the displacement. lw $t5, 0($t4); //load the displacement to t5.

49. Chapter 2 — Instructions: Language of the Computer — 49 Hexadecimal Base 16 Compact representation of bit strings 4 bits per hex digit 000004010081000c1100 100015010191001d1101 2001060110a1010e1110 3001170111b1011f1111 Example: eca8 6420 1110 1100 1010 1000 0110 0100 0010 0000

50. Chapter 2 — Instructions: Language of the Computer — 50 I-format Instructions (MIPS) Immediate arithmetic and load/store instructions rt: destination or source register number Constant: –2 15 to +2 15 – 1 Address: offset added to base address in rs Design Principle 4: Good design demands good compromises Different formats complicate decoding, but allow 32-bit instructions uniformly Keep formats as similar as possible oprsrtconstant or address 6 bits5 bits 16 bits

51. Chapter 2 — Instructions: Language of the Computer — 51 Data Transfer (DT) Instruction (ARM) Design Principle 4: Good design demands good compromises Different formats complicate decoding, but allow 32-bit instructions uniformly Keep formats as similar as possible CondFOpcodeRn 4 bits 2 bits6 bits RdOffset12 4 bits12 bits 141243 4 bits 2 bits6 bits 532 4 bits12 bits LDR r5, [r3, #32] ; Temporary reg r5 gets A[8]

52. Chapter 2 — Instructions: Language of the Computer — 52 Stored Program Computers Instructions represented in binary, just like data Instructions and data stored in memory Programs can operate on programs e.g., compilers, linkers, … Binary compatibility allows compiled programs to work on different computers Standardized ISAs The BIG Picture

53. Chapter 2 — Instructions: Language of the Computer — 53 Logical Operations (MIPS) Instructions for bitwise manipulation OperationCJavaMIPS Shift left<< sll Shift right>>>>> srl Bitwise AND&& and, andi Bitwise OR|| or, ori Bitwise NOT~~ nor Useful for extracting and inserting groups of bits in a word §2.6 Logical Operations

54. Chapter 2 — Instructions: Language of the Computer — 54 Logical Operations (ARM) Instructions for bitwise manipulation OperationCJavaARM Shift left<< LSL Shift right>>>>> LSR Bitwise AND&& AND Bitwise OR|| ORR Bitwise NOT~~ MVN Useful for extracting and inserting groups of bits in a word §2.6 Logical Operations

55. Chapter 2 — Instructions: Language of the Computer — 55 Shift Operations (MIPS) shamt: how many positions to shift Shift left logical Shift left and fill with 0 bits sll by i bits multiplies by 2 i Shift right logical Shift right and fill with 0 bits srl by i bits divides by 2 i (unsigned only) oprsrtrdshamtfunct 6 bits 5 bits

56. Chapter 2 — Instructions: Language of the Computer — 56 Shift Operations (ARM) shift_imm: how many positions to shift Logical shift left (LSL) Shift left and fill with 0 bits LSL by i bits multiplies by 2 i rm, LSL # ADD r5,r1,r2 LSL #2 ; r5 = r1 + (r2 << 2) Logical shift right(LSR) Shift right and fill with 0 bits LSR by i bits divides by 2 i (unsigned only) rm, LSR # MOV r6,r5, LSR # 4 ; r6 = r5 >> 4 Cond000OpcodeSRn 4 bits 3 bits4 bits1 bit Rdshift_imm 4 bits8 bits 000Rm 4 bits3 bits

57. Chapter 2 — Instructions: Language of the Computer — 57 Shift Operations (ARM) shift_imm: how many positions to shift Arithmetic shift right(LSR) Shift right and fill with sign bits rm, ASR # MOV r6,r5, ASR # 4 ; r6 = r5 >> 4 Cond000OpcodeSRn 4 bits 3 bits4 bits1 bit Rdshift_imm 4 bits8 bits 000Rm 4 bits3 bits

58. Chapter 2 — Instructions: Language of the Computer — 58 AND Operations (MIPS) Useful to mask bits in a word Select some bits, clear others to 0 and $t0, $t1, $t2 0000 0000 0000 0000 0000 1101 1100 0000 0000 0000 0000 0000 0011 1100 0000 0000 $t2 $t1 0000 0000 0000 0000 0000 1100 0000 0000 $t0

59. Chapter 2 — Instructions: Language of the Computer — 59 AND Operations (ARM) Useful to mask bits in a word Select some bits, clear others to 0 AND r5, r1, r2 ; reg r5 = reg r1 & reg r2 0000 0000 0000 0000 0000 1101 1100 0000 0000 0000 0000 0000 0011 1100 0000 0000 r2 r1 0000 0000 0000 0000 0000 1100 0000 0000 r5

60. Chapter 2 — Instructions: Language of the Computer — 60 OR Operations (MIPS) Useful to include bits in a word Set some bits to 1, leave others unchanged or $t0, $t1, $t2 0000 0000 0000 0000 0000 1101 1100 0000 0000 0000 0000 0000 0011 1100 0000 0000 $t2 $t1 0000 0000 0000 0000 0011 1101 1100 0000 $t0

61. Chapter 2 — Instructions: Language of the Computer — 61 OR Operations (ARM) Useful to include bits in a word Set some bits to 1, leave others unchanged ORR r5, r1, r2 ; reg r5 = reg r1 | reg r2 0000 0000 0000 0000 0000 1101 1100 0000 0000 0000 0000 0000 0011 1100 0000 0000 r2 r1 0000 0000 0000 0000 0011 1101 1100 0000 r5

62. Chapter 2 — Instructions: Language of the Computer — 62 NOT Operations (MIPS) Useful to invert bits in a word Change 0 to 1, and 1 to 0 MIPS has NOR 3-operand instruction a NOR b == NOT ( a OR b ) nor $t0, $t1, $zero 0000 0000 0000 0000 0011 1100 0000 0000 $t1 1111 1111 1111 1111 1100 0011 1111 1111 $t0 Register 0: always read as zero

63. Chapter 2 — Instructions: Language of the Computer — 63 NOT Operations (ARM) Useful to invert bits in a word Change 0 to 1, and 1 to 0 ARM has Move Not (MVN) MVN r5, r1 ; reg r5 = ~ reg r1 0000 0000 0000 0000 0011 1100 0000 0000 r1 1111 1111 1111 1111 1100 0011 1111 1111 r5

64. Chapter 2 — Instructions: Language of the Computer — 64 Conditional Operations (MIPS) Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to instruction labeled L1; bne rs, rt, L1 if (rs != rt) branch to instruction labeled L1; j L1 unconditional jump to instruction labeled L1 §2.7 Instructions for Making Decisions

65. Chapter 2 — Instructions: Language of the Computer — 65 Conditional Operations (ARM) Branch to a labeled instruction if a condition is true Otherwise, continue sequentially CMP reg1,reg2 BEQ L1 if (reg1 == reg2) branch to instruction labeled L1; CMP reg1,reg2 BNE L1 if (reg1 != reg2) branch to instruction labeled L1; B exit ; go to exit unconditional jump to instruction labeled exit §2.7 Instructions for Making Decisions

66. Chapter 2 — Instructions: Language of the Computer — 66 Compiling If Statements (MIPS) C code: if (i==j) f = g+h; else f = g-h; f, g, … in $s0, $s1, … Compiled MIPS code: bne $s3, $s4, Else add $s0, $s1, $s2 j Exit Else: sub $s0, $s1, $s2 Exit: … Assembler calculates addresses

67. Chapter 2 — Instructions: Language of the Computer — 67 Compiling If Statements (ARM) C code: if (i==j) f = g+h; else f = g-h; f, g, … in r0, r1,..r4 Compiled ARM code: CMP r3,r4 BNE Else ; go to Else if i != j ADD r1,r1,r2 ; f = g + h (skipped if i != j) B exit Else : SUB r0,r1,r2 ; f = g + h (skipped if i = j) Exit: Assembler calculates addresses

68. Chapter 2 — Instructions: Language of the Computer — 68 Compiling Loop Statements (MIPS) C code: while (save[i] == k) i += 1; i in $s3, k in $s5, address of save in $s6 Compiled MIPS code: Loop: sll $t1, $s3, 2 %word-> byte addr add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, 1 j Loop Exit: …

69. Chapter 2 — Instructions: Language of the Computer — 69 Compiling Loop Statements (ARM) C code: while (save[i] == k) i += 1; i in r3, k in r5, base address of save in r6 Compiled ARM code: Loop: ADD r12,r6, r3, LSL # 2 ; r12 = address of save[i] LDR r0,[r12,#0] ; Temp reg r0 = save[i] CMP r0,r5 BNE Exit ; go to Exit if save[i] ≠ k ADD r3,r3,#1 ; i = i + 1 B Loop ; go to Loop Exit:

70. Chapter 2 — Instructions: Language of the Computer — 70 Basic Blocks A basic block is a sequence of instructions with No embedded branches (except at end) No branch targets (except at beginning) A compiler identifies basic blocks for optimization An advanced processor can accelerate execution of basic blocks

71. Chapter 2 — Instructions: Language of the Computer — 71 More Conditional Operations Set result to 1 if a condition is true Otherwise, set to 0 slt rd, rs, rt if (rs < rt) rd = 1; else rd = 0; slti rt, rs, constant if (rs < constant) rt = 1; else rt = 0; Use in combination with beq, bne slt $t0, $s1, $s2 # if ($s1 < $s2) bne $t0, $zero, L # branch to L

72. Chapter 2 — Instructions: Language of the Computer — 72 Branch Instruction Design Why not blt, bge, etc? Hardware for <, ≥, … slower than =, ≠ Combining with branch involves more work per instruction, requiring a slower clock All instructions penalized! beq and bne are the common case This is a good design compromise

73. Chapter 2 — Instructions: Language of the Computer — 73 Signed vs. Unsigned (MIPS) Signed comparison: slt, slti Unsigned comparison: sltu, sltui Example $s0 = 1111 1111 1111 1111 1111 1111 1111 1111 $s1 = 0000 0000 0000 0000 0000 0000 0000 0001 slt $t0, $s0, $s1 # signed –1 < +1  $t0 = 1 sltu $t0, $s0, $s1 # unsigned +4,294,967,295 > +1  $t0 = 0

74. Chapter 2 — Instructions: Language of the Computer — 74 Signed vs. Unsigned (ARM) Signed comparison: BGE,BLT,BGT,BLE Unsigned comparison: BHS,BLO,BHI,BLS Example r0 = 1111 1111 1111 1111 1111 1111 1111 1111 r1 = 0000 0000 0000 0000 0000 0000 0000 0001 CMP r0,r1 BLO L1 ; unsigned branch Branch not taken since 4,294,967,295 ten > 1 ten BLT L2 ; signed branch Branch taken to L2 since -1 ten < 1 ten.

75. Chapter 2 — Instructions: Language of the Computer — 75 Procedure Calling Steps required 1.Place parameters in registers 2.Transfer control to procedure 3.Acquire storage for procedure 4.Perform procedure’s operations 5.Place result in register for caller 6.Return to place of call §2.8 Supporting Procedures in Computer Hardware

76. Chapter 2 — Instructions: Language of the Computer — 76 ARM register conventions

77. 77 Procedure Call: basic concept Caller –The program that instigates a procedure and provides the necessary parameter values. Callee –A procedure that executes a series of stored instructions based on parameters provided by the caller and then returns control to the caller. Return Address –A link to the calling site that allows a procedure to return to the proper address; in MIPS it is stored in the register $ra Stack –A data structure for spilling registers organized as a last-in-first- out queue. Stack Pointer –A value denoting the most recently allocated address in a stack that shows where registers should be spilled or where old register values can be found.

78. 78 Allocate New Data on the Stack Frame pointer ($fp) –Help $sp to save the first address of the callee procedure (a stable based register within a procedure for local memory references; $sp might be changed during the procedure.) Saved argument Saved return address Saved saved registers Local arrays and structures High Address Low Address $fp $sp $fp $sp $fp $sp Proc. A Proc. A calls Proc. B Proc. A (return from Proc. B)

79. 79 Chapter 2 — Instructions: Language of the Computer — 79 Local Data on the Stack Local data allocated by callee –e.g., C automatic variables Procedure frame (activation record) –Used by some compilers to manage stack storage

80. Memory Layout Text: program code Static data: global variables e.g., static variables in C, constant arrays and strings $gp initialized to address allowing ±offsets into this segment Dynamic data: Heap E.g., malloc in C, new in Java Stack: automatic storage Chapter 2 — Instructions: Language of the Computer — 80

81. 81 Allocate New Data on the Heap Heap vs. stack –Heap used to save static variable and dynamic data structure Arrays, linked lists, etc. Stack Dynamic data Static data Text Reserved $sp $gp 7fff fffc hex 1000 8000 hex 1000 0000 hex 0040 0000 hex pc 0

82. 82 Saving registers Both leaf and non-leaf procedures need to save: –Saved registers (so space can be reused by other variables) Non-leaf procedures need to save additionally: –Argument registers –Temporary registers –Return register

83. 83 Policy of Use Conventions Register 1 ($at) reserved for assembler, 26-27 for operating system

84. Chapter 2 — Instructions: Language of the Computer — 84 Register Usage (MIPS) $a0 – $a3: arguments (reg’s 4 – 7) $v0, $v1: result values (reg’s 2 and 3) $t0 – $t9: temporaries Can be overwritten by callee $s0 – $s7: saved Must be saved/restored by callee $gp: global pointer for static data (reg 28) $sp: stack pointer (reg 29) $fp: frame pointer (reg 30) $ra: return address (reg 31)

85. Chapter 2 — Instructions: Language of the Computer — 85 Procedure Call Instructions (MIPS) Procedure call: jump and link jal ProcedureLabel Address of following instruction put in $ra Jumps to target address Procedure return: jump register jr $ra Copies $ra to program counter Can also be used for computed jumps e.g., for case/switch statements

86. Chapter 2 — Instructions: Language of the Computer — 86 Procedure Call Instructions (ARM) Procedure call: Branch and link BL ProcedureAddress Address of following instruction put in lr Jumps to target address Procedure return: MOV pc,lr Copies lr to program counter Can also be used for computed jumps e.g., for case/switch statements

87. 87 C Pure Procedure Stack pointer ($sp) and return address ($ra) C code: int leaf_example(int g, int h, int i, int j) { int f; f = (g + h) – (i + j); return f } MIPS ‘code’: leaf_example: addi $sp, $sp, -12 ; backup the values sw $t1, 8($sp) ; of registers which sw $t0, 4($sp) ; will be used in this sw $s0, 0($sp) ; procedure add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $zero lw $s0, 0($sp) ; restore the values lw $t0, 4($sp) ; saved in stack lw $t1, 8($sp) ; previously addi $sp, $sp, 12 jr $ra ; return address

88. Chapter 2 — Instructions: Language of the Computer — 88 Leaf Procedure Example (MIPS) C code: int leaf_example (int g, h, i, j) { int f; f = (g + h) - (i + j); return f; } Arguments g, …, j in $a0, …, $a3 f in $s0 (hence, need to save $s0 on stack) Result in $v0

89. Chapter 2 — Instructions: Language of the Computer — 89 Leaf Procedure Example (MIPS) MIPS code: (if there is no need to save $t’s) leaf_example: addi $sp, $sp, -4 sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $zero lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra Save $s0 on stack Procedure body Restore $s0 Result Return

90. Chapter 2 — Instructions: Language of the Computer — 90 Leaf Procedure Example (ARM) C code: int leaf_example (int g, h, i, j) { int f; f = (g + h) - (i + j); return f; } Arguments g, …, j in r0, …, r3 f in r4 (hence, need to save r4 on stack) Result in r0

91. Chapter 2 — Instructions: Language of the Computer — 91 Leaf Procedure Example (ARM) ARM code: leaf_example: SUB sp, sp, #12 STR r6,[sp,#8] STR r5,[sp,#4] STR r4,[sp,#0] ADD r5,r0,r1 ADD r6,r2,r3 SUB r4,r5,r6 MOV r0,r4 LDR r4, [sp,#0] LDR r5, [sp,#4] LDR r6, [sp,#8] ADD sp,sp,#12 MOV pc,lr Save r4,r5,r6 on stack Restore r4,r5,r6 Result moved to return value register r0. Return Make room for 3 items r5 = (g+h), r6= (i+j) Result in r4

92. Chapter 2 — Instructions: Language of the Computer — 92 Non-Leaf Procedures Procedures that call other procedures For nested call, caller needs to save on the stack: Its return address Any arguments and temporaries needed after the call Restore from the stack after the call

93. 93 Recursive Procedure Stack pointer ($sp) and return address ($ra) C code: int fact(int n) { if(n < 1) return (1); else return (n * fact(n-1)); } MIPS ‘code’: fact: addi $sp, $sp, -8 sw $ra, 4($sp) ; backup the return address sw $a0, 0($sp) ; & argument n slti $t0, $a0, 1 beq $t0, $zero, L1 addi $v0, $zero, 1 addi $sp, $sp, 8 jr $ra L1: addi $a0, $a0, -1 jal fact lw $a0, 0($sp) ; restore the return address lw $ra, 4($sp) ; & argument n addi $sp, $sp, 8 mul $v0, $a0, $v0 ; n * fact(n-1) jr $ra ; return to the caller

94. Chapter 2 — Instructions: Language of the Computer — 94 Non-Leaf Procedure Example (MIPS) C code: int fact (int n) { if (n < 1) return 1; else return n * fact(n - 1); } Argument n in $a0 Result in $v0

95. Chapter 2 — Instructions: Language of the Computer — 95 Non-Leaf Procedure Example (MIPS) MIPS code: fact: addi $sp, $sp, -8 # adjust stack for 2 items sw $ra, 4($sp) # save return address sw $a0, 0($sp) # save argument slti $t0, $a0, 1 # test for n < 1 beq $t0, $zero, L1 addi $v0, $zero, 1 # if so, result is 1 addi $sp, $sp, 8 # pop 2 items from stack jr $ra # and return L1: addi $a0, $a0, -1 # else decrement n jal fact # recursive call lw $a0, 0($sp) # restore original n lw $ra, 4($sp) # and return address addi $sp, $sp, 8 # pop 2 items from stack mul $v0, $a0, $v0 # multiply to get result jr $ra # and return

96. Chapter 2 — Instructions: Language of the Computer — 96 Non-Leaf Procedure Example (ARM) C code: int fact (int n) { if (n < 1) return 1; else return n * fact(n - 1); } Argument n in register r0 Result in register r0

97. Chapter 2 — Instructions: Language of the Computer — 97 Non-Leaf Procedure Example (ARM) ARM code: fact: SUB sp,sp,#8 ; Adjust stack for 2 items STR lr,[sp,#4] ; Save return address STR r0,[sp,#0] ; Save argument n CMP r0,#1 ; compare n to 1 BGE L1 MOV r0,#1 ; if so, result is 1 ADD sp,sp,#8 ; Pop 2 items from stack MOV pc,lr ; Return to caller L1: SUB r0,r0,#1 ; else decrement n BL fact ; Recursive call MOV r12,r0 ; Restore original n LDR r0,[sp,#0] ; and return address LDR lr,[sp,#4] ; pop 2 items from stack ADD sp,sp #8 ; MUL r0,r0,r12 ; Multiply to get result MOV pc,lr ; and return

98. 98 MIPS instructions so far: InstructionMeaning (Register Transfer Language, RTL) add $s1,$s2,$s3$s1 = $s2 + $s3 sub $s1,$s2,$s3$s1 = $s2 – $s3 lw $s1,100($s2)$s1 = Memory[$s2+100] sw $s1,100($s2)Memory[$s2+100] = $s1 bne $s4,$s5,LNext instr. is at Label if $s4 ° $s5 beq $s4,$s5,LNext instr. is at Label if $s4 = $s5 j LabelNext instr. is at Label Formats: op rs rt rdshamtfunct op rs rt 16 bit address op 26 bit address RIJRIJ

99. 99 Chapter 2 — Instructions: Language of the Computer — 99 ARM instruction format summary

100. Chapter 2 — Instructions: Language of the Computer — 100 Character Data Byte-encoded character sets ASCII: 128 characters 95 graphic, 33 control Latin-1: 256 characters ASCII, +96 more graphic characters Unicode: 32-bit character set Used in Java, C++ wide characters, … Most of the world’s alphabets, plus symbols UTF-8, UTF-16: variable-length encodings §2.9 Communicating with People

101. Chapter 2 — Instructions: Language of the Computer — 101 Byte/Halfword Operations (MIPS) Could use bitwise operations MIPS byte/halfword load/store String processing is a common case lb rt, offset(rs) lh rt, offset(rs) Sign extend to 32 bits in rt lbu rt, offset(rs) lhu rt, offset(rs) Zero extend to 32 bits in rt sb rt, offset(rs) sh rt, offset(rs) Store just rightmost byte/halfword

102. Chapter 2 — Instructions: Language of the Computer — 102 Byte/Halfword Operations (ARM) Could use bitwise operations ARM byte load/store String processing is a common case LDRB r0, [sp,#0] ; Read byte from source STRB r0, [r10,#0] ; Write byte to destination Sign extend to 32 bits LDRSB ; Sign extends to fill leftmost 24 bits ARM halfword load/store LDRH r0, [sp,#0] ; Read halfword (16 bits) from source STRH r0,[r12,#0] ; Write halfword (16 bits) to destination Sign extend to 32 bits LDRSH ; Sign extends to fill leftmost 16 bits

103. Chapter 2 — Instructions: Language of the Computer — 103 String Copy Example (MIPS) C code (naïve): Null-terminated string void strcpy (char x[], char y[]) { int i; i = 0; while ((x[i]=y[i])!='\0') i += 1; } Addresses of x, y in $a0, $a1 i in $s0

104. Chapter 2 — Instructions: Language of the Computer — 104 String Copy Example (MIPS) MIPS code: strcpy: addi $sp, $sp, -4 # adjust stack for 1 item sw $s0, 0($sp) # save $s0 add $s0, $zero, $zero # i = 0 L1: add $t1, $s0, $a1 # addr of y[i] in $t1; no *4 lbu $t2, 0($t1) # $t2 = y[i] add $t3, $s0, $a0 # addr of x[i] in $t3 sb $t2, 0($t3) # x[i] = y[i] beq $t2, $zero, L2 # exit loop if y[i] == 0 addi $s0, $s0, 1 # i = i + 1 j L1 # next iteration of loop L2: lw $s0, 0($sp) # restore saved $s0 addi $sp, $sp, 4 # pop 1 item from stack jr $ra # and return

105. Chapter 2 — Instructions: Language of the Computer — 105 String Copy Example (ARM) C code (naïve): Null-terminated string void strcpy (char x[], char y[]) { int i; i = 0; while ((x[i]=y[i])!='\0') i += 1; } Addresses of x, y in registers r0, r1 i in register r4

106. Chapter 2 — Instructions: Language of the Computer — 106 String Copy Example (ARM) ARM code: strcpy: SUB sp,sp, #4 ; adjust stack for 1 item STR r4,[sp,#0] ; save r4 MOV r4,#0 ; i = 0 + 0 L1: ADD r2,r4,r1 ; addr of y[i] in r2 LDRBr3, [r2, #0] ; r3 = y[i] ADD r12,r4,r0 ; ; Addr of x[i] in r12 STRB r3 [r12, #0] ; x[i] = y[i] BEQ L2 ; exit loop if y[i]==0 (Z=1) ADD r4,r4,#1 ; i = i + 1 B L1 ; next iteration of loop L2: LDR r4, [sp,#0] ; restore saved r4 ADD sp,sp, #4 ; pop 1 item from stack MOV pc,lr ; return

107. Chapter 2 — Instructions: Language of the Computer — 107 0000 0000 0111 1101 0000 0000 0000 0000 32-bit Constants (MIPS) Most constants are small 16-bit immediate is sufficient For the occasional 32-bit constant lui rt, constant Copies 16-bit constant to left 16 bits of rt Clears right 16 bits of rt to 0 lui $s0, 61 0000 0000 0111 1101 0000 1001 0000 0000 ori $s0, $s0, 2304 §2.10 MIPS Addressing for 32-Bit Immediates and Addresses

108. Chapter 2 — Instructions: Language of the Computer — 108 32-bit Constants (ARM) Most constants are small 16-bit immediate is sufficient For the occasional 32-bit constant Load 32 bit constant to r4 §2.10 ARM Addressing for 32-Bit Immediates and Addresses 0000 0000 1101 1001 0000 0000 0000 0000 The 8 non-zerobits (1101 1101 2, 217 ten ) of the constant is rotated by 16 bits and MOV instruction (opcode -13) loads the 32 bit value

109. Chapter 2 — Instructions: Language of the Computer — 109 Branch Addressing (MIPS) Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward oprsrtconstant or address 6 bits5 bits 16 bits PC-relative addressing Target address = PC + offset × 4 PC already incremented by 4 by this time

110. Chapter 2 — Instructions: Language of the Computer — 110 Jump Addressing (MIPS) Jump ( j and jal ) targets could be anywhere in text segment Encode full address in instruction opaddress 6 bits 26 bits (Pseudo)Direct jump addressing Target address = PC 31…28 : (address × 4)

111. Chapter 2 — Instructions: Language of the Computer — 111 Target Addressing Example (MIPS) Loop code from earlier example Assume Loop at location 80000 Loop: sll $t1, $s3, 2 800000019940 add $t1, $t1, $s6 8000409229032 lw $t0, 0($t1) 8000835980 bne $t0, $s5, Exit 8001258212 addi $s3, $s3, 1 80016819 1 j Loop 80020220000 Exit: … 80024

112. Chapter 2 — Instructions: Language of the Computer — 112 Branching Far Away (MIPS) If branch target is too far to encode with 16-bit offset, assembler rewrites the code Example beq $s0,$s1, L1 ↓ bne $s0,$s1, L2 j L1 L2:…

113. Chapter 2 — Instructions: Language of the Computer — 113 Addressing Mode Summary (MIPS)

114. Chapter 2 — Instructions: Language of the Computer — 114 Branch Instruction format (ARM) Condition12 4 bits address 24 bits  Encoding of options for Condition field

115. Chapter 2 — Instructions: Language of the Computer — 115 Conditional Execution (ARM) ARM code for executing if statement Code on right does not use branch. This can help performance of pipelined computers (Chapter 4) CMP r3, r4 ; reg r3 and r4 contain i,j BNE Else ; go to Else if i <> j ADD r0,r1,r2 ; f = g + h B Exit ; go to Exit Else: SUB r0,r1,r2 ; f = g – h Exit: CMP r3,r4 ADDEQ r0,r1,r2 ; f = g+h SUBNE r0,r1,r2 ; f = g- h

116. Chapter 2 — Instructions: Language of the Computer — 116 Addressing Mode Summary (1-3 of 12) (ARM)

117. Chapter 2 — Instructions: Language of the Computer — 117 Addressing Mode Summary (4-6 of 12) (ARM)

118. Chapter 2 — Instructions: Language of the Computer — 118 Addressing Mode Summary (7-8 of 12) (ARM)

119. Chapter 2 — Instructions: Language of the Computer — 119 Addressing Mode Summary (9-10 of 12) (ARM)

120. Chapter 2 — Instructions: Language of the Computer — 120 Addressing Mode Summary (11-12) (ARM)

121. Chapter 2 — Instructions: Language of the Computer — 121 Synchronization (to avoid data racing) Two processors sharing an area of memory P1 writes, then P2 reads Data race if P1 and P2 don’t synchronize Result depends of order of accesses Hardware support required Atomic read/write memory operation No other access to the location allowed between the read and write Could be a single instruction E.g., atomic swap of register ↔ memory Or an atomic pair of instructions §2.11 Parallelism and Instructions: Synchronization

122. Chapter 2 — Instructions: Language of the Computer — 122 Synchronization (MIPS) Load linked: ll rt, offset(rs) Store conditional: sc rt, offset(rs) Succeeds if location not changed since the ll Returns 1 in rt Fails if location is changed Returns 0 in rt Example: atomic swap (to test/set lock variable) try: add $t0,$zero,$s4 ;copy exchange value ll $t1,0($s1) ;load linked sc $t0,0($s1) ;store conditional beq $t0,$zero,try ;branch store fails add $s4,$zero,$t1 ;put load value in $s4

123. Chapter 2 — Instructions: Language of the Computer — 123 Synchronization (ARM) Two processors sharing an area of memory P1 writes, then P2 reads Data race if P1 and P2 don’t synchronize Result depends of order of accesses Hardware support required Atomic read/write memory operation No other access to the location allowed between the read and write Single instruction for atomic exchange or swap Atomic swap of register ↔ memory ARM instruction: SWP §2.11 Parallelism and Instructions: Synchronization

124. Chapter 2 — Instructions: Language of the Computer — 124 Translation and Startup Many compilers produce object modules directly Static linking §2.12 Translating and Starting a Program

125. Chapter 2 — Instructions: Language of the Computer — 125 Assembler Pseudoinstructions Most assembler instructions represent machine instructions one-to-one Pseudoinstructions: figments of the assembler’s imagination move $t0, $t1 → add $t0, $zero, $t1 blt $t0, $t1, L → slt $at, $t0, $t1 bne $at, $zero, L $at (register 1): assembler temporary

126. Chapter 2 — Instructions: Language of the Computer — 126 Assembler Pseudoinstructions (ARM) Most assembler instructions represent machine instructions one-to-one Pseudoinstructions: figments of the assembler’s imagination LDR r0, #constant The assembler determines which instructions to use to create the constant in the most efficient way.

127. Chapter 2 — Instructions: Language of the Computer — 127 Producing an Object Module Assembler (or compiler) translates program into machine instructions Provides information for building a complete program from the pieces Header: described contents of object module Text segment: translated instructions Static data segment: data allocated for the life of the program Relocation info: for contents that depend on absolute location of loaded program Symbol table: global definitions and external refs Debug info: for associating with source code

128. Chapter 2 — Instructions: Language of the Computer — 128 Linking Object Modules Produces an executable image 1.Merges segments 2.Resolve labels (determine their addresses) 3.Patch location-dependent and external refs Could leave location dependencies for fixing by a relocating loader But with virtual memory, no need to do this Program can be loaded into absolute location in virtual memory space

129. Chapter 2 — Instructions: Language of the Computer — 129 Loading a Program (MIPS) Load from image file on disk into memory 1.Read header to determine segment sizes 2.Create virtual address space 3.Copy text and initialized data into memory Or set page table entries so they can be faulted in 4.Set up arguments on stack 5.Initialize registers (including $sp, $fp, $gp) 6.Jump to startup routine Copies arguments to $a0, … and calls main When main returns, do exit syscall

130. Chapter 2 — Instructions: Language of the Computer — 130 Loading a Program (ARM) Load from image file on disk into memory 1.Read header to determine segment sizes 2.Create virtual address space 3.Copy text and initialized data into memory Or set page table entries so they can be faulted in 4.Set up arguments on stack 5.Initialize registers 6.Jump to startup routine Copies arguments to r0, … and calls main When main returns, startup terminates with exit system call

131. Chapter 2 — Instructions: Language of the Computer — 131 Dynamic Linking Only link/load library procedure when it is called Requires procedure code to be relocatable Avoids image bloat caused by static linking of all (transitively) referenced libraries Automatically picks up new library versions

132. 132 Linking Object Files Reallocate the address in text segment and data segment –Link procedure A & B Object file header NameProcedure A Text size100 hex Data size20 hex Text segmentAddressInstruction 0lw $a0, 0($gp) 4jal 0 …… Data segment0(X)(X) …… Relocation information AddressInstruction type Dependenc y 0lwX 4jalB Symbol tableLabelAddress X- B- Object file header NameProcedure B Text size200 hex Data size30 hex Text segmentAddressInstruction 0sw $a1, 0($gp) 4jal 0 …… Data segment0(Y)(Y) …… Relocation information AddressInstruction type Dependenc y 0swY 4jalA Symbol tableLabelAddress Y- A-

133. 133 Reallocated Executable Image Text segment starts at 40 0000 $gp = 1000 8000 hex ** (8000 hex in 16b 2’s == -8000 hex ) Data segment starts at 1000 0000 hex = $gp + 8000 hex (= $gp – 0000 8000 hex ) Executable file header Text size300 hex Data size50 hex Text segmentAddressInstruction 0040 0000 hex lw $a0, 8000 hex ($gp) ** 0040 0004 hex jal 40 0100 hex …… 0040 0100 hex sw $a1, 8020 hex ($gp) 0040 0104 hex jal 40 0000 hex …… Data segmentAddress 1000 0000 hex (X)(X) …… 1000 0020 hex (Y)(Y) …… Stack Dynamic data Static data Text Reserved 1000 0000 hex 0040 0000 hex pc 0 $gp 1000 8000 hex

134. 134 Loader Operating system read executable file to memory and start it Read header determine size of text and data segment Create space for text and data segment Copy instructions and data into memory Copy parameter to main program Initialize register and stack pointer Jump to start-up routine Exit system call

135. 135 Lazy Procedure Linkage (Dynamically Linked Library, DLL) jal … lw jr … Text Data liID j … Text Dynamic Linker/Loader j … Text DLL Routine … jr Text jal … lw jr … Text Data DLL Routine … jr Text First call Subsequent call Indirect jump Loaded Program before 1 st call Loaded Program after 1 st call

136. Chapter 2 — Instructions: Language of the Computer — 136 Lazy Linkage Indirection table Stub: Loads routine ID, Jump to linker/loader Linker/loader code Dynamically mapped code

137. Chapter 2 — Instructions: Language of the Computer — 137 Starting Java Applications Simple portable instruction set for the JVM Interprets bytecodes Compiles bytecodes of “hot” methods into native code for host machine

138. Chapter 2 — Instructions: Language of the Computer — 138 C Sort Example (MIPS) Illustrates use of assembly instructions for a C bubble sort function Swap procedure (leaf) void swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } v in $a0, k in $a1, temp in $t0 §2.13 A C Sort Example to Put It All Together

139. Chapter 2 — Instructions: Language of the Computer — 139 The Procedure Swap (MIPS) swap: sll $t1, $a1, 2 # $t1 = k * 4 add $t1, $a0, $t1 # $t1 = v+(k*4) # (address of v[k]) lw $t0, 0($t1) # $t0 (temp) = v[k] lw $t2, 4($t1) # $t2 = v[k+1] sw $t2, 0($t1) # v[k] = $t2 (v[k+1]) sw $t0, 4($t1) # v[k+1] = $t0 (temp) jr $ra # return to calling routine

140. Chapter 2 — Instructions: Language of the Computer — 140 C Sort Example (ARM) Illustrates use of assembly instructions for a C bubble sort function Swap procedure (leaf) void swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } §2.13 A C Sort Example to Put It All Together

141. Chapter 2 — Instructions: Language of the Computer — 141 The Procedure Swap (ARM) Assembler directive vRN 0; 1st argument address of v k RN 1; 2nd argument index k temp RN 2; local variable temp2 RN 3; temporary variable for v[k+1] vkAddrRN 12; to hold address of v[k]

142. Chapter 2 — Instructions: Language of the Computer — 142 The Sort Procedure in C (MIPS) Non-leaf (calls swap) void sort (int v[], int n) { int i, j; for (i = 0; i < n; i += 1) { for (j = i – 1; j >= 0 && v[j] > v[j + 1]; j -= 1) { swap(v,j); } v in $a0, n in $a1, i in $s0, j in $s1

143. Chapter 2 — Instructions: Language of the Computer — 143 The Procedure Body (MIPS) move $s2, $a0 # save $a0 into $s2 move $s3, $a1 # save $a1 into $s3 move $s0, $zero # i = 0 for1tst: slt $t0, $s0, $s3 # $t0 = 0 if $s0 ≥ $s3 (i ≥ n) beq $t0, $zero, exit1 # go to exit1 if $s0 ≥ $s3 (i ≥ n) addi $s1, $s0, –1 # j = i – 1 for2tst: slti $t0, $s1, 0 # $t0 = 1 if $s1 < 0 (j < 0) bne $t0, $zero, exit2 # go to exit2 if $s1 < 0 (j < 0) sll $t1, $s1, 2 # $t1 = j * 4 add $t2, $s2, $t1 # $t2 = v + (j * 4) lw $t3, 0($t2) # $t3 = v[j] lw $t4, 4($t2) # $t4 = v[j + 1] slt $t0, $t4, $t3 # $t0 = 0 if $t4 ≥ $t3 beq $t0, $zero, exit2 # go to exit2 if $t4 ≥ $t3 move $a0, $s2 # 1st param of swap is v (old $a0) move $a1, $s1 # 2nd param of swap is j jal swap # call swap procedure addi $s1, $s1, –1 # j –= 1 j for2tst # jump to test of inner loop exit2: addi $s0, $s0, 1 # i += 1 j for1tst # jump to test of outer loop Pass params & call Move params Inner loop Outer loop Inner loop Outer loop

144. Chapter 2 — Instructions: Language of the Computer — 144 sort: addi $sp,$sp, –20 # make room on stack for 5 registers sw $ra, 16($sp) # save $ra on stack sw $s3,12($sp) # save $s3 on stack sw $s2, 8($sp) # save $s2 on stack sw $s1, 4($sp) # save $s1 on stack sw $s0, 0($sp) # save $s0 on stack … # procedure body … exit1: lw $s0, 0($sp) # restore $s0 from stack lw $s1, 4($sp) # restore $s1 from stack lw $s2, 8($sp) # restore $s2 from stack lw $s3,12($sp) # restore $s3 from stack lw $ra,16($sp) # restore $ra from stack addi $sp,$sp, 20 # restore stack pointer jr $ra # return to calling routine The Full Procedure (MIPS)

145. Chapter 2 — Instructions: Language of the Computer — 145 The Sort Procedure in C (ARM) Non-leaf (calls swap) void sort (int v[], int n) { int i, j; for (i = 0; i < n; i += 1) { for (j = i – 1; j >= 0 && v[j] > v[j + 1]; j -= 1) { swap(v,j); }

146. Chapter 2 — Instructions: Language of the Computer — 146 sort (ARM) Register allocation and saving registers for sort (ARM) Register allocation v RN 0; 1 st argument address of v n RN 1; 2 nd argument index n iRN 2; local variable i jRN 3; local variable j vjAddrRN 12; to hold address of v[j] vjRN 4; to hold a copy of v[j] vj1RN 5; to hold a copy of v[j+1] vcopyRN 6; to hold a copy of v ncopyRN 7; to hold a copy of n

147. Chapter 2 — Instructions: Language of the Computer — 147 sort (ARM) Procedure body – sort (ARM)

148. Chapter 2 — Instructions: Language of the Computer — 148 sort (ARM) Restoring registers and return – sort (ARM)

149. Chapter 2 — Instructions: Language of the Computer — 149 Effect of Compiler Optimization Compiled with gcc for Pentium 4 under Linux

150. Chapter 2 — Instructions: Language of the Computer — 150 Effect of Language and Algorithm

151. Chapter 2 — Instructions: Language of the Computer — 151 Lessons Learnt Instruction count and CPI are not good performance indicators in isolation Compiler optimizations are sensitive to the algorithm Java/JIT compiled code is significantly faster than JVM interpreted Comparable to optimized C in some cases Nothing can fix a dumb algorithm!

152. Chapter 2 — Instructions: Language of the Computer — 152 Arrays vs. Pointers Array indexing involves Multiplying index by element size Adding to array base address Pointers correspond directly to memory addresses Can avoid indexing complexity §2.14 Arrays versus Pointers

153. Chapter 2 — Instructions: Language of the Computer — 153 Example: Clearing and Array (MIPS) clear1(int array[], int size) { int i; for (i = 0; i < size; i += 1) array[i] = 0; } clear2(int *array, int size) { int *p; for (p = &array[0]; p < &array[size]; p = p + 1) *p = 0; } move $t0,$zero # i = 0 loop1: sll $t1,$t0,2 # $t1 = i * 4 add $t2,$a0,$t1 # $t2 = # &array[i] sw $zero, 0($t2) # array[i] = 0 addi $t0,$t0,1 # i = i + 1 slt $t3,$t0,$a1 # $t3 = # (i < size) bne $t3,$zero,loop1 # if (…) # goto loop1 move $t0,$a0 # p = & array[0] sll $t1,$a1,2 # $t1 = size * 4 add $t2,$a0,$t1 # $t2 = # &array[size] loop2: sw $zero,0($t0) # Memory[p] = 0 addi $t0,$t0,4 # p = p + 4 slt $t3,$t0,$t2 # $t3 = #(p<&array[size]) bne $t3,$zero,loop2 # if (…) # goto loop2

154. Chapter 2 — Instructions: Language of the Computer — 154 Example: Clearing and Array (ARM) clear1(int array[], int size) { int i; for (i = 0; i < size; i += 1) array[i] = 0; } clear2(int *array, int size) { int *p; for (p = &array[0]; p < &array[size]; p = p + 1) *p = 0; }

155. Chapter 2 — Instructions: Language of the Computer — 155 Comparison of Array vs. Ptr Multiply “strength reduced” to shift Array version requires shift to be inside loop Part of index calculation for incremented i c.f. incrementing pointer Compiler can achieve same effect as manual use of pointers Induction variable elimination Better to make program clearer and safer

156. Chapter 2 — Instructions: Language of the Computer — 156 ARM & MIPS Similarities ARM: the most popular embedded core Similar basic set of instructions to MIPS §2.16 Real Stuff: ARM Instructions ARMMIPS Date announced1985 Instruction size32 bits Address space32-bit flat Data alignmentAligned Data addressing modes93 Registers15 × 32-bit31 × 32-bit Input/outputMemory mapped

157. Chapter 2 — Instructions: Language of the Computer — 157 Compare and Branch in ARM Uses condition codes for result of an arithmetic/logical instruction Negative, zero, carry, overflow Compare instructions to set condition codes without keeping the result Each instruction can be conditional Top 4 bits of instruction word: condition value Can avoid branches over single instructions

158. Chapter 2 — Instructions: Language of the Computer — 158 Instruction Encoding

159. Chapter 2 — Instructions: Language of the Computer — 159 The Intel x86 ISA Evolution with backward compatibility 8080 (1974): 8-bit microprocessor Accumulator, plus 3 index-register pairs 8086 (1978): 16-bit extension to 8080 Complex instruction set (CISC) 8087 (1980): floating-point coprocessor Adds FP instructions and register stack 80286 (1982): 24-bit addresses, MMU Segmented memory mapping and protection 80386 (1985): 32-bit extension (now IA-32) Additional addressing modes and operations Paged memory mapping as well as segments §2.17 Real Stuff: x86 Instructions

160. Chapter 2 — Instructions: Language of the Computer — 160 The Intel x86 ISA Further evolution… i486 (1989): pipelined, on-chip caches and FPU Compatible competitors: AMD, Cyrix, … Pentium (1993): superscalar, 64-bit datapath Later versions added MMX (Multi-Media eXtension) instructions The infamous FDIV bug Pentium Pro (1995), Pentium II (1997) New microarchitecture (see Colwell, The Pentium Chronicles) Pentium III (1999) Added SSE (Streaming SIMD Extensions) and associated registers Pentium 4 (2001) New microarchitecture Added SSE2 instructions

161. Chapter 2 — Instructions: Language of the Computer — 161 The Intel x86 ISA And further… AMD64 (2003): extended architecture to 64 bits EM64T – Extended Memory 64 Technology (2004) AMD64 adopted by Intel (with refinements) Added SSE3 instructions Intel Core (2006) Added SSE4 instructions, virtual machine support AMD64 (announced 2007): SSE5 instructions Intel declined to follow, instead… Advanced Vector Extension (announced 2008) Longer SSE registers, more instructions If Intel didn’t extend with compatibility, its competitors would! Technical elegance ≠ market success

162. Chapter 2 — Instructions: Language of the Computer — 162 Basic x86 Registers

163. Chapter 2 — Instructions: Language of the Computer — 163 Basic x86 Addressing Modes Two operands per instruction Source/dest operandSecond source operand Register Immediate RegisterMemory Register MemoryImmediate Memory addressing modes Address in register Address = R base + displacement Address = R base + 2 scale × R index (scale = 0, 1, 2, or 3) Address = R base + 2 scale × R index + displacement

164. Chapter 2 — Instructions: Language of the Computer — 164 x86 Instruction Encoding Variable length encoding Postfix bytes specify addressing mode Prefix bytes modify operation Operand length, repetition, locking, …

165. Chapter 2 — Instructions: Language of the Computer — 165 Implementing IA-32 Complex instruction set makes implementation difficult Hardware translates instructions to simpler microoperations Simple instructions: 1–1 Complex instructions: 1–many Microengine similar to RISC Market share makes this economically viable Comparable performance to RISC Compilers avoid complex instructions

166. Chapter 2 — Instructions: Language of the Computer — 166 Fallacies Powerful instruction  higher performance Fewer instructions required But complex instructions are hard to implement May slow down all instructions, including simple ones Compilers are good at making fast code from simple instructions Use assembly code for high performance But modern compilers are better at dealing with modern processors More lines of code  more errors and less productivity §2.18 Fallacies and Pitfalls

167. Chapter 2 — Instructions: Language of the Computer — 167 Fallacies Backward compatibility  instruction set doesn’t change But they do accrete more instructions x86 instruction set

168. Chapter 2 — Instructions: Language of the Computer — 168 Pitfalls Sequential words are not at sequential addresses Increment by 4, not by 1! Keeping a pointer to an automatic variable after procedure returns e.g., passing pointer back via an argument Pointer becomes invalid when stack popped

169. Chapter 2 — Instructions: Language of the Computer — 169 Concluding Remarks Design principles 1.Simplicity favors regularity 2.Smaller is faster 3.Make the common case fast 4.Good design demands good compromises Layers of software/hardware Compiler, assembler, hardware MIPS: typical of RISC ISAs c.f. x86 §2.19 Concluding Remarks

170. Chapter 2 — Instructions: Language of the Computer — 170 Concluding Remarks Measure MIPS instruction executions in benchmark programs Consider making the common case fast Consider compromises Instruction classMIPS examplesSPEC2006 IntSPEC2006 FP Arithmetic add, sub, addi 16%48% Data transfer lw, sw, lb, lbu, lh, lhu, sb, lui 35%36% Logical and, or, nor, andi, ori, sll, srl 12%4% Cond. Branch beq, bne, slt, slti, sltiu 34%8% Jump j, jr, jal 2%0%