1. Figure 3-1 Block Diagram of SI4205
3. Technical brief
3.1 Transceiver (SI4205-BM, U401)
The RF parts consist of a transmitter part, a receiver part, a frequency synthesizer part, a voltage supply part, and a VCTCXO part.
The Aero I transceiver is the integrated RF front end for multi-band GSM/GPRS digital cellular handsets and wireless data modems. The integrated solution eliminates the IF SAW filter, external low noise amplifier (LNAs) for three bands, transmit and RF voltage controlled oscillator (VCO modules, and other discrete components found in conventional designs.
Figure 3-1 Block Diagram of SI4205

2. Table 3-1 The Logic and current
(1) Receiver part
The Aero I transceiver uses a low-IF receiver architecture which allows for the on chip integration of the channel selection filters, eliminating the external RF image reject filters and the IF SAW filter required in conventional superheterodyne architectures.
A. RF front end
RF front end consists of Antenna Switch(FL400), two SAW Filters(FL401, FL402) and dual band LNAs integrated in transceiver (U401).
The Received RF signals(GSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz) are fed into the antenna or Mobile switch.
The Antenna Switch(FL400) is used to control the Rx and Tx paths. And, the input signals VC1 and VC2 of a FL400 are directly connected to baseband controller to switch either Tx or Rx path on.
The logic and current is given below Table 3-1.
Three differential-input LNAs are integrated in SI4205. The GSM input supports the GSM 850 ( MHz) or E-GSM 900 ( MHz) bands. The DCS input supports the DCS 1800 ( MHz) band. The PCS input supports the PCS 1900 ( MHz) band.
The LNA inputs are matched to the 150Ω balanced output SAW filters through external LC matching networks. The LNA gain is controlled with the LNAG[1:0] and LNAC[1:0] bits in register 05h (Figure 3-2).
Table 3-1 The Logic and current
DCS TX
GSM TX

3. Figure 3-2 Block Diagram of Receiver part of SI4205
B. Intermediate frequency (IF) and Demodulation
A quadrature image-reject mixer downconverts the RF signal to a 100KHz intermediate frequency (IF) with the RFLO from the frequency synthesizer. The RFLO frequency is between to MHz, and is internally divided by 2 for GSM 850 and E-GSM 900 modes. The mixer output is amplified with an analog programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in register 05h (Figure3-2). The quadrature IF signal is digitized with high resolution A/D converters (ADCs).
The ADC output is downconverted to baseband with a digital 100KHz quadrature LO signal. Digital decimation and IIR filters perform channel selection to remove blocking and reference interference signals. The selectivity setting (CSEL=0) or a low selectivity setting (CSEL=1). The low selectivity filter has a flatter group channelization filter is in the baseband chip. After channel selection, the digital output is scaled with a digital PGA, which is controlled with the DGAIN [5:0] bits in register 05h.
The amplified digital output signal go through with DACs that drive a differential analog signal onto the RXIP,RXIN,RXQP and RXQN pins to interface to standard analog ADC input baseband ICs. No special processing is required in the baseband for offset compensation or extended dynamic range.
Compared to a direct-conversion architecture, the low-IF architecture has a much greater degree of immunity to dc offsets that can arise from RF local oscillator(RFLO) self-mixing, 2nd order distortion of blockers, and device 1/f noise.

4. Figure 3-3 Block Diagram of Transmitter part of SI4205
The transmit (Tx) section consists of an I/Q baseband upconverter, and offset phase-locked loop (OPLL) and two output buffers that can drive external power amplifiers (PA), one for the GSM 850 ( MHz) and E-GSM 900 ( MHz) bands and one for the DCS 1800 ( MHz) and PCS 1900 ( MHz) bands.
A. IF Modulator
The baseband converter(BBC) within the GSM chipset generates I and Q baseband signals for the Transmit vector modulator. The modulator provides more than 40dBc of carrier and unwanted sideband rejection and produces a GMSK modulated signal. The baseband software is able to cancel out differential DC offsets in the I/Q baseband signals caused by imperfections in the D/A converters.
The Tx-Modulator implements a quadrature modulator. A quadrature mixer upconverts the differential in-phase (TXIP, TXIN) and quadrature (TXQP, TXQN) signals with the IFLO to generate a SSB IF signal that is filtered and used as the reference input to the OPLL.
The IFLO frequency is generated between 766 and 896 MHz and internally divided by 2 to generate the quadrature LO signals for the quadrature modulator, resulting in an IF between 383 and 448 MHz. For the E-GSM 900 band, two different IFLO frequencies are required for spur management. Therefore, the IF PLL must be programmed per channel in the E-GSM 900 band.
Figure 3-3 Block Diagram of Transmitter part of SI4205

5. B. OPLL
The OPLL consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated TXVCO. The TXVCO is centered between the DCS 1800 and PCS 1900 bands, and its output is divided by 2 for the GSM 850 and E-GSM 900 bands. The RFLO frequency is generated between 1272 and 1483 MHz. To allow a single VCO to be used for the RFLO, high-side injection is used for the GSM 850 and E-GSM 900 bands, and low-side injection is used for the DCS 1800 and PCS 1900 bands. The I and Q signals are automatically swapped when switching bands. Additionally, the SWAP bit in register 03h can be used to manually exchange the I and Q signals.
Low-pass filters before the OPLL phase detector reduce the harmonic content of the quadrature modulator and feedback mixer outputs. The cutoff frequency of the filters is programmable with the FIF[3:0] bits in register 04h (Figure 3-3), and should be set to the recommended settings detailed in the register description.

6. Figure 3-4 Block Diagram of Frequency Synthesizer part of SI4205
The Aero I transceiver integrates two complete PLLs including VCOs, varactors, resonators, loop filters, reference and VCO dividers, and phase detectors. The RF PLL uses two multiplexed VCOs. The RF1 VCO is used for receive mode, and the RF2 VCO is used for transmit mode. The IF PLL is used only during transmit mode. All VCO tuning inductors are also integrated. The IF and RF output frequencies are set by programming the N-Divider registers, NRF1, NRF2 and NIF. Programming the N-Divider register for either RF1 or RF2 automatically selects the proper VCO. The output frequency of each PLL is as follows:
fout = N x f
The DIV2 bit in register 31h controls a programmable divider at the XIN pin to allow either a 13 or 26 MHz reference frequency. For receive mode, the RF1 PLL phase detector update rate (fφ) should be programmed fφ = 100 kHz for DCS 1800 or PCS 1900 bands, and fφ = 200 kHz for GSM 850 and E-GSM 900 bands. For transmit mode, the RF2 and IF PLL phase detector update rates are always fφ =200 kHz.
Figure 3-4 Block Diagram of Frequency Synthesizer part of SI4205

7. Figure 3-5 Functional Block Diagram of RF3133
3.2 Power Amplifier Module (RF3133, U400)
The RF3133 is a high-power, high-efficiency power amplifier module with integrated power control. The device is self-contained with 50 input and output terminals. The power control function is also incorporated, eliminating the need for directional couplers, detector diodes, power control ASICs and other power control circuitry; this allows the module to be driven directly from the DAC output.
The device is designed for use as the final RF amplifier in GSM 850, E-GSM 900, DCS and PCS handheld digital cellular equipment and other applications in the MHz, MHz, MHz, and MHz bands.
On-board power control provides over 37 dB of control range with an analog voltage input (TX_RAMP); and, power down with a logic “low” for standby operation (TX_ENABLE).
External control (BAND_SELECT) is used to select the GSM or DCS band with a logic high or low. A logic low enables the GSM band whereas a logic high enables the DCS band.
Figure 3-5 Functional Block Diagram of RF3133

8. Figure 3-6 VCTCXO circuit diagram
MHz Clock
The 13 MHz clock(X400) consists of a TCXO(Temperature Compensated Crystal Oscillator) which oscillates at a frequency of 13 MHz. It is used within the Si4205, analog base band chipset (U101, AD6521), digital base band chipset (U102, AD6525), and MIDI (U200) chipset.
Figure 3-6 VCTCXO circuit diagram
3.4 Power Supplies for RF Circuits
Two regulators are used for RF circuits. One is MIC5255 (U402), and the other is one port of ADP3522 (U301).
MIC5255 (U402) supplies power to transceiver (SI4205, U401).
One port of ADP3522 supplies power to VCTCXO (X400).
Main power (VBAT) from battery is used for PAM (RF3133, U400) because PAM requires high power.
Table 3-2 Power suppliers for RF circuits.
Supplier Voltage Powers enabled signal
U V U RF_EN
U V X400
Battery ~ 4.2 V U400
Figure 3-7 U402 circuit diagram

9. Figure 3-8 Block Diagram of the AD6525 Internal Architecture
3.5 Digital Main Processor (AD6525, U100)
(1) Architecture Overview
Figure 3-8 Block Diagram of the AD6525 Internal Architecture
The internal architecture of AD6525 is shown in Figure 3-8. AD6525 regroups three main subsystems connected together through a dynamic and flexible communication bys network. It also includes onboard system RAM (SRAM) and interfaces with external Flash Memory, Baseband converter functions, and terminal functions like MMI, SIM and Universal System Connector (USC).
The Digital Signal Processing (DSP) subsystem primarily hosts all the speech processing, channel equalization and channel codec functions. The code used to implement such functions can be stored in external Flash Memory and dynamically downloaded on demand into the DSP’s program RAM and Instruction Cache.

10. The microcontroller subsystem supports all the GSM terminal software, including the layer 1, 2 and 3 of the GSM protocol stack, the MMI, and applications software such as data services, test and maintenance. It is tightly associated with on-chip system SRAM and also includes boot ROM memory with a small dedicated routine to facilitate the initialization of the external Flash Memory via code download using the on-chip serial interface to the external Flash Memory interface.
The peripheral subsystem is composed of system peripherals such as interrupt controller, real time clock, watch dog timer, power management and a timing and control module. It also includes peripheral interfaces to the terminal functions: keyboard, battery supervision, radio and display. Both the DSP and the MCU can access the peripheral subsystem via the peripheral bus (PBUS).
For program and data storage, both the MCU subsystem and the DSP subsystem can access the on chip system SRAM and external memory such Flash Memory. The access to the SRAM module is made through the RAM Bus (RBUS) under the control of the bus arbitration logic. Similarly, access to the Flash Memory is through the parallel External Bus (EBUS).

11. Figure 3-9 Example of System Interconnection of AD6525 External Interfaces

12. Table 3-3 LCD module interface
(2) Interconnection with external devices
A. RTC Block Interface
Countered by external crystal oscillator (MC-146, X100).
The X-tal oscillates KHz.
B. LCD Module Interface
Controlled by LCD_CS, LCD_RES, ADD1, WR, DATA[0:15], LCD_DIM, and LCD_ID.
Table 3-3 LCD module interface
Description
LCD_CS
LCD driver chip enable. LCD driver IC has own CS pin
LCD_RES
This pin resets LCD module.
This pin determines whether the data to LCD module are display data or control data. ADD1 can select 16 bit parallel bus. ADD1 is also used to address flash memory.
ADD1 WR
Write control.
Parallel data lines. Color LCD driver chip uses the 16 bit data interface.
DATA[0:15]
LCD_DIM
Control signal for white LED(LCD backlight) driver IC.
LCD_ID
Reserved for future use.
C. RF Interface
The AD6525 control RF parts through RF_EN, ANT_SW1/2, PA_EN, PA_BAND, PDNB, S_EN, S_DATA, AND S_CLK.

13. Table 3-4 RF interface
GPO
Signal Name
Description 4
RF_EN
RF Enable / Disable 9
ANT_SW1
Antenna Switch Band Select 11
ANT_SW2
Antenna Switch Band Select 16
PA_EN
PAM Enable / Disable 17
PA_BAND
PAM Band Select 18
PDNB
Power Down Input 19
S_EN
Serial Enable Input 20
S_DATA
Serial Data Input 21
S_CLK
Serial Clock Input
D. SIM Interface
The AD6525 check status periodically in call mode if SIM card is inserted or not, but the AD6525 don't check in deep sleep mode.
Interface signals are SIM_DATAOP, SIM_CLK, SIM_RST, SIM_EN
Table 3-5 SIM interface
Description
SIM_DATAOP
This pin receives and sends data to SIM card. This model support 3.0 volt interface SIM card.
SIM_CLK
Clock 3.25 MHz frequency.
SIM_RST
Reset SIM Block
SIM_EN
Enable SIM Block
E. Key Interface
Key Interface includes 5 column (KEYCOL[0:4]) and 5 row (KEYROW[0:4]). AD6525 detects key press by interrupt.

14. F. ADP3522(PMIC, U301) Interface
There are 4 signals for PMIC (power management IC) interface.
Table 3-6 PMIC interface
Description
CHRDET
The pin is activated when charger is inserted.
CHG_EN
Enable charging
EOC
The pin is activated by PMIC when VBAT reaches 4.2V.
GATE_EN
Control signal from AD6525 to charge NiMH battery. Not used.

15. Figure 3-10 Functional Block Diagram of AD6521
3.6 Analog Main Processor (AD6521, U101)
(1) Block Diagram
Figure 3-10 Functional Block Diagram of AD6521

16. (2) BB Transmit Section
This section generates in-phase and quadrature BB modulated GMSK signals (BT = 0.3) in accordance with GSM Phase 2 specifications.
The transmit channel consists of a digital GMSK modulator, a matched pair of 10-bit DACs and a matched pair of reconstruction filter.
There are TXIP, TXIN, TXQP, TXQN, and RAMPDAC.
(3) BB Receiver Section
This section consists of two identical ADC channels that process baseband in-phase(I) and quadrature(Q) input signals.
Each channel consists of a coarse switched capacitor input filter, followed by a high-order sigma-delta modulator and a lowpass digital filter.
There are RXIP, RXIN, RXQP, and RXQN.
(4) Auxiliary Section
This section contains two auxiliary DACs(AFC DAC, IDAC) for system control.
This section also contains AUX ADC and Voltage Reference
AUX ADC : 6 channel 10 bits
AFC DAC : 13 bits
IDAC : 10 bits
(5) Voiceband Section
Receive audio signal from MIC. The phones use differential configuration.
Send audio signal to Receiver. The phones use differential configuration.
It interconnects external devices such as main microphone, main receiver, ear-phone and Hands free kit through the VINNORP, VINNORN, VOUTNORP, VOUTNORN, VINAUXP, VINAUXN, VOUTAUXP, and VOUTAUXN
VINNORP, VINNORN: Main MIC positive/negative terminal.
VOUTNORP, VOUTNORN: Main Receiver positive/negative terminal.
VINAUXP, VINAUXN: Hands free kit microphone positive/negative terminal.
VOUTAUXP, VOUTAUXON: Hands free kit speaker positive/negative terminal.

17. Figure 3-11 Circuit Diagram of AD6521.

18. Figure 3-12 Block Diagram of ADP3522.
3.7 Power Management IC (ADP3522, U301)
Block Diagram
Figure 3-12 Block Diagram of ADP3522.
Table 3-7 LDOs of ADP3522.

19. Power on sequence
If a battery is inserted, the battery powers the 6 LDOs.
Then if PWRONKEY is detected, the LDOs output turn on.
REFOUT is also enabled, Reset signal is generated and send to the AD6525.
LDO block
There are 6 LDOs in the ADP3522.
Charging Process
1. Check charger is inserted or not.
2. If ADP3522 detects that Charger is inserted, the CC-CV charging starts.
3. Exception: When battery voltage is lower than 3.2V, the trickle charge (low current charge mode) starts firstly. After the battery voltage reaches to 3.2V, the CC-CV charging starts.
Battery charging block
It can be used to charge Lithium Ion and/or Nickel Metal Hydride batteries. The phones use Li-Ion battery only. Charger initialization, trickle charging, and constant current charging are implemented in hardware.
Pins used for charging
CHGDET : Interrupt to AD6525 when charger is plugged.
CHG_EN : Control signal from AD6525 to charge battery.
EOC : Interrupt to AD6525 when battery is fully charged.
GATE_EN : Control signal from AD6525 to charge NiMH battery. But, not used.
TA (Travel Adaptor)
Input voltage : AC 110V ~ 240V, 50~60Hz
Output voltage : DC 5.2V(±0.2 V)
Output current : Max 800mA
Battery
Li-ion battery : Max 4.2V, Nom 3.7V
Standard battery : Capacity - 950mAh, Li-ion

20. Figure 3-13 Block Diagram of Memory.
3.8 Memory (U300)
The memory is consists of 128Mbit Nor Flash Memory and 32Mbit Pseudo SRAM. It has 16 bit parallel data bus and 22 bit address.
Software, RF calibration data, audio parameters and battery calibration data are stored in the Flash memory.
Figure 3-13 Block Diagram of Memory.
Figure 3-8 Pin Description of U300.

21. Figure 3-14 Circuit Diagram of Driver IC for LCD backlight.
3.9 LCD and LCD Backlight
(1) LCD Features
Display Mode : Transmissive 65K Color STN LCD
Color Depth : 32(Red) * 64(Green) * 32(Blue) = 65K Color
Resolution : 128 * RGB * 128 dots for Color display
Interface : 80-series MPU interface
Data bus : 16 bit Parallel interface
Duty ratio : 1/96 Duty for Color display
Viewing Direction : 12 o'clock
LCD Driver : S6B33B2 by SEC
Display RAM capacity : 132 x 16 x 162 = K bits for Color display
Control Signal is explained in Table 3-3.
(2) LCD Backlight
For LCD backlight illumination, there is a driver (U600) which is driven by LCD_DIM signal from AD6525. Power for the driver is supplied by VBAT.
Figure 3-14 Circuit Diagram of Driver IC for LCD backlight.

22. Figure 3-15 Circuit Diagram of Keypad Switches.
3.10 Keypad Switches and Key Backlight Illumination
(1) Keypad Switches
The key switches are metal domes, which make contact between two concentric pads on the keypad layer of the PCB when pressed. There are 21 switches (KB500-KB522), connected in a matrix of 5 rows by 5 columns, as shown in Figure, except for the power switch (KB500), which is connected independently. Functions, the row and column lines of the keypad are connected to ports of AD6525. The columns are outputs, while the rows are inputs and have pull-up resistors built in. When a key is pressed, the corresponding row and column are connected together, causing the row input to go low and generate an interrupt. The columns/rows are then scanned by AD6525 to identify the pressed key.
Figure 3-15 Circuit Diagram of Keypad Switches.

23. Figure 3-16 Circuit Diagram of Key backlight illumination
There are 6 blue LEDs for key backlight illumination which are driven by KEY_BACKLIGHT signal from AD6525.
Figure 3-16 Circuit Diagram of Key backlight illumination

24. Figure 3-17 Circuit Diagram of Microphone.
The microphone is placed to the front cover and is connected to main PCB. The audio signal is passed to VINNORP and VINNORN pins of AD6525. The voltage supply 2V55_VAN is output from ADP3522, and is a bias voltage for the VINNORP.
The VINNORP and VINNORN signals are A/D converted by the Voiceband ADC part of AD6521. The digitized speech is then passed to the DSP section of AD6525 for processing (coding, interleaving etc).
Figure 3-17 Circuit Diagram of Microphone.

25. Figure 3-18 Circuit Diagram of Dual Mode Speaker.
3.12 Dual Mode Speaker and MIDI IC
(1) Dual Mode Speaker
There is a control signal (SPK_RCV_EN) which is for enabling receiver or speaker because one dual mode speaker is used for both receiver and speaker. The signal is produced by AD6525 and controls the analog switch (U201).
The dual mode speaker is placed in the front cover and contacted to PCB.
A. Receiver Operation
The dual mode speaker is driven by VOUTNORP and VOUTNORN of AD6521 through a analog switch (U201) when it is used for receiver. The gain is controlled by the PGA in AD6521.
B. Speaker Operation
The dual mode speaker is driven by SPOUT1 and SPOUT2 of YMU759B (U200) through the analog switch (U201) when it is used for loud speaker.
Figure 3-18 Circuit Diagram of Dual Mode Speaker.

26. Figure 3-19 Circuit Diagram of MIDI-IC and external LDO.
(2) MIDI IC (YMU759B, U200)
The phone uses melody IC which makes the robust joyful melody sounds.
6 signals (MIDI_RST, ADD0, RD, MIDI_CS, WR, MIDI_INT) from AD6525 are used to control the melody IC.
Melody data (DATA[8:15]) is transferred to melody IC and played by the dual mode speaker.
External 3.3V LDO (U202) is used for the MIDI chip because the maximum output current of analog amplifier in melody IC is 300mA.
Figure 3-19 Circuit Diagram of MIDI-IC and external LDO.

27. Figure 3-20 Circuit Diagram of Headset Interface.
3.13 Headset Jack Interface
3-pole type ear-mic jack which has three electrodes such as Receiver+, Mic+, and GND. This type usually supports only single-ended configuration (VOUTAUXP for headset speaker and VINAUXP for headset mic) in the audio path.
There are two control signals for jack interface. One is JACK_DETECT which is for detecting the headset jack and the other is HOOK_DETECT which is enabled when hook of the headset is pressed. The pins (JACK_DETECT and HOOK_DETECT) interfaces with AD6525.
Figure 3-20 Circuit Diagram of Headset Interface.

28. 4. Trouble Shooting
4.1 RF Components
SW 400
FL400
FL401
FL402
U402
U401
U400
X400
Figure 4-1
Table 4-1
Reference
Description
Reference
Description
SW400
Mobile Switch
U400
Power Amplifier Module
FL400
Antenna Switch
U401
Transceiver
FL401
Saw Filter for GSM
U402
LDO
FL402
Saw Filter for DCS
X400
VCTCXO

29. 4.2 RX Trouble 4 5 1 3 2 6 Figure 4-2 START HP8922 : Test mode
62 CH, 7 level setting (TCH)
62 CH, -60dBm setting (BCCH)
START
4. Check
Ant SW &
Mobile SW
6. Check
RX IQ
3. Check
Control
Signal
5. Check
Saw Filter
Circuit
HP8922 : Test mode
Spectrum analyzer setting
Oscilloscope setting
2. Check
VCTCXO Circuit
1. Check
Regulator Circuit 4 5 1 3 2 6
Figure 4-2

30. VRF 4.2.1 Checking Regulator Circuit U402.5 U402.3 Figure 4-3
Pin3.
High ?
Yes
Changing the Board
RF 2.85V
O.K? No
Replace U402
Regulator Circuit is OK
See next Page to check
VCTCXO
Check Pin 3.
Check Pin 5.
VRF
Graph 4-1

31. 4.2.2 Checking VCTCXO Circuit
Figure 4-4
X400.3
X400.4
Check Pin 3.
Refer to Graph 4-2
13 MHz
O.K? No
VCTCXO Circuit is OK
See next Page to check
ANT SW & Mobile SW
Yes
Check Pin 4.
Refer to Graph 4-3
2.75V OK?
Changing X400
Check U301, PMIC
Graph 4-2
Graph 4-3

32. 4.2.3 Checking PLL Control Signal
S_DATA (TP404)
S_CLK (TP403)
S_EN (TP402)
PDNB (TP401)
Figure 4-5
Check TP 401.
Level is High?
Yes
Control Signal is OK
See next Page to check
ANT SW & Mobile SW No
Check TP 402, 403,
404. Check if there is
Any Major Difference
Refer to Graph 4-5
Similar?
Download the SW
Graph 4-4
Graph 4-5

33. 4.2.4 Checking Antenna Switch & Mobile Switch
SW400.ANT
SW400.RF
FL400.10
FL400.1
L405 (VC1)
L404 (VC2)
Figure 4-6
For these 2 test case,
No Call connection is needed
Check SW400 Pin ANT,RF
with RF Cable connected.
Open No
Changing SW400
Yes
Check SW400 Pin ANT,RF
with No RF Cable Connected
Short No
Changing SW400
Yes
Check L404, L405
Check whether Ant SW
Set as RX mode
Refer to Table 4-2
VC1 :Low
VC2 :Low No
Changing the Board.
Yes
Check RF Level of
FL (for GSM) & FL400.1 (for DCS)
Pin10 : ~ -62dBm No
Changing FL400
Pin 1 : ~ -63dBm
Table 4-2
Yes
Ant SW & Mobile SW is OK
See next Page to check
Rx IQ Signal
ANT SW
VC1
VC2
DCS TX 1
EGSM TX 1
EGSM, DCS RX
For this RF Level test case,
RX Stand alone Mode is needed refer to chapter 11

34. FL401 FL402 4.2.5 Checking SAW Filter Figure 4-7 Check RF Level of
Saw Filter Input
For GSM : FL401.1
Changing
C422 for GSM
FL401.1 : ~ -61dBm No
Yes
Check the parts are well Soldered
For GSM : C422
Changing FL401 for GSM, FL402 for DCS
Check RF Level of
Saw Filter Input
For GSM : FL401.3
For DCS : FL402.3
FL401.3: ~ -64dBm No
Soldering is
OK?
Yes
FL402.3: ~ -64dBm
Yes
Check the parts are well Soldered
For GSM : L402,C420
For DCS : L403, C425 No
Changing
L402, C420 for GSM
L403, C425 for DCS
Saw Filter is OK
See next Page to check
Rx IQ Signal
For the test,
RX Stand alone Mode is needed. Refer to chapter 11

35. 4.2.6 Checking RX IQ C417,C419 Figure 4-8 Graph 4-6 Check C417, C419.
Check if there is
Any Major Difference
Refer to Graph 4-6
Replace U401
Similar? No
Yes
Redownload the Software
And calibrate
Graph 4-6

36. 4.3 TX Trouble 6 1 3 5 2 4 Figure 4-9 START HP8922 : Test mode
62 CH, 7 level setting (TCH)
62 CH, -60dBm setting (BCCH)
Spectrum analyzer setting
Oscilloscope setting
START
2. Check
VCTCXO Circuit
1. Check
Regulator Circuit
3. Check
Control
Signals
5. Check
PAM Control Signal
4. Check
TX IQ
6. Check
Ant SW &
Mobile SW 6 1 3 5 2 4
Figure 4-9

37. VRF 4.3.1 Checking Regulator Circuit U402.5 U402.3 Figure 4-10
Check Pin 3.
Check Pin 5. No
Changing the Board
RF 2.85V
O.K? No
Pin3.
High ?
Yes
Yes
Regulator Circuit is OK
See next Page to check
VCTCXO
Replace U402
VRF
Graph 4-7

38. 4.3.2 Checking VCTCXO Circuit
Figure 4-11
X400.3
X400.4
Check Pin 3.
Refer to Graph 4-8
13 MHz
O.K? No
VCTCXO Circuit is OK
See next Page to check
ANT SW & Mobile SW
Yes
Check Pin 4.
Refer to Graph 4-9
2.75V OK?
Changing X400
Check U301, PMIC
Graph 4-8
Graph 4-9

39. 4.3.3 Checking PLL Control Signal
S_DATA (TP404)
S_CLK (TP403)
S_EN (TP402)
PDNB (TP401)
Figure 4-12
Check TP 401.
Level is High?
Yes
Control Signal is OK
See next Page to check
ANT SW & Mobile SW No
Check TP 402, 403,
404. Check if there is
Any Major Difference
Refer to Graph 4-11
Similar?
Download the SW
Graph 4-10
Graph 4-11

40. 4.3.4 Checking TX IQ C421,C424 Figure 4-13 Graph 4-12
Check C421, C424.
Check if there is
Any Major Difference
Refer to Graph 4-12
Replace U401
Similar? No
Yes
Redownload the Software
And calibrate
Graph 4-12

41. 4.3.5 Checking PAM Control Signal
TX_RAMP (R401)
PA_EN (R402)
Figure 4-14
Go to Next Step
Check TX_RAMP and PA_EN
Check if there is
Any Major Difference or not
Refer to Graph 4-13
Similar?
Yes No
Download S/W
Graph 4-13

42. 4.3.6 Checking Antenna Switch & Mobile Switch
SW400.ANT
SW400.RF
FL400.5
FL400.3
L405 (VC1)
L404 (VC2)
Figure 4-15
For the test,
TX Stand alone Mode is needed. Refer to chapter 11 (PL=7 for GSM, PL=2 for DCS)
Check L405, L404
Check whether Ant SW
Set as TX mode
Refer to Graph 4-14,15
Refer to Table 4-3
Check VC1, VC2 No
Changing board
Yes
Check RF Level of
FL400 Pin 5 (for GSM) & Pin 3 (for DCS)
Pin5 : ~29.5dBm
Go to Checking PAM control signal No
Pin 3 : ~26.5dBm
Table 4-3
Yes
Check SW400.ANT, RF with RF Cable connected. No
Changing SW400
ANT SW
VC1
VC2
Open
DCS TX 1
Yes
EGSM TX 1
Check SW400.ANT,RF
with RF Cable disconnected
Short No
Changing SW400
EGSM, DCS RX
Yes
END

43. (VC1)
(VC2)
Graph 4-14 DCS TX
(VC1)
(VC2)
Graph 4-15 EGSM TX

44. and check the level change
4.4 Power On Trouble
SETTING : Connect PIF, and set remote switch off at PIF
* Refer to Figure 16 No
Yes
START
Check Battery Voltage
> 3.35V ?
THE PHONE WILL
POWER ON.
Push power-on key
and check the level change
of U301 Pin 30
Check the voltage of
the following pins at U301
Pin 21 = 1.8V ?
Pin 25 = 2.75V ?
Pin 20 = 2.8V ?
Pin 3 = 2.0V ?
Logic level at pin 29 of U301
= HIGH?
Charge or Change Battery
Check the contact of power-key
or dome switch.
Replace U301
Redownload software

45. U301.21
1V8_VCORE
U301.20
2V8_VMEM
U301.25
2V75_VTCXO
U301.29
RPWRON
U301.30
POWERKEY
Figure 4-16
U301.3
2V0_VRTC

46. 4.5 Charging Trouble
SETTING : Connect the battery (3.4 ~ 4V) and the charging adaptor(TA) to the phone
START
Charging Connector(CN601) No
Re-solder CN601.
well-soldered?
Yes
Voltage at Pin 7 of U301 No
The charging adaptor(TA) is out of order.
= 5.2V?
Change the charging adaptor.
Yes
R300, Q300, D300
well-soldered? No
Re-solder R300, Q300, D300 .
Yes
Voltage across
D300 = ~0.3V No
Replace D300.
Yes
Voltage across
R300 is ~160mV. No
Replace R300.
Yes
~0.7< Voltage(Q300) < ~1.3V No
Replace Q300
Yes No
The battery may have the problem.
Is the battery charged ?
Change the battery and try again.
Yes
CHARGING WILL
OPERATE PROPERLY.

47. Charging current direction
Q300
D300
Figure 4-17
Charging current direction

48. 4.6 LCD Trouble CN600 Figure 4-18 U600.9 U600 (LCD_DIM) Figure 4-19
START
PIF Power On
Is the connection of LCD
module with LCD connector on
PCB OK?
Check the soldering
Of CN600 OK No
Not OK
Yes
Re-solder CN600
Replace U600
Does LCD backlight work
properly?
Reassemble LCD module with LCD connector
LCD
Working!!
Replace LCD module
Does LCD work
Check pin9 of U600 is
high when backlight are
turned on
Download S/W

49. 4.7 Receiver Trouble R206 R207 R209 U201 Figure 4-20 START
Replace the Main board. ABB is out of order.
Re-soldering U201
START
Check the signal level of
RCVP & RCVN at R206, R207. Are these voltage is about 1.2V?
Check the signal level at R209. Is it almost 0?
Yes No
Check the soldering of U201
Check the contact state of dual mode speaker.
Replace the dual mode speaker
The dual mode speaker will work properly.
Check the soldering
R206 & R207
Re-soldering R206, R207
Replace U201

50. 4.8 Speaker Trouble
SETTING: Connect PIF to the phone, and Power on. Enter The engineering mode, and set “Melody on” at Buzzer of BB test menu
START
Voltage across C235
= 3.3 V?
Replace U202
( Melody IC LDO) No
Yes
The voltage
of R209 is ~2.8V
Check the state of contact of dual mode speaker
Speaker
Working!!
Check the soldering of U202
Re-soldering U202
Voltage across C238
= 2.8 V?
Check the signal level of
R234, R236
Replace U302
Check the soldering of U302
Re-soldering U302
Replace U200
Replace U201
Check the soldering of U201
Re-soldering U201
Replace speaker

51. U202
U200
R209
R236
U201
C235
C238
R234
Figure 4-21

52. 4.9 MIC Trouble R211 R214 C221 C222 C217 C250 MIC200 Figure 4-22
Re-soldering R207
Replace the U301.
Check the C221 voltage=~1.9V, C222=a few hundred mV?
Yes
START
Check the C217 voltage is almost 2.2V(DC) No
Voltage at pin 23 of U301 is 2.55V(DC)?
Check R211 voltage=~1.4V, R214 voltage=~1.0V?
Receiver will work properly.
Re-soldering R210
Replace the MIC200
Check the soldering of R210
Replace the main board

53. 4.10 Vibrator Trouble
SETTING: After initialize Agilent 8960, Test in EGSM, connect PIF to the phone, and Power on. Enter The engineering mode, and set “Vibrator on” at Vibration of BB test menu
START
Is the voltage at pin 3 of Q500 near 0V?
Check the soldering of R500
Replace Q500
Yes No
Check the soldering of R501
Re-solder R500
Check the signal level of CN500
Re-solder Vibrator connector
Replace Vibrator
Vibrator
Working!!
Re-solder R501

54. CN500
R500
R501
Q500
Figure 4-24

55. 4.11 Key Backlight LED Trouble
SETTING: Connect PIF to the phone, and power on. Enter engineering mode,
and set “Backlight on “ at “BB test-Backlight” menu
Is the voltage level at Pin1 at
O301 about 1.2V?
START
PIF Power On
Are all LEDs LD300~LD305 working
Backlight LED
Working!!
Yes No
Check the soldering or
Replace LEDs not working
Check the soldering of
R313,R315
U302
LD301
LD304
R306
R309
R312
R316
R310
R307
LD305
LD302
R311
R313
R315
LD303
R305
R308
LD300
Figure 4-25
Q301
Figure 4-26

56. 4.12 SIM Detect Trouble
Setting : Insert the SIM into J301. Connect PIF to the phone, and power on.
START
Does the SIM supports 3V?
Voltage at pin 1 of J500 = 2.85V ?
Change the SIM and try again. Does it work properly?
Change the SIM. Our phone supports 3V SIM only.
Replace U301.
Yes No
Voltage at pin 18 of U301 = 2.85V ?
Check the soldering condition of J500.
Re-solder J500
Check the contact between J500 and SIM card.
Replace J500
The SIM is malfunctioned. Change the SIM.
Does it work properly after re-downloading SW ?
Change the main board.
SIM will be detected.
J500
PIN 1
Figure 4-27

57. SETTING:After Initialize Agilent 8960, Test in EGSM, DCS Mode
4.13 Ear Jack Trouble
SETTING:After Initialize Agilent 8960, Test in EGSM, DCS Mode
START
Inset the earphone to the phone
Does the audio profile of the phone change to the earphone mode? No
voltage at pin1 of U204 = 2.8V? No
Check the soldering U204 No
Check the soldering J200 No
Replace U204
Yes
Yes
Yes
Yes
Download S/W
Re-soldering U204
Re-soldering U204
Set the audio part of the test equipment to echo mode.
Yes
Can you
hear your voice from the earphone? No
Change the earphone and try again
Yes
Can you hear your voice from the earphone? No
Yes
Set the audio part of test equipment to PRBS or continuous wave mode
Earphone will work properly
Yes
Can you hear your voice from the earphone? No
voltage at C227=~1.2V No
Download S/W
Yes
Voltage at C224=~1.6V
Yes
Voltage at pin4 of U203=~1V No
Re-soldering U301
Re-soldering R219
Check soldering of R226,C228
Replace
main board
Re-soldering R226,C228
Check soldering C227,R224,J200
Not good
Re-solder C227,R224,J200
Yes
Replace
main board

58. J200
U204.1
U204
U203
Figure 4-28
C228
C227
C224
Figure 4-30
Figure 4-29

59. 5. Disassembly Instruction
6. Download and Calibration
7. Block Diagram - refer to G5400 service manual
8. Circuit Diagram
9. PCB Layout
10.Engineering Mode
11.Stand Alone Test
12.Auto Calibration
13. Exploded View & Replacement Part List