1. ENG6090 RCS1 ENG6090 Reconfigurable Computing Systems Hardware Description Languages Part 4: Modeling Dataflow

2. ENG6090 RCS2 Topics Concurrent Statements Concurrent Statements Conditional Signal Assignment Conditional Signal Assignment Selected Signal Assignment Selected Signal Assignment

3. ENG6090 RCS3 Concurrent Signal Assignment Thus far, all the signal assignments have been performed inside the process body. If the process contains only simple signal signal assignments, then this is too cumbersome. VHDL provides “shortcuts” through concurrent signal assignments. defined The concurrent signal assignments are defined by equivalent process statements by equivalent process statements. written The concurrent signal assignments are written inside architecture bodies inside architecture bodies.

4. ENG6090 RCS4 Dataflow Description how data moves through the system Describes how data moves through the system and the various processing steps. evaluated at the same time Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus, order of these statements doesn’t matter. most useful style when Data Flow is most useful style when series of Boolean equations can represent a logic.

5. ENG6090 RCS5 XOR3 Example

6. ENG6090 RCS6 Entity (XOR3 Gate) entity XOR3 is port( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; RESULT : out STD_LOGIC ); end XOR3;

7. ENG6090 RCS7 Dataflow Architecture (XOR3 Gate) architecture XOR3_DATAFLOW of XOR3 is signal U1_OUT: STD_LOGIC; begin U1_OUT <= A xor B; RESULT <= U1_OUT xor C; end XOR3_DATAFLOW; U1_out XOR3

8. ENG6090 RCS8 Full Adder: Data Flow Representation

9. ENG6090 RCS9 Decoders: Data Flow

10. ENG6090 RCS10 entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic); end entity decoder_2_to_4; architecture dataflow1 of dec_2_to_4 is Signal A0_n, A1_n: std_logic; begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1; end architecture dataflow1; entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic); end entity decoder_2_to_4; architecture dataflow1 of dec_2_to_4 is Signal A0_n, A1_n: std_logic; begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1; end architecture dataflow1; Decoder: Data Flow Example #1 Example: 2-to-4 decoder D0 D1 D2 D3 A(1) A(0) Interface Functionality A0_n

11. ENG6090 RCS11 zmux: z <= d0 when sel1 = ‘0’ and sel0 = ‘0’ else d1 when sel1 = ‘0’ and sel0 = ‘1’ else d2 when sel1 = ‘1’ and sel0 = ‘0’ else d3; zmux: process (d0,d1,d2,d3,sel0,sel1) is begin if sel1 = ‘0’ and sel0 = ‘0’ then z <= d0; elsif sel1 = ‘0’ and sel0 = ‘1’ then z <= d1; elsif sel1 = ‘1’ and sel0 = ‘0’ then z <= d2; else z <= d3; end; When Else Statement

12. ENG6090 RCS12 entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) ); end entity dec_2_to_4; architecture dataflow2 of dec_2_to_4 is begin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX"; end architecture dataflow2; entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) ); end entity dec_2_to_4; architecture dataflow2 of dec_2_to_4 is begin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX"; end architecture dataflow2; Decoder: Data Flow Example #2 Example: 2-to-4 decoder D(0) D(1) D(2) D(3) A(1) A(0) Interface Functionality A(1..0)D(3..0) 000001 010010 100100 111000

13. ENG6090 RCS13 Multiplexers: Data Flow

14. ENG6090 RCS14 entity mux_4_to_1 is port ( S : in std_logic_vector(1 downto 0); D : in std_logic_vector(0 to 3); Y : out std_logic ); end entity mux_4_to_1; architecture dataflow1 of mux_4_to_1 is begin Y <= D(0) when S = "00" else D(1) when S = "01" else D(2) when S = "10" else D(3) when S = "11" else "X"; end architecture dataflow1; entity mux_4_to_1 is port ( S : in std_logic_vector(1 downto 0); D : in std_logic_vector(0 to 3); Y : out std_logic ); end entity mux_4_to_1; architecture dataflow1 of mux_4_to_1 is begin Y <= D(0) when S = "00" else D(1) when S = "01" else D(2) when S = "10" else D(3) when S = "11" else "X"; end architecture dataflow1; Multiplexer: Data Flow Ex#1 Example: 4-to-1 Multiplexer D(0) D(1) D(2) D(3) S(1)S(0) Interface Functionality Y S1S0Y 00D0 01D1 10D2 11D3

15. ENG6090 RCS15 alu: with alu_function select result <= a+b after Tpd when alu_add, a-b after Tpd when alu_sub; alu: process (alu_function,a,b) is begin case alu_function is when alu_add => result <= a+b; when alu_sub => result <= a-b; end case; end; Selected signal assignment

16. ENG6090 RCS16 entity mux_4_to_1 is port ( S : in std_logic_vector(1 downto 0); D : in std_logic_vector(0 to 3); Y : out std_logic ); end entity mux_4_to_1; architecture dataflow2 of mux_4_to_1 is begin with S select Y <= D(0) when "00“; D(1) when "01“; D(2) when "10“; D(3) when "11“; "X“ when others; end architecture dataflow2; entity mux_4_to_1 is port ( S : in std_logic_vector(1 downto 0); D : in std_logic_vector(0 to 3); Y : out std_logic ); end entity mux_4_to_1; architecture dataflow2 of mux_4_to_1 is begin with S select Y <= D(0) when "00“; D(1) when "01“; D(2) when "10“; D(3) when "11“; "X“ when others; end architecture dataflow2; Multiplexer: Data Flow Ex#2 Example: 4-to-1 Multiplexer D(0) D(1) D(2) D(3) S(1)S(0) Interface Functionality Y S1S0Y 00D0 01D1 10D2 11D3

17. ENG6090 RCS17Summary Data Flow is a behavioral description in which the data dependencies in the description match those in a real implementation (best used for Boolean function implementation) It basically describes how data moves through the system and the various processing steps. Data Flow uses series of concurrent statements to realize logic. Think of the conditional signal assignment and selected assignment statements as routing structures rather than sequential control constructs. –The conditional signal assignment statement infers a priority routing structure, and a large number of when clauses leads to a long cascading chain. –The selected signal assignment statements infers a multiplexing structure, and a large number of choices leads to a wide mux.

18. ENG6090 RCS18

19. ENG6090 RCS19 Example rst_gen: reset <= ‘1’,’0’ after 200 ns when extended_reset; ‘1’,’0’ after 50 ns; Assume extended_reset is a constant. There are no signals named on the RHS. rst_gen: process is begin if extended_reset then reset <= ‘1’,’0’ after 200 ns; else reset <= ‘1’, ‘0’ after 50 ns; end if; wait; end;