1. International Technology Roadmap for Semiconductors
Assembly and Packaging
2007

2. Assembly and Packaging Roadmap 2007 Participants
W. R. Bottoms, Chair William Chen, Co-chair
Seiichi Abe
Joseph Adam
Mudasir Ahmad
Bernd Appelt
Ivor Barber
Muhannad Bakir
Mario Bolanos-Avila
Craig Beddinfield
Kwang Yoo Byun
Carl Chen
Chi Chi Chang
Bob N. Chylak
Sonjin Cho
Jason Cho
Chetan Desai          
Kishor Desai
Darvin Edwards
John T. "Jack" Fisher
Darrell Frear                             
George Harman
Ryo Haruta
Harry Hedler          
Harold Hosack
John Hunt
Mike Hung, Ph.D
Sreenivasan Koduri 
Li Li
Rongshen Lee
Dongho Lee
David Love
Mike Lamson 
HeeSoo Lee 
Choon Heung Lee
Sebastian Liau
Hongwei Liang 
Weichung Lo
Michitaka Kimura
Debendra Mallik
Lei Mercado
Stan Mihelcic
Abhay Maheshwari
Gary Morrison 
Jean-Pierre Moscicki
Hikari Murai
Rajen Murugan
Manoj Nagulapally 
Hirofumi Nakajima
Keith Newman
Luu Nguyen
Dick Otte
Masashi Otsuka
Bob Pfahl
Ralf Plieninger
Klaus Pressel
Marc Petersen 
Gilles Poupon
Charles Richardson
Bernd Roemer
Bill Reynolds
Bidyut Sen
Yong-Bin Sun
Coen Tak
Henry Utsunomiya
Shoji Uegaki
David Walter 
Lawrence Williams
M. Juergen Wolf
Jie Xue
Zhiping Yang, Ph.D.
Edgar Zuniga

3. ITRS A&P Chapter Organization
This Chapter is organized in eight major sections:
Difficult Challenges
Single Chip Packaging
Wafer Level Packaging
System-in-Package
Packaging for Specialized Functions
Advanced Packaging Technologies
Equipment Requirements
Cross-Cut Issues

4. Packaging Technology Challenges
Interconnect Scaling
Connect Si features (nm) to circuit board features (cm)
High Speed Signaling
Facilitate distortion –free signaling
Power Delivery
Efficiently deliver Power to enable high speed Si performance
Power Removal
Efficiently duct away dissipated power

5. Assembly and Packaging
Difficult Challenges
Pb free transition presents cost, reliability and process compatibility problems that are not yet fully resolved
A new generation of DFM & DFT solutions will be required for complex SiP, SoC 3D packaging
Thermal issues for complex 3D packaging
Stress induced changes in electrical properties for very thin die
Reliability for through wafer vias and die layer bonding
Warpage control for stacked die
Interconnect for nano-scale structures
Handling of ultra thin die and self assembly for very small die

6. The Pace of Change in Packaging is Accelerating
As traditional CMOS scaling nears it natural limits other technologies are needed to continue progress
This has resulted in an increase in the pace of innovation.
Many areas has outpaced ITRS Roadmap forecasts. Among these are:
Wafer thinning and handling of thinned wafers/die
Wafer level packaging
Incorporation of new materials
3D integration
The consumerization of electronics is the primary driving force.

7. Consumer Markets Drive Innovation
Consumers now drive more than half of integrated circuit revenue
Assembly and Packaging technology is a primary differentiator for consumer electronics
These factors are driving an unprecedented pace of innovation in:
New Materials
New Technologies
New Systems Integration architecture

8. New Packaging Technologies
Thinned wafers
3D systems integration
Wafer level packaging
Bio-chips
Integrated optics
Embedded/integrated active and passive devices
MEMS
Flexible (wearable) electronics
Printable circuits
Semiconductors
Light emitters RF
Interconnect
Texflex embroidered interconnects (Fraunhofer IZM)

9. Wafer Thinning It was easier than we thought.
Table 102a&b Thinned Silicon Wafer Thickness 200 mm/300 mm
Year of Production
2007
2008
2009
2010
2011
2012
2013
2014
2015
Min. thickness of thinned wafer (microns) (general product) 50 45 40
Min. thickness of thinned wafer (microns) (For extreme thin package ex. Smart card)* 20 15 10 8
Handling of Thinned wafers and die will be the limiting factor

10. Wafer Level Packaging One of the fastest growing
packaging architectures
WLP offers portable consumer products :
inherent lower cost
improved electrical performance
lower power requirements
Smaller size
Several architectural variations are in use today

11. Applications for New Materials
In this decade most if not all packaging materials will change due to changing functional and regulatory requirements
Bonding wire
Molding compounds
Underfill
Thermal interface materials
Die attach materials
Substrates
Solder

12. Many are in development
New Materials
Many are in use today
Many are in development
Cu interconnect
Ultra Low k dielectrics
High k dielectrics
Organic semiconductors
Green Materials
Pb free
Halogen free
Nanotubes
Nano Wires
Macromolecules
Nano Particles
Composite materials

13. Through Silicon Vias (TSV)
From front side
From back side
A Key technology for both wafer level packaging and 3D integration

14. System in Package (SiP) “The next step in Assembly and Packaging:
System in Package (SiP) “The next step in Assembly and Packaging: Systems Level Integration”
Introduction & Motivation
The basic elements generic to all SiP System level integration applications will be defined.
Examples will be used from various application areas to show how the basic elements are incorporated into these applications.

15. SiP: Multi-level System Integration
SiP may include SoC and other traditional packages
Packages may include:
Sub-system packages
Stacked thin packages including WLP, passives and active chips
Mechanical, optical and other non electrical functions
Complete systems or sub-systems with embedded components
Bare die
Source: Fraunhofer IZM

16. Categories of SiP
PiP, PoP and more

17. 3D Packaging increases Performance Density and enables system level integration
New System in Package (SIP) solutions enables rapid integration of different functions
Sibley
Spacer
256M NAND
Wire bonded stacked die
Converged computing and communications devices more performance per mm3.
More Mbits, More MIPS in shrinking volumetric dimensions
Thru-Si via Stacking
Small form factor for ultramobile PCs, hand-helds, phones & other consumer electronics

18. 3D Integration Table 101 System-in-a-Package Requirements
Year of Production
2007
2008
2009
2010
2011
2012
2013
2014
2015
Number of terminals—low cost handheld
700
800
Number of terminals—high performance (digital)
3050
3190
3350
3509
3684
3860
4053
4246
4458
Number of terminals—maximum RF
200
Low cost handheld / #die / stack* 7 8 9 10 11 12 13 14
high performance / die / stack 3 4 5
Low cost handheld / #die / SiP
high performance / #die / SiP 6
Minimum TSV pitch
10.0
8.0
6.0
5.0
4.0
3.8
3.6
3.4
3.3
TSV maximum aspect ratio**
TSV exit diameter(um)
3.0
2.5
2.0
1.9
1.8
1.7
1.6
TSV layer thickness for minimum pitch 50 20 15
Minimum component size (micron)
1005
600x300
400x200
200x100

19. 3D System Integration & Packaging
Stacked functional Layers with TSV and /or flexible polymer Interposer

20. 3D Stacked Die Package TSV of Tezzaron TSV of Ziptronix Samsung TSV
35 micron thick
Elpida (Poly-Si TSV)

21. Stacked die SiP packages 2014 through 2020
Limited by thermal density

22. Mold resin thickness on top of die: 0.10 mm
Typical SiP in 2010
TSV
0.025mm
Mold resin thickness on top of die: 0.10 mm
●　●　　　　　　　　　　　　　　　　　　　　●　●
1.0
Substrate thickness: 0.16
●　●　●　●　　　　　　　　　　●　●　●　●
Die attach thickness
　0.015
Ball pitch: 0.8 mm
Embedded

23. Interconnect Challenges for Complex SiPs
New circuit elements and components place expanded demands on the environment provided by the package
Evolutionary and revolutionary interconnect technologies are needed to enable the migration of microsystems from conventional state-of-art to 3D SiP.

24. Interconnect Requirements may be satisfied by Optical Wave Guide Solutions
Solder bump
Die
Mirror
VCSEL/PD
Substrate
Polymer pin
Lens
Fiber
Board-level integrated optical devices
Fiber-to-the-chip
Quasi free-space
optical I/O
Lens assisted quasi free-space optical I/O
Surface-normal optical waveguide I/O
Optical
source/PD
Examples of guided wave optical interconnects
for chip-to-chip interconnection.

25. Low k Dielectric will Require Low Stress IO Interconnections
Si die
Innovations in low stress electrical I/O can potentially eliminate the need for underfill reducing cost and processing complexity as I/O density rises.

26. SiP presents new challenges for Thermal management
High performance and form factor reduction generate high thermal density
Heat removal requires much greater volume than the semiconductor
Increased volume means increased wiring length causing higher interconnect latency, higher power dissipation, lower bandwidth, and higher interconnect losses
These consequences of increased volume generates more heat to restore the same performance
ITRS projection for 14nm node
Power density >100W/cm2
Junction to ambient thermal resistance <0.2degrees C/W

27. Thermofluidic Heat Sinks may be the Solution
Conventional
thermal Interconnects
Back-side integrated
fluidic heat sink and
Back and front-side
inlets/outlets
Thermal interface Material
fluidic heat sink using
TIM and inlets/outlets
tube
Die
fluidic I/O
Examples of thermofluidic cooling integration with CMOS technology

28. Summary Packaging innovation enables “More than Moore”
3D packaging technologies
Equivalent scaling through functional diversity
Consumer market demands drive innovation in packaging
Size, power, cost, performance, time to market
New materials and architectures are required to meet today’s market demand but will enable many future advances in packaging