1. M. A. Clarke-GaytherRAL/ASTeC/HIPPI SPG development Beam Chopper R & D for Next Generation High Power Proton Drivers Michael. A. Clarke-Gayther RAL / ASTeC / HIPPI

2. M. A. Clarke-GaytherRAL/ASTeC/HIPPI ‘Fast-Slow’ Chopping at RAL HIPPI WP4: The RAL† Fast Beam Chopper Development Programme Progress Report for the period: January 2004 – June 2005 M. A. Clarke-Gayther † † CCLRC Rutherford Appleton Laboratory, Didcot, Oxfordshire, UK EU contract number RII3-CT-2003-506395CARE/HIPPI Document-2005-008

3. M. A. Clarke-GaytherRAL/ASTeC/HIPPI ‘Fast-Slow’ Chopping at RAL Chopper 1 (fast transition) Chopper 2 / Beam dump (slower transition) BEAM Fast and slow chopper modules

4. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development M. A. Clarke-GaytherRAL/ASTeC/HIPPI 4 Phase 2 FPG system Dual polarity @ 1.4 kV max. 9 x Pulse generator cards High peak power loads Control and interface Combiner 9 x Pulse generator cards Power supply 9 x Pulse generator cards

5. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development Pulse ParameterESS Requirement MeasuredCompliancyComment Amplitude (kV into 50 Ohms)± 2.2± 1.5NoScalable Transition time (ns)≤ 2.0T rise = 1.8, T fall = 1.2Yes10 – 90 % Duration (ns)10 - 15 YesFWHM Droop (%)2.0 in 10 ns1.9 in 10 nsYesF 3dB ~ 300 kHz Repetition frequency (MHz)2.4 Yes Burst duration (ms)1.5 Yes Burst repetition frequency (Hz)50 YesDuty cycle ~ 0.27 % Post pulse aberration (%)± 2± 5NoReducible Timing stability (ps over 1 hour)± 100± 50YesPeak to Peak Burst amplitude stability (%)+ 10, - 5+ 5, - 3Yes Measured performance parameters for the Phase 2 FPG system

6. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development Time & amplitude dependent FPG waveform analysis / 324 MHz FETS scheme

7. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development † Assumes 4 kV SPG with ~ 9 ns transition time (10 – 90 %) ††Assumes 8 kV SPG with ~ 12 ns transition time (10 – 90%) FPG duty cycle and LF droop for the ESS and FETS schemes

8. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development FPG duty cycle droop compensation

9. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development FPG duty cycle droop compensation I.S. RAMPING (100 % CHOPPING)30 % CHOPPINGOFF

10. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development FPG duty cycle droop compensation I.S. RAMPING (100 % CHOPPING)30 % CHOPPINGOFF

11. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development FPG duty cycle droop compensation I.S. RAMPING (100 % CHOPPING)30 % CHOPPINGOFF

12. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development FPG duty cycle droop compensation CHBEAMI.S. RAMPINGCHBEAMCHBEAMCHBEAMCH 805 ns

13. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development FPG duty cycle droop compensation CHBEAMI.S. RAMPINGCHBEAMCHBEAMCHBEAMCH 805 ns

14. M. A. Clarke-GaytherRAL/ASTeC/HIPPI FPG development 0.8 m 0.28 m SPG Module SPG prototype system / Modular construction

15. M. A. Clarke-GaytherRAL/ASTeC/HIPPI SPG development Pulse ParameterESS Requirement MeasuredCompliancyComment Amplitude (kV into RLC load)± 6.0 Yes± 8 kV rated Transition time (ns)~ 12.0T rise ~ 13, T fall ~ 12Yes10 – 90 % Duration (μs)0.2 – 100 YesFWHM Droop (%)00YesDC coupled Repetition frequency (MHz)1.21.2 (≤ 6 μs burst)LimitedBurst limitation Burst duration @ 1.2 MHz1.5 ms≤ 6 μsNoBurst limitation Burst duration @ 0.1 MHz PRF-≤ 10 ms-PRF limitation Burst repetition frequency (Hz)50 YesDuty cycle ~ 0.27 % Post pulse aberration (%)± 2≤ ± 2Yes Timing stability (ns over 1 hour)± 0.5± 0.4YesPeak to Peak Burst amplitude stability (%)+ 10, - 5< + 10, -5Limited@ 0.1 MHz PRF Measured performance parameters for the ‘Breadboard’ SPG system

16. M. A. Clarke-GaytherRAL/ASTeC/HIPPI SPG development  SPG prototype system designed and part constructed Pre - prototype measurements show PRF limitation Prototype tests will explore switch limitations  Preparation of detailed specification for new HV switch FETS schemes A & B reduce voltage requirement  Identification of candidate HV switch manufacturers Behlke (Germany), DEI (USA), Kentech (UK)  Distribute SPG specification to manufacturers Prepare to modify existing SPG module design Status

17. M. A. Clarke-GaytherRAL/ASTeC/HIPPI Slow-wave structure development Helical structure B with L - C trimmers and adjustable delay Adjustable L-C trimmer Adjust cable lengths to change delay

18. M. A. Clarke-GaytherRAL/ASTeC/HIPPI Slow-wave structure development Helical structure C with L - C trimmers Quadrupole bore diameter

19. M. A. Clarke-GaytherRAL/ASTeC/HIPPI Slow-wave structure development  Re-design for 3 MeV operation Simulation using CST Microwave Studio code Implications of reduced delay to be explored Integrate adjustable L-C trimmers into new design  Manufacture pre-prototype modules Bench test using TDR & TDT techniques Planned activity

20. M. A. Clarke-GaytherRAL/ASTeC/HIPPI ‘Fast-Slow’ Chopping at RAL Summary  Three candidate chopping schemes for RAL FETS Schemes A & B ready for first engineering analysis  FPG can meet ESS and RAL FETS requirements Duty cycle droop compensation scheme to be tested  SPG prototype system designed and part constructed Pre - prototype measurements show PRF limitation  Slow – wave structure engineering concepts refined L – C impedance trimming and adjustable delay