1. Chapter 11 Interrupts Programming in Assembly and C

2. Objective
8051 提供插斷(interrupt)的功能，當 I/O 需服務時，CPU 會中斷目前的工作，而跳躍到此 I/O 的插斷服務程式 (interrupt service routine)，做完後才又回到原本的工作地方繼續執行。
8051 的插斷(interrupt)的功能，共針對 6 種 I/O： Reset、 timers、 external hardware、 serial communication，我們將會分別討論。
我們首先要瞭解 8051 插斷的運作方式，進而探討相關程式的撰寫。希望透過插斷的使用，讓 8051 工作得更有效率。

3. Review of Call A Subroutine
ROM addr.
0000
ROM addr.
DELAY
0300
MOV R5,#0FFH;
0004
LCALL DELAY; MOV A,#0AAH;
0007
0009
return address
0304
RET;
Opcode of LCALL DELAY:

4. Sections 11.1 8051 Interrupts 11.2 Programming timer interrupts
11.3 Programming external hardware interrupts
11.4 Programming the serial communication interrupt
11.5 Interrupt priority in the 8051/52
11.6 Interrupt programming in C

5. Section Interrupts

6. Inside Architecture of 8051
External interrupts
Timer/Counter
On-chip ROM for program code
External T/C
Interrupt Control
On-chip RAM
Timer 1
Counter Inputs
Timer 0 x
CPU
Serial Port
Bus Control
4 I/O Ports
OSC
P0 P1 P2 P3
TxD RxD
Address/Data
Figure 1-2. Inside the 8051 Microcontroller Block Diagram

7. Interrupt of the 8051 Each component runs individually.
Whenever any component needs CPU’s service, the component notifies the interrupt control by sending it an signal, referred to the interrupt signal.
CPU stops its regular work and jumps to serve this component.
Execute the Interrupt Service Routine (ISR) or interrupt handler.
After finishing the work of this component, CPU returns to its regular work.
紅綠燈 or 定時炸彈當範例說明 8051 的 CPU 可能要同時做很多事情
Ask 8051 有那一些 component, 分別可能會執行那一些工作? Ex: serial port RxD: need to move SBUF to ACC.
ISR 和 subroutine service 都是 programmer 自己寫的, 只是 ISR 有固定的位址與長度, 回到主程式用 RETI.

8. Six Interrupts in the 8051 Reset Two interrupt for the timers
TF0, TF1
Two interrupt for external hardware interrupts
INT0, INT1
Serial communication
TI or RI

9. Figure 4-1. 8051 Pin Diagram 8051 (8031) external hardware interrupt 
PDIP/Cerdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
GND
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051
(8031)
external hardware interrupt 

10. Create A Square Wave on P2.1 without Timer
CPU
To create a square wave on P2.1 and complement P1
We use DJNZ to generate a time delay.
The 8051 CPU is busy for DJNZ!
The 8051 CPU can only do one task.
R0=#08H
HERE:
DJNZ R0,HERE NO
YES
CPL P2.1
XRL P1,#0FFH

11. Create A Square Wave on P2.1 with Timer
CPU
Timer 0, mode 2
TH0=#0F0H, SETB TR0
The 8051 CPU is busy for monitoring TF0! NO
If TF0=1
YES
CPL P2.1
Timer 0
TH0
TL0
TF0
auto reload
roll over
XRL P1,#0FFH
CLR TF0

12. Create A Square Wave on P2.1 with Interrupt
CPU
Interrupt Control
Enable Interrupt
Timer 0, mode 2
TH0=#0F0H, SETB TR0 NO
If TF0=1
YES
Regular Work
ISR
An Interrupt Event
CPL P2.1
Timer 0
TH0
TL0
TF0
auto reload
roll over
XRL P1,#0FFH
RETI

13. Steps in Executing an 8051 Interrupt (1/2)
Upon activation of an interrupt, the microcontroller goes through the following steps:
It finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack.
It also saves the current status of all the interrupts internally.
It jumps to a fixed location in memory based on the interrupt vector table.
It also saves the current status of all the interrupts internally 是說不是儲存於 stack.

14. Steps in Executing an 8051 Interrupt (2/2)
Executing steps (continuous):
The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it.
The microcontroller starts to execute the interrupt service routine until it reaches the last instruction of the subroutine which is RETI (return from interrupt).
Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted.
First, it gets the program counter (PC) address from the stack by popping the top two bytes of the stack into the PC.
Then it starts to execute from that address.

15. Interrupt Service Routines
ISRs are similar to normal subroutines.
ISRs are generated by programs to handle interrupt events.
For interrupt event, its ISR is hold at a fixed location in memory.
ISR 和一般 subroutine 不同之處: 呼叫 ISR 可能在 program 的任何地方; ISR 沒有像 LCALL 後面跟著 subroutine 的位置可以知道跳躍到何處; ISR for each interrupt 只能是固定的位置; RETI 使用與 RET 同樣的方式回到 main program, 但會多做一些事情 (ex: CLR TF0). 1
TF0
jumps to B
ISR of timer0
main program
Reserved for Interrupt

16. The Addresses of ISRs
The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector table.
Table 11-1 is the interrupt vector table for 8051.
3 bytes for reset
8 bytes for timers and external hardware interrupts
If the service routine is too short to fit the ISR, an SJMP/LJMP instruction is placed in the vector table to point to the address of the ISR.

17. Table 11-1: Interrupt Vector Table for the 8051
ROM Location (Hex)
Pin
Reset
0000 9
External hardware interrupt 0 (INT0)
0003
P3.2
(12)
Timer 0 interrupt (TF0)
000B
External hardware interrupt 1 (INT1)
0013
P3.3
(13)
Timer 1 interrupt (TF1)
001B
Serial COM interrupt (RI or TI)
0023
跳到 Table 11.1 時, 要請同學回答每一個 interrupt 可以使用的 ISR 的 memory size.
Reset: 3 bytes; Timer 0 / timer 1: 9 bytes; External hardware interrupt: 9 bytes; Serial communication: depend on the location of main program as shown in Figure 11.1

18. Figure 11-1: Programs with Interrupts
;---- the first instruction is executed as the 8051 powers up
ORG ;ROM reset location
LJMP MAIN ;by-pass interrupt vector table
;---- ISR for INT0
ORG 0003H :
RETI
;---- ISR for Timer 0
ORG 000BH
....
;---- the wake-up program
ORG 30H
MAIN:
END
0000
LJMP MAIN
0003
ISR of INT0
000B
ISR of Timer0
0013
Reserved for Interrupt
ISR of INT1
001B
ISR of Timer1
0023
ISR of Serial
Communication
0030
Main Program

19. Notices Interrupt is disable upon RESET.
You can open the functionality of interrupt or not.
You can choose to disable some interrupt events,
You do not need to write ISRs for them.
Programmers must enable these interrupts before using them.

20. IE (Interrupt Enable)
In the 8051, the IE (interrupt enable) register denotes the usage of these interrupts.
Figure 11-2 : IE register 
Upon reset, all interrupts are disabled (masked).
The interrupts must be enabled by software.
IE is bit-addressable.
If we want to enable a special interrupt, set EA=1 first.
Enable each interrupt by setting its corresponding bit in IE. EA --
ET2 ES
ET1
EX1
ET0
EX0 D7 D0

21. Enable/Disable Interrupts
TF0
Timer/
Counter 0
INT1
External
Interrupt 1
TF1
Counter 1
RI/TI
Serial
Port
TF2
Counter 2
INT0
Interrupt 0
CPU EA
ET2 ES
ET1
EX1
ET0
EX0
IE register

22. Figure 11-2. IE (Interrupt Enable) Register
EA IE.7 Disables all interrupts.
If EA=0, no interrupt is acknowledged.
If EA=1, each interrupt source is individually enabled or
disabled by setting or clearing its enable bit.
IE.6 Not implemented, reserved for future use. *
ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt
(8052).
ES IE.4 Enables or disables the serial port interrupt. RI or TI
ET1 IE.3 Enables or disables timer 1 overflow interrupt. TF1
EX1 IE.2 enables or disables external interrupt 1. INT1
ET0 IE.1 Enables or disables timer 0 overflow interrupt. TF0
EX0 IE.0 enables or disables external interrupt 0. INT0 

23. Example 11-1 (1/2) Show the instructions to
enable the serial interrupt, timer 0 interrupt, and external hardware interrupt 1 (EX1)
disable (mask) the timer 0 interrupt
show how to disable all the interrupts with a single instruction.
Solution:
(a) MOV IE,# B
EA serial INT1 timer 0
Another way to perform the “MOV IE,# B” instruction is by using single-bit instructions as shown below.
SETB IE.7 ;EA-1, Global enable (D2 AF)
SETB IE.4 ;enable serial interrupt (D2 AC)
SETB IE.2 ;enable hardware interrupt 1 (D2 AA)
SETB IE.1 ;enable Timer 0 (D2 A9)
SETB IE.7 和 SETB EA 都是 D2 AF since IE has byte address A8H
SETB ES 會翻成 D2 AC; SETB EX1會翻成 D2 AA; SETB ET0 會翻成 D2 A9.

24. Example 11-1 (2/2) Or you can write
SETB EA ;EA-1, Global enable (D2 AF)
SETB ES ;enable serial interrupt (D2 AC)
SETB EX1 ;enable hardware interrupt 1 (D2 AA)
SETB ET0 ;enable Timer 0 (D2 A9)
Since IE is a bit-addressable register, we can use the following instructions to access individual bits of the register.
(b) CLR IE.1 ;mask (disable) timer 0 interrupt (C2 A9)
(c) CLR IE.7 ;disable all interrupts (C2 AF)

25. Section 11.2 Programming Timer Interrupts

26. Roll-over Timer Flag and Interrupt
In polling TF, we have to wait until the TF is raised.
HERE: JNB TF0, HERE
Using interrupt, whenever TF is raised, the microcontroller is interrupted and jumps to the interrupt vector table to service the ISR. 1
TF0
jumps to B
ISR of timer0
Timer 0 Interrupt Vector: 000BH 1
TF1
jumps to
B....
ISR of timer1
Timer 1 Interrupt Vector: 001BH

27. Example 11-2 (1/3)
Write a program that continuously gets 8-bits data from P0 and
sends it to P1 while simultaneously creating a square wave of 200
µs period on pin P2.1. Use timer 0 to create the square wave.
Assume that XTAL = MHz.
Solution:
We use timer 0 in mode 2 and interrupt to generate half period.
TH0 = 100 µs /1.085 µs = 92 for half clock.
We must avoid using memory space allocated to interrupt vector table. Therefore, we place the main memory in 0030H 1
TF0
jumps to B
ISR of timer0
main program
interrupt vector table
100 µs
200 µs
P2.1
interrupt

28. Example 11-2 (2/3)
;LJMP redirects the controller away from the interrupt vector table.
ORG 0000H
LJMP MAIN ;by-pass interrupt vector table
;The ISR for Timer 0 to generate square wave
;The ISR is small enough to fit in the 8 bytes.
ORG 000BH ;Timer 0 interrupt vector table
CPL P2.1 ;toggle P2.1 pin
RETI ;return from ISR
;In the ISR for timer 0, notice that there is no need for “CLR TF0” before “RETI”. The reason for this is that the 8051 clears the TF flag internally by the execution of RETI.

29. Example 11-2 (3/3) ;The main program for initialization
ORG 0030H ;after vector table space
MAIN: MOV P0,#0FFH ;make P0 an input port
MOV TMOD,#02H ;Timer 0,mode 2(auto reload)
MOV TH0,#0A4H ;TH0=A4H for -92
MOV IE,#82H ;IE= (bin) enable Timer 0
SETB TR ;Start Timer 0
BACK: MOV A,P ;get data from P0 and put it to P1
MOV P1,A ;loop unless interrupted by TF0
SJMP BACK
END

30. Example 11-3 (1/4)
Rewrite Example 11-2 to create a square wave that has a high portion of 1085 µs and a low portion of 15 µs. Assume XTAL = MHz. Use timer 1.
Solution:
Low: 15 µs = µs × 14 ← by DJNZ
High: 1085 µs = µs × 1000 ← by timer 1
we need to use mode 1 of timer 1.
1085 µs
15 µs
interrupt
one period 1
TF1
jumps to B
ISR of timer1
main program
interrupt vector table
P2.1

31. Example 11-3 (2/4) ORG 0000H ;by-pass interrupt vector table LJMP MAIN
;ISR for Timer 1 to generate square wave
ORG 001BH ;timer 1 interrupt vector table
LJMP ISR_T1 ;jump to ISR
;The main program for initialization
ORG 0030H ;after vector table
MAIN: MOV TMOD,#10H ;timer 1, mode 1
MOV P0,#0FFH ;make P0 an input port
MOV TL1,#018H ;TL1=18 the low byte of -1000
MOV TH1,#0FCH ;TH1-FC the high byte of -1000
MOV IE,#88H ;IE= enable timer 1.
SETB TR ;start timer 1

32. Example 11-3 (3/4) ;The main program for initialization
BACK: MOV A,P ;get data from P0 and put it to P1
MOV P1,A ;loop unless interrupted by TF0
SJMP BACK

33. Example 11-3 (4/4)
;Timer 1 ISR. Must be reloaded since not auto-reload
;The low portion of the clock is created by the 14 MC
ISR_T1:CLR TR ;stop Timer 1
CLR P ;end of high portion
MOV R2,# ; low portion(2 MC)
HERE: DJNZ R2,HERE ; (3 × 2 MC)
MOV TL1,#18H ;load T1 low byte value (2 MC)
MOV TH1,#0FCH ;load T1 high byte value (2 MC)
SETB TR ;starts timer 1 (1 MC)
SETB P ;P2.1=1, back to high (1 MC)
RETI ;start of high portion
END

34. Example 11-4 (1/2)
Write a program to generate a square wave of 50 Hz frequency on pin P1.2. This is similar to Example 9-12 except that it uses an interrupt for timer 0. Assume that XTAL= MHz.
Solution:
(a) The period of the square wave = 1 / 50 Hz = 20 ms.
(b) The half square wave = 10 ms = s × 9216
65536 – 9216 = in decimal = DC00H in hex.
ORG 0
LJMP MAIN
ORG 000BH
CPL P1.2
MOV TL0,#00
MOV TH0,#0DCH
RETI
P1.2
interrupt
50%
50%
50%
20ms

35. Example 11-4 (2/2) ;--main program for initialization ORG 30H
MAIN: MOV TMOD,# B ;timer 0, mode 1
MOV TL0,#00
MOV TH0,#0DCH
MOV IE,# B ;enable timer 0 interrupt
SETB TR0
HERE: SJMP HERE
END
8051
TH0
TL0
P1.2
50 MHz square wave

36. Section 11.3 Programming External Hardware Interrupts

37. External Hardware Interrupts (1/2)
The 8051 has two external hardware interrupts:
EX0: INT0, Pin 12 (P3.2)
EX1: INT1, Pin 13 (P3.3) 
These two pins are used in timer/counter.
INT is a trigger for hardware control (GATE=1).
Timer/counter is enabled only while the INT pin is high and the TR control pin is set.
They are enabled and disabled using the IE register.
EX0 by IE.0
EX1 by IE.2

38. External Hardware Interrupts (2/2)
Upon activation of these pins, the 8051 gets interrupted and jumps to the vector table to perform the ISR.
There are two activation levels for the external hardware interrupts:
Low level triggered (default)
Falling edge triggered
This is chosen by IT0/IT1 in TCON.
On Reset, IT0 and IT1 are both low, making external interrupts low level-triggered.

39. Low Level-triggered Interrupt
Also called as level-activated interrupt.
After the hardware interrupts in the IE register are enabled, the controller keeps sampling the INT pin for a low-level signal once each machine cycle.
INT0 and INT1 pins are normally high.
If a low-level signal is applied to them, it triggers the interrupt.
minimum duration of logic 0
1 MC
1.085ms
4 MC
1.085ms × 4
to INT0 or INT1 pins

40. Sampling the Low Level-triggered
The duration of the low level-triggered interrupt:
The pin must be held in a low state until the start of the execution of ISR. If the INT pin is bought back to a logic high before the start of the execution of ISR, there will be no interrupt.
The low-level signal at the INT pin must be removed before the execution of RETI; otherwise, another interrupt will be generated after one instruction is executed.
See Example11-5. 
講解完後再在黑板畫圖, 說明INT一直維持在低電位, 會使 interrupt 不斷地發生. CPU 回到主程式只執行一個指令就回到 ISR. 所以如果希望 interrupt 只發生一次, 就要在 ISR 結束前回到高電位.

41. Falling Edge-triggered Interrupt
IT is set to specify falling edge triggered external interrupt.
The controller keeps sampling the INT pin once each machine cycle. When a high-to-low signal is applied to INT0 (INT1) pin, the controller will be forced to jump to location 0003H (0013H) to service the ISR.
The external source must be held high for at least one MC, and then held low for at least one MC.
1 MC
1.085ms
to INT0 or INT1 pins
1.085ms
1 MC

42. Sampling the Falling Edge-triggered Interrupt
When a falling edge-triggered interrupt occurs:
The IE0 and IE1 of TCON register goes high whenever a falling edge is detected. 
When IE0/IE1=1, it indicates to the external world that the interrupt is begin serviced now and on this INT pin no new interrupt will be responded to until this service is finished.
The IE0 and IE1 function as interrupt-in-service flags.
The RETI clears IE0 (IE1) flag.
During the time that the ISR is being executed, the INT pin is ignored, no matter how many times it makes a high-to-low transition.
畫圖說明當偵測到 falling edge 後, IE 就會被設成 1, 直到執行 RETI 才又會被清為 0.
畫圖說明當偵測到 falling edge, IE 就會被設成 1 後, 不論之後 INT 出現多少個 falling edges, 只要 IE 仍等於 1, 這些 falling edge 都會被忽略, 全部只會執行一次 interrupt.

43. Figure 11-4. Activation of INT0 (1/2)
IE0
(TCON.1)
INT0 (Pin 3.2)
Interrupt Service Table with addr.
0003H
Edge-triggered
level-triggered
IT 0 =0
IT 0 =1
RETI IE0=0
INT0
in ISR IE0=1

44. Figure 11-4. Activation of INT1 (2/2)
IE1
(TCON.3)
INT1 (Pin 3.3)
Interrupt Service Table with addr.
0013H
Edge-triggered
level-triggered
IT 1 =0
IT 1 =1
RETI IE1=0
INT1
in ISR IE1=1

45. TCON Register (1/3) Timer control register: TCON TF1 TR1 TF0 TR0 IE1
Upper nibble for timer/counter, lower nibble for interrupts
Bit-addressable
TR0/TR1 are used to start or stop timers.
TF0/TF1 indicate if the timer has rolled over.
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Timer0
for Interrupt
(MSB)
(LSB)

46. TCON Register (2/3) IT (Interrupt type control bit)
IT0 for external interrupt 0; IT1 for external interrupt 1.
IT is set/cleared by software to specify falling edge/low-level triggered external interrupt.
IT=0 : low-level triggered interrupt
IT=1: falling edge triggered interrupt
In the 8051, once IT0/IT1 are set to 0 or 1, they will not be altered again since the designer has fixed the interrupt either as edge- or level-triggered. 
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Timer0
INT INT0
(MSB)
(LSB)

47. TCON Register (3/3) IE (External interrupt edge flag)
IE0 for external interrupt 0; IE1 for external interrupt 1.
IEs indicate whether or not an interrupt is in use for falling edge-triggered interrupt.
It does not latch level-triggered interrupts.
IE is set by CPU when the external interrupt edge (H-to-L transition) is detected.
Cleared by CPU when the ISR is finished. 
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Timer0
INT INT1
(MSB)
(LSB)

48. Example 11-5 (1/2)
Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low, it should turn on an LED.
The LED is connected to P1.3 and is normally off.
When it is turned on, it should stay on for a fraction of a second.
As long as the switch is pressed low, the LED should stay on.
Solution:
Pressing the switch will cause the
LED to be turned on.
If it is kept activated,
the LED stays on.
講解完後再在黑板畫圖, 說明 (or 發問) 一直按著按鈕讓 p13維持在低電位, 會使 interrupt 不斷地發生. CPU 回到主程式只執行一個指令就回到 ISR.
To LED
8051
P1.3
INT1
Vcc

49. Example 11-5 (2/2) ORG 0000H LJMP MAIN
;--ISR for hardware interrupt INT1 to turn on the LED
ORG 0013H
SETB P1.3
MOV R3,#255 ;stay on for a fraction of a second
BACK: DJNZ R3,BACK
CLR P1.3
RETI
;--main program for initialization
ORG 30H
MAIN: MOV IE,# B ;enable INT1
HERE: SJMP HERE ;stay here until get interrupt
END 

50. Example 11-6 (1/2)
Assuming that pin 3.3 (INT1) is connected to a pulse generator, write a program in which the falling edge of the pulse will send a high to P1.3 which is connected to an LED (or buzzer). In other words, the LED is turned on and off at the same rate as the pulses are applied to the INT1 pin.
This is an edge-triggered version of Example But in this example, to turn on the LED again, the INT1 pulse must be brought back high and then forced low to create a falling edge to activate the interrupt.
講解完後再在黑板畫圖 (or 用發問), 說明若 P3.3 也是連到 switch, 手一直壓著 switch 不放, 一直按著按鈕讓 p13維持在低電位, 因為使用 falling edge triggered, LED 會只亮一次, 之後都不會亮. 若是使用 low level triggered, LED 會一直亮,
因此在這一題, 若要使 LED 一直亮, 使 interrupt 不斷地發生, pin 13 要接到 pulse generator, 而且若 square wave 的 frequency 夠大, 就可讓 LET 頻繁地 turn on/off, 就會有燈一直亮的錯覺. 如果 frequency 很小, LED 幾乎是看不到亮燈的狀況.
INT1 to
LED
P3.3
P1.3
8051
pulse generator
interrupt

51. Example 11-6 (2/2) ORG 0000H LJMP MAIN
;--ISR for hardware interrupt INT1 to turn on the LED
ORG 0013H
SETB P1.3
MOV R3,#255 ;keep the buzzer on for a while
BACK: DJNZ R3,HERE
CLR P1.3
RETI
;--MAIN program for initialization
ORG 30H
MAIN: SETB TCON ;make INT1 edge-trigger interrupt
MOV IE,# B ;enable External INT 1
HERE: SJMP HERE
END

52. Example 11-7
What is the difference between the RET and RETI instructions?
Explain why we cannot use RET instead of RETI as the last instruction of an ISR.
Solution:
Both perform the same actions of popping off the top two bytes of the
stack into the program counter, and making the 8051 return to where it
left. However, RETI also performs an additional task of clearing the
interrupt-in-service flag, indicating that the servicing of the interrupt is
over and the 8051 now can accept a new interrupt on that pin. If you
use RET instead of RETI as that last instruction of the interrupt service
routine, you simply block any new interrupt on that pin after the first
interrupt, since the pin status would indicate that the interrupt is still
being serviced. In the cases of TF0, TF1, TCON.1, and TCON.3, they
are cleared due to the execution of RETI.

53. Section 11.4 Programming the Serial Communication Interrupt

54. Serial Communication Interrupt
In Chapter 10, the 8051 CPU waits for TI or RI to be raised. While we wait, we cannot do anything else.
In this section, interrupt-based serial communication are introduced.
This allows the 8051 to do many things, in addition to sending and receiving data from the serial communication port.
In Chapter 10, all examples of serial communications used the polling method.

55. RI and TI Flags and Interrupts
In the 8051 these is only one interrupt set aside for serial communication.
This interrupt is used to both send and receive data.
The interrupt is used mainly for receiving data.
If the interrupt bit IE.4 is enabled, when RI or TI is raised, the 8051 jumps to memory 0023H to execute the ISR.
You have to clear of the RI or TI flags yourself.
Because the 8051 does not know who generated it.
RETI does not clear RI or TI.

56. Example 11-8 (1/3)
Write a program in which the 8051 reads data from P1 and writes it
to P2 continuously while giving a copy of it to the serial COM port
to be transferred serially. Assume that XTAL= MHz. Set the baud rate at 9600Hz.
Solution:
The moment a byte is written into SBUF, it is framed and transferred serially. As a result, when the last bit (stop bit) is transferred the TI is raised, and that causes the serial interrupt to be invoked since the corresponding bit in the IE register is high.
We check for both TI and RI since both could have invoked interrupt (but do noting about RI=1).
P1  P2
 TxD

57. Example 11-8 (2/3) ORG 0 LJMP MAIN ORG 23H
LJMP SERIAL ;jump to serial interrupt ISR
; main program, initialization
ORG 30H
MAIN: MOV P1,#OFFH ;make P1 an input port
MOV TMOD,#20H ;timer 1,mode 2 (auto reload)
MOV TH1,#OFDH ;9600 baud rate
MOV SCON,#50H ;8-bit, 1 stop, REN enabled
MOV IE,# B ;enable serial interrupt
SETB TR ;start timer 1

58. Example 11-8 (3/3) ;------ stay in loop indefinitely ------ MOV A,P1
MOV SBUF,A
BACK: MOV A,P1
MOV P2,A
SJMP BACK
; Serial communication ISR
ORG 100H
SERIAL: JB TI,TRANS ;jump if TI is high
CLR RI ;do nothing but clear RI
RETI
TRANS: CLR TI ;clear TI
MOV SBUF,A ;transmit the copy of P1 again
END

59. Example 11-9 (1/3)
Write a program in which the 8051 gets data from P1 and sends it to P2 continuously while incoming data from the serial port is sent to P0.
Assume that XTAL = MHz.
Set the baud rate at 9600Hz.
Solution:
The main program is the same as the main program in Example 11-8.
Only the ISR of serial communication has a little different.
P1  P2
RxD  P0

60. Example 11-9 (2/3) ORG 0 LJMP MAIN ORG 23H
LJMP SERIAL ;jump to serial ISR
ORG 30H
; main program, initialization
MAIN: MOV P1,#0FFH ;make P1 an input port
MOV TMOD,#20H ;timer 1, mode 2 (auto reload)
MOV TH1,#OFDH ;9600 baud rate
MOV SCON,#50H ;8-bit,1 stop, REN enabled
MOV IE,# B ;enable serial interrupt
SETB TR ;start timer 1

61. Example 11-9 (3/3) ;------ stay in loop indefinitely ------
BACK: MOV A,P1
MOV P2,A
SJMP BACK
; Serial communication ISR
ORG 100H
SERIAL: JB TI,TRANS ;jump if TI is high
MOV A,SBUF
MOV P0,A
CLR RI
RETI
TRANS: CLR TI ;do nothing
END

62. Example (1/4)
Write a program using interrupts to do the following:
(a) Receive data serially and sent it to P0.
(b) Have P1 port read and transmitted serially, and a copy given to P2.
(c) Make timer 0 generate a square wave of 5 kHz frequency on P0.1.
Assume that XTAL = MHz. Set the baud rate at 4800Hz.
Solution:
Two interrupts (a)+(b) and (c) must be set:
TF0 (address 000BH) for square wave by timer 0: toggle P0.1 (c)
RI (address 0023H) for receive data  P0 (a)
P1  TI (address 0023H) for transmit data (b)
(notice: Timer 1 is used for baud rate. But it is not necessary to enable TF1)
An indefinitely loop in main program: P1  P2 (b)

63. Example 11-10 (2/4) ORG 0 LJMP MAIN ORG 000BH ;ISR for Timer 0
CPL P ;toggle P0.1
RETI
ORG 0023H
LJMP SERIAL ;jump to serial ISR
(c)
(a)+(b)

64. Example 11-10 (3/4) ; ------ main program, initialization ------
ORG 30H
MAIN:MOV P1,#0FFH ;make P1 as an input port
MOV TMOD,#22H ;Timer 0 &1,mode 2, auto-reload
MOV SCON,#50H ;8-bit,1 stop bit, REN enabled
MOV TH1,#0FAH ;4800 baud rate for (a)
MOV TH0,# ;5KHz square wave for (c)
MOV IE,# B ;enable serial, timer 0 interrupt
SETB TR ;start Timer 1 for (a)
SETB TR ;start Timer 0 for (c)
; stay in loop indefinitely for (b) : P1  P
MOV A,P1
MOV SBUF,A
BACK: MOV A,P1
MOV P2,A
SJMP BACK

65. Example 11-10 (4/4) ;------ Serial communication ISR ------ ORG 100H
SERIAL:JB TI,TRANS ;jump if TI is high
MOV A,SBUF ;for (a)
MOV P0,A
CLR RI
RETI
TRANS: CLR TI
MOV SBUF,A ;for (b)
END

66. Section 11.5 Interrupt Priority in the 8051/52

67. Interrupt Priority upon Reset
When the 8051 is powered up, the priorities are assigned according to Table 11.3:
If some interrupts are activated, they are latched and kept internally. The 8051 checks all five interrupts according to the sequence listed in Table If any is activated, it services it in sequence.
External Interrupt (INT0) high priority
Timer Interrupt (TF0)
External Interrupt (INT1)
Timer Interrupt (TF1)
Serial Communication (RI+TI)
Timer 2 (8052 only) (TF2) low priority

68. Example 11-11
Discuss what happens if interrupts INT0, TF0, and INT1 are
activated at the same time. Assume priority levels were set by the
power-up reset and that the external hardware interrupts are edge-
triggered.
Solution:
If these three interrupts are activated at the same time, they are latched and kept internally. Then the 8051 checks all five interrupts according to the sequence listed in Table 11-3.
INT 0 > TF 0 > INT 1 > TF 1 > RI or TI
If any is activated, it services it in sequence. Therefore, when the above three interrupts are activated, INT0 (external interrupt 0) is serviced first, then timer 0 (TF0), and finally INT1 (external interrupt 1).

69. Setting Interrupt Priority with the IP (Interrupt Priority) Register
To give a higher priority to any of the interrupts, we make the corresponding bit in the IP high.
Upon power-up reset, IP contains all 0s, making the priority sequence based on Table 11.3.
IP bit = 1: high priority
IP bit = 0: low priority
First, high-priority and low-priority: 2 levels
Second, if some interrupts have the same priority than others, they are serviced according to the sequence of Table 11.3.

70. Figure 11-8. Interrupt Priority Register (Bit Addressable)--
PT2 PS
PT1
PX1
PT0
PX0 --
IP.7
Reserved
IP.6
PT2
IP.5
Timer 2 interrupt priority bit (8052 only). PS
IP.4
Serial port interrupt priority bit.
PT1
IP.3
Timer 1 interrupt priority bit.
PX1
IP.2
External interrupt 1 priority bit.
PT0
IP.1
Timer 0 interrupt priority bit.
PX0
IP.0
External interrupt 0 priority bit.
User software should never write 1s to unimplemented bits, since they may be used in future products.

71. Example 11-12
(a) Program the IP register to assign the highest priority to INT1
(external interrupt 1), then (b) discuss what happens if INT0, INT1,
and TF0 are activated at the same time. Assume that the interrupts
are both edge-triggered.
Solution:
(a) MOV IP,# B or SETB IP.2
IP.2=1 to assign INT1 higher priority.
(b) The instruction is Step (a) assigned a higher priority to INT1 than the others:
INT1 > INT 0 > TF 0 > TF 1 > RI or TI
When INT0, INT1, and TF0 interrupts are activated at the same time, the 8051 services INT1 first, then it services INT0, then TF0.

72. Example 11-13
Assume that after reset, the interrupt priority is set by the instruction
“MOV IP,# B”. Discuss the sequence in which the
interrupts are serviced.
Solution:
The instruction “MOV IP,# B” sets the external interrupt 1 (INT1) and timer 1 (TF1) to a higher priority level compared with the rest of the interrupts.
They will have the following priority.
High priority: INT 1 > TF 1
Low priority: INT 0 > TF 0 > RI or TI
That is: INT 1 > TF 1 > INT 0 > TF 0 > RI or TI
Question: INT1>RI>INT0>TF0>TF1, IP=
Question: INT1>TF1>TF0>INT0>SI, impossible, 因為 TF1>TF0 表示 INT1, TF1 是 high priority group, 其他是 low priority group. 但在 low priority group 中 TF0> INT0 是不合理的, so impossible.

73. Interrupt inside an Interrupt
What happens if the 8051 is executing an ISR belonging to an interrupt and another interrupt is activated?
A high-priority interrupt can interrupt a low-priority interrupt.
This is an interrupt inside an interrupt.
ISR of Timer 1
main A C
main
The order is ABC
Timer 1 occurs
INT 0 occurs B
ISR of INT0

74. Triggering the Interrupt by Software
Sometimes we need to test ISR.
We can cause an interrupt with an instruction which raises the interrupt flag.
For example, if the IE bit for timer 1 is set, “SETB TF1” will interrupt the 8051 and force it jump to the interrupt vector table.

75. I/O Services A single microcontroller can serve several devices.
Two ways:
Polling method
Interrupt method

76. Polling Method
CPU
If INT0
Handle INT 0
YES NO
The microcontroller continuously monitors the status of a given device.
When the condition is met, it performs the service.
After that, it moves on to monitor the next device until every one is serviced.
The microcontroller check all devices in a round-robin fashion. NO
If TF0=1
YES
 NO
If RI/TI=1
YES
Handle Serial

77. Interrupt Method
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.
Whenever any device needs its service, the device notifies the microcontroller by sending it an interrupt signal.
Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device by executing the Interrupt Service Routine.

78. The Advantage of Interrupts
The use of microcontroller is more efficient.
Ex In polling system, HERE: JNB TI, HERE wastes much of the microcontroller’s time.
The microcontroller can monitor many devices simultaneously.
Each device can get service based on the priority assigned to it.
The microcontroller can ignore (mask) a device request.
雖然 polling 可以依據順序服務許多 services, 但不像 interrupt, 同時可以與多個 devices 同時執行自己的工作, 必要時才被 device 通知插斷, 就好像可以同時 service 多的 devices.
舉例來說, polling 像是 sales 自己一個接一個親自拜訪客戶; 而 interrupt 像是 sales 有一個手機, 可以待在家裡, 若客戶有問題, 自己會打電話給 sales, 然後 sales 就停止手上的工作, 執行此客戶的要求, 做完後再回到原來的事情上.
因為 polling 的方式是使用 round-robin, 所以是按照順序為 devices 服務, 若同時有 2 個 devices 要求服務, 完全就是依據目前檢查到那一個 device 來決定, 所以沒有辦法做到 priority.
Microcontroller 一旦被 interrupt 執行 interrupt service routine, 還可以被 priority 更高的 device 所 interrupt, 優先執行此 higher priority 的 ISR, 再回到 lower priority 的 ISR 工作.

79. Section 11.6 Interrupt Programming in C

80. 8051C Interrupt Numbers
The 8051 C compilers have extensive support for the 8051 interrupts with two major features as follows:
1. They assign a unique number to each of the 8051 interrupts, as shown in Table 11-4.
2. It can also assign a register bank to an ISR. This avoids code overhead due to the pushes and pops of the R0-R7.

81. Table 11–4 8051/52 Interrupt Numbers in C

82. Example (1/3)
Write an 8051 C program that continuously gets a single bit of data form P1.7 and sends it to P1.0. While simultaneously creating a square wave of 200 ms period on pin P2.5.
Use timer 0 to create the square wave. Assume XTML= MHz.
Solution:
Using Timer 0, mode 2.
100ms /1.085ms =92
TH0=256-92=164=A4H
8051
P1.0
LED
200ms
Switch
P1.7
P2.5

83. Example 11-14 (2/3) #include <reg51.h> sbit SW=P1^7;
sbit IND=P1^0;
sbit WAVE=P2^5;
//Interrup subroutine for creating WAVE
void timer0(void) interrupt 1 {
WAVE=~WAVE; //toggle pin }

84. Example 11-14 (3/3) void main(void) { //setup Timer Interrupt 1
TMOD=0x02;
TH0=0xA4; //TH0=-92
IE=0x82; //enable interrupts for timer 0
TR0=1; //start the timer 0
//setup SW  IND
SW=1; //make P1.7 an input pin
while(1) {
IND=SW; //send switch to LED }}

85. Example (1/4)
Write a C program that continuously gets a single bit of data from P1.7 and sends it to P1.0 in the main, while simultaneously
(a) creating a square wave of 200 ms period on pin P2.5.
(b) sending letter ‘A’ to the serial port.
Use timer 0 to create the
square wave.
Assume XTML= MHz.
Use the 9600 baud rate
as same as Ex 11-14
8051
P1.0
LED
200ms
Switch
P1.7
P2.5
Serial Port
TxD

86. Example 11-15 (2/4) Solution: #include <reg51.h> sbit SW=P1^7;
sbit IND=P1^0;
sbit WAVE=P2^5;
//Interrup subroutine for creating WAVE
void timer0(void) interrupt 1 {
WAVE=~WAVE; //toggle pin }

87. Example 11-15 (3/4) //Interrup subroutine for sending ‘A’
void serial0() interrupt 4 {
if (TI==1) {
SUBF = ‘A’; //send ‘A’
TI=0; //clear interrupt }
else {
RI=0; //clear interrupt

88. Example 11-15 (4/4) void main(void) { SW=1; //make P1.7 an input pin
TH1= -3; //9600 baud rate
TMOD=0x22;//mode 2 for both timers
TH0=0xA4; //TH0=-92
SCON=0x50;
TR0=1; TR1=1;
IE=0x92; //enable interrupts for timer 0
while(1) {
IND=SW; //send switch to LED }}

89. You are able to (1/2) Contrast and compare interrupts versus polling
Explain the purpose of the ISR (interrupt service routine)
List the interrupts of the 8051
Enable or disable 8051 interrupts
Program the 8051 timers using interrupts
Describe the two external hardware interrupts of the 8051/52

90. You are able to (2/2)
Contrast edge-triggered with level-triggered interrupts
Program the 8051 for interrupt-based serial communication
Define the interrupt priority of the 8051
Program 8051/52 interrupts in C