1. 1 2004 Winter ITRS Conference Lithography International Technical Working Group

2. 2 Lithography iTWG Participants at Winter Meeting Japan Masaomi Kameyama (Nikon) Isamu Hanyu (Fujitsu) Masaru Sasago (Matsushita) Naoya Hayashi (Dai Nippon Printing) Iwao Higashikawa (Toshiba) Masaki Yamabe (Fujitsu) Europe Mauro Vasconi (ST Microelectronics) Reiner Garreis (Carl Zeiss SMT) Andreas Dorsel (Carl Zeiss SMT) Korea Hanku Cho (Samsung) Taiwan Burn Lin (TSMC) Benjamin Lin (UMC) US Scott Hector (SEMATECH and Freescale Semiconductor) Giang Dao (SEMATECH and Intel)

3. 3 Highlights of Plans for 2005 Lithography Update Agreed on larger printed CD in resist and 75/25 error budget allocation for litho and etch Developed plan to determine effect of CD variability on device performance with Design, PIDS and FEP and consider increasing CD tolerance to > 10% Proposed definition of LWR and LER with Metrology TWG to account for metrology, transistor and interconnect performance Propose to reduce overlay tolerances to reflect use of dedicated tools to achieve better performance than shown in 2004 roadmap Plan to update potential solutions

4. 4 High level agenda for Litho iTWG meetings in 2005 SPIE: Should we plan a meeting at SPIE in February? No Spring: Review changes for year, each region proposes potential solutions Summer: Each iTWG chair reports on results of review of changes and potential solutions by each iTWG; identify items that should be addressed in next update year; editing of difficult challenges tables Winter: Start debating items identified at summer meeting and plan for next update year and

5. 5 Agenda for 2004 Winter iTWG and Cross TWG meetings Cross TWG preparations –Factory –Metrology –CSNTG –Modeling –Yield –Metrology –ESH Brief review of 2004 update Discuss 2005 changes

6. 6 Topics for Cross TWG Meetings Litho Factory Integration APC challenges (provided presentation by Vasconi) –Tool-to-tool matching for high mix fabs Environment control (airborne molecular contamination) Mask quality controlcumulative mask defects Mask shop operations Tool footprint, height and weight for future nodes; vibration requirements for fab vs. equipment isolators Gas usage requirements (for purging, EUV source fuel and debris buffering, etc.) Litho cell throughputintegrated throughput requires large area track with many modules and faster mask exchange times –Traffic jam of carriers in litho sector and mask storage capacity –Mask automation interfaces House water quality and pressure for immersion lithography; cooling water temperature and flow rate for EUV EM effects on mask and equipment

7. 7 Topics for Cross TWG Meetings Litho Metrology LER/LWR –Presentation by Hitachi –Propose metrology centric definition in ITRS but values should be broken into low and high spatial frequency regimes and determined based on effects on device performance –Low frequency roughness (affects transistor drive current, Vt and leakage current) –High frequency roughness (may affect interconnect reliability but smoothed by dopant diffusion and requires additional study) CD control –Increase in ADI (printed in resist) to ACI (after etch) CD bias proposed for 2005 Tool-to-tool matching requirements –Becoming very critical for mask and wafer CD metrology (see Microlithography World November 2004 and Leica presentation at SPIE BACUS September 2004) –Difficulty of achieving this might be noted with separate values for repeatability and matching Incorporating CD measurements into APC, scatterometry EUV tool components metrology

8. 8 Roughness definitions (reported as rms values) LWR = all spatial wavelengths between 1 micron and 20 nm over a 2 micron length with a spacing of 10 nm. LER = all spatial wavelengths between 1 micron and 15nm taken over a 2 micron length with a spacing of 7.5nm. –For monitoring specular scatteringmeasure from 15nm to twice the smallest interval using the smallest possible interval. –Longer wavelengths affect reliability, and short wavelengths increase line resistivity –Measure sidewall after barrier metal deposition

9. 9 Topics for Cross TWG Meetings Litho CSNTG CD control –US and Japan TWG studies concluded that <4nm 3 CD control has no known solutions –CD control will remain red for the present and future nodes –Printed gate length in resist values to be re-evaluated in 2005 LWR/LER effects on device performance –Propose metrology centric definition in ITRS but values should be broken into low and high spatial frequency regimes and determined based on effects on device performance –The low and high frequency cutoffs should be based on device performance effects DFM –Propose section on DFM in Litho (coordinate with Design and Yield) Litho field size adjustment (22 by 32mm now; should it be larger?)

10. 10 Results of logic device CD value survey Survey reflects present status of lithography in manufacturing at six companies which responded –Significant trim bias is used –M1 contacted half pitch in most cases is larger than 107 nm predicted for 2004 in 2003 update of ITRS Minimum value in range

11. 11 Results of logic device CD control survey Majority are not meeting the 10% CD Control targets at present. Majority support the 75/25 Litho/FEP responsibility split. (not shown in chart) Relaxing the nominal Printed Gate Length target does not solve the problem - need consensus on relaxation of gate length control from 10% to 12% in order to change cell colors from red. Majority will not approve relaxation of the 10% target, citing their company designers and specified finished product performance as reason for inflexibility. Minimum value in range

12. 12 Simulations indicated larger CD in resist provides better total CD control. They also indicated that ITRS total CD control values will probably not be achieved, starting at the 65nm node.

13. 13 Trends to manage CD control and yield Present approaches are not enough –More stringent design rule restrictions Single orientation, pitch restrictions –Larger CD on resist and larger etch bias –Relaxed minimum half pitch –Use of RET on more layers –Field by field and within field dose corrections Further actions--DFM –Automation of software analysis of weak spots in design and feedback to physical layout of cells RET applied to library cell layouts –Coordinates of weak points provided to mask and wafer CD metrology tools Focus and exposure are optimized for printing hot spot regions with maximum process latitude rather than for CD of CD bars. –Identification of critical timing paths to locally specify CD control and intensity of RET –Test programs optimized to detect electrical effects at weak points –Local corrections of mask to account for variations of scannermask specification to particular scanners –Software for reduction of slivers in design data is also being developed to reduce mask CD error and writing time. Based on AMD, Cadence, Cypress, IBM, Intel, ASML, PLAB, TI and Toshiba presentations at SPIE, PMJ, IEEE Litho and BACUS Example of content that may be included in text of Litho chapter for 2005

14. 14 Topics for Cross TWG Meetings Litho Modeling Polarization effects with NA>0.85, including illumination and mask effects Simulation accuracy for RET for low k 1 LWR effect on devices DFM Full chip predictive patterning simulation Stray light simulation accuracy

15. 15 Topics for Cross TWG Meetings Litho Yield DFM challengespredictive simulation of patterning performance and correction of design and mask data (check for weak designs) –Propose section in 2005 Litho ITRS chapter to be coordinated with Design and Yield iTWGs Metrology for shorts and opens Immersion-related defects Low k1 process effects on yield and device performance effects of larger CD variation deterministic errors driving yield loss –How does this fit with yield models?

16. 16 Topics for Cross TWG Meetings Litho ESH PFOS reduction and ban affects resist and developer material selection EUV challenges with sources –Power requirements –Proposal to use Li droplets

17. 17 Summary of 2004 Update to Lithography Chapter of the ITRS Lithography International Technical Working Group

18. 18 Changes to Lithography Tables in 2004 CD control (total CD control) –US and Japan TWG studies concluded that <4nm 3 CD control has no known solutions –CD control will remain red for the present and future nodes –Printed gate length in resist values to be re-evaluated in 2005 Definition of potential solutions –More specific criteria for N to N+2 nodes –N+3 node and beyond may be more broad ranging and inclusive Difficult challenges updated, emphasizing needs for immersion Changes to coloring, footnotes, etc. –Definition of overlay in overall lithography requirements Tables 77a and 77b –Mask table values updated –Resist table values updated More discussion needed (2005 updates probable) –LWR/LER definitions and values with input from PIDS, FEP and Metrology –APC requirements

19. 2004 Lithography exposure tool potential solutions Notes: EPL is a potential solution at the 65, 45 and 32-nm nodes for one geographical region, and PEL is a potential solution at the 32-nm node for one geographical region. RET will be used with all optical lithography solutions, including with immersion; therefore, it is not explicitly noted. Unofficial version of Figure 34; Not for publication Technology Node 2007 2013 2019 2004 2016 2010 hp90hp65hp32hp16hp22hp45 Research Required Development Underway Qualification/ Pre-Production Continuous Improvement DRAM Half-pitch (dense lines) Technology Options at Technology Nodes (DRAM Half-Pitch, nm) 90 193 nm 65 193nm + LFD 193nm immersion PEL 32 EUV 193nm immersion + LFD 157nm immersion + LFD, ML2 Imprint 22 EUV Innovative 157nm or 193 nm immersion ML2 Imprint, innovative technology 16 Innovative technology ML2, EUV + RET, imprint 45 193nm immersion + LFD EUV ML2, 157nm immersion, PEL RET = Resolution enhancement technology LFD = Lithography friendly design rules ML2 = Maskless lithography Lithography Potential Solutions in 2004 Update

20. 20 Summary of 2004 Lithography Chapter Updates Defined new criteria for evaluating near- term potential solutions Stronger emphasis on difficult challenges related to immersion lithography Continued emphasis on challenges for implementing cost-effective post-optical lithography solutions

21. 21 2003 ITRS potential solutions Technology Node 200720132019200420162010 hp90hp65hp32hp16hp22hp45 20032005200620082009201120122014201520172018 Research RequiredDevelopment UnderwayQualification/Pre-ProductionContinuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. DRAM Half-pitch (dense lines) Technology Options at Technology Nodes (DRAM Half - Pitch, nm) 90 193 nm + RET 65 Narrow options 193 nm + RET + litho-friendly designs 157 nm + RET + litho-friendly designs 193 nm immersion lithography EPL, PEL 32 EUV 157 nm immersion + RET + litho-friendly designs EPL, imprint lithography ML2 Narrow options 22 Narrow options EUV, EPL ML2, imprint lithography Innovative technology 16 Narrow options Innovative technology ML2, EUV + RET 45 157 nm + RET + litho-friendly designs Immersion 193 nm lithography + RET + litho-friendly designs EPL, PEL, ML2 PEL Narrow options Technology Node 200720132019200420162010 hp90hp65hp32hp16hp22hp45 20032005200620082009201120122014201520172018 Research RequiredDevelopment UnderwayQualification/Pre-ProductionContinuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Technology Node hp90hp65hp32hp16hp22hp45 20032005200620082009201120122014201520172018 200720132019200420162010 hp90hp65hp32hp16hp22hp45 hp90hp65hp32hp16hp22hp45 2003200520062008200920112012201420152017201820032005200620082009201120122014201520172018 Research RequiredDevelopment UnderwayQualification/Pre-ProductionContinuous ImprovementResearch RequiredDevelopment UnderwayQualification/Pre-ProductionContinuous Improvement Research Required Development Underway Qualification/Pre-ProductionQualification/Pre-ProductionContinuous Improvement DRAM Half-pitch (dense lines) DRAM Half-pitch (dense lines) DRAM Half Pitch (dense lines) - 90 193 nm + RET 65 Narrow options 193 nm + RET + litho-friendly designs 157 nm + RET + litho-friendly designs 193 nm immersion lithography EPL, PEL 32 EUV 157 nm immersion + RET + litho-friendly designs EPL, imprint lithography ML2 Narrow options 22 Narrow options EUV, EPL ML2, imprint lithography Innovative technology 16 Narrow options Innovative technology ML2, EUV + RET 45 157 nm + RET + litho-friendly designs Immersion 193 nm lithography + RET + litho-friendly designs EPL, PEL, ML2 PEL Narrow options 90 193 nm + RET 65 Narrow options 193 nm + RET + litho-friendly designs 157 nm + RET + litho-friendly designs 193 nm immersion lithography EPL, PEL 32 EUV 157 nm immersion + RET + litho-friendly designs EPL, imprint lithography ML2 Narrow options 22 Narrow options EUV, EPL ML2, imprint lithography Innovative technology 16 Narrow options Innovative technology ML2, EUV + RET 45 157 nm + RET + litho-friendly designs Immersion 193 nm lithography + RET + litho-friendly designs EPL, PEL, ML2 PEL Narrow options 193 nm + RET Narrow options 193 nm + RET + litho-friendly designs 157 nm + RET + litho-friendly designs 193 nm immersion lithography EPL, PEL 193 nm + RET + LFD 157 nm + RET + LFD 193 nm immersion EPL, PEL EUV 157 nm immersion + RET + litho-friendly designs EPL, imprint lithography ML2 Narrow options friendly designs ML2 Narrow options Narrow options Narrow options EUV, EPL ML2, imprint lithography Innovative technology Narrow options EUV, EPL ML2, imprint lithography Innovative technology Narrow options Narrow options Innovative technology ML2, EUV + RET Narrow options Innovative technology ML2, EUV + RET Narrow options 157 nm + RET + litho-friendly designs Immersion 193 nm lithography + RET + litho-friendly designs EPL, PEL, ML2 PEL Narrow options 90 65 32 22 16 45 157 nm + RET + litho-friendly designs Immersion 193 nm lithography + RET + litho-friendly designs EPL, PEL, ML2 PEL Narrow options Narrow options Narrow options 157 nm + RET + LFD 193 nm immersion + RET + LFD EUV, EPL, PEL, ML2 EUV 157 nm immersion + RET + LFD EPL, imprint ML2 EUV, EPL ML2, imprint Innovative technology ML2, EUV + RET Unofficial version of 2003 table; Not for publication RET = Resolution enhancement technology LFD = Lithography friendly design rules DRAM Half Pitch (nm)

22. 22 New criteria for potential solutions All infrastructure (masks, tools, resist,…) needs to be in place to meet the ramp for the specified node Technology must be planned to be used by IC makers in at least two geographical regions –For N+3 and later nodes with black coloring, the requirement to have more than one region support is not applicable Technology should be targeting leading edge critical layer needs Consideration (not a requirement): 100 tools worldwide over the life of that tool generation

23. 23 Proposed process for evaluating potential solutions Each regional TWG will evaluate options known to that TWG for each node against criteria Each TWG will judge the potential readiness of the technology for that node and make a recommendation to iTWG on whether to include it at that node –The process for deciding on a recommendation to the iTWG will established within each regional TWG. –Each TWG will judge the probability and or widespread use of each potential solution at each node. The potential solutions that qualify for each node will be ranked with highest probability and most widespread adoption ranked higher than other potential solutions A solution will be added if at least two regional TWGs support its inclusion.

24. 24 90 50 40 30 20 100 80 70 60 120 140 KrF+ PSM ArF+ PSM F 2 + PSM IPLPXLPEL ML2 EPL EUV Innovation 2001 Edition 65@2007 45@2010 32@2013 22@2016 90@2004 130@2001 ArF+ RET+LFD+Immersion 2003 Edition F 2 + RET+LFD+Immersion PEL ML2 EPL EUV +RET Imprint Innovation 2004 Update PEL EUV ML2 F 2 + LFD+Immersion Imprint Innovation +RET Innovative Immersion ArF +LFD+Immersion EPL PEL Transition of ITRS Litho Potential Solutions

25. 25 Difficult Challenges - Short Term (1)

26. 26 Difficult Challenges - Short Term (2)

27. 27 Difficult Challenges - Long Term (1)

28. 28 Difficult Challenges - Long Term (2)

29. 29 Lithography ITWG Chairmen and Co-chairmen for 2004

30. 30 Proposed Updates to Lithography Chapter of the 2005 ITRS Lithography International Technical Working Group

31. 31 High level action items for 2005 update Each region to propose potential solutions for each node based on process agreed in July 2004 (by April 2005) (Hector to send out spreadsheet for 2005 inputs by December 31, 2004) Check Metrology and FEP tables for consistency with Litho (Hector by September 2005) oProvide contamination levels for lens, mask and wafer purging at 193nm, EUV and 157nm to Yield and Factory Integration TWGs (Kameyama) oNikon and Canon discussing requirements, and resulting agreement will be sent to ASML by February 2005 oReview Mask tables with industry stakeholders and send results to iTWG (Hector in February 2005) oInclude APC in 2005 text and review APC section in Metrology (European TWG by April 2005) (Metrology to send text to the European TWG) oLitho iTWG to send quantitative data to Factory Integration iTWG where possible on EUV tool requirements, tool footprint, height and weight ranges, mask inspection and handling requirements in the fab (Hector to collect data) oFactory Integration to send data to Litho on mask shop data handling from DPI and Litho to send papers on progressive defects to Factory Integration (Hector) oLitho needs to identify owner to help Metrology with text on sensors inside litho tools (Hector)

32. 32 High level action items for 2005 update (cont.) oCommunicate proposed resist tables updates to iTWG resist experts (Hector by December 31, 2004) oDevelop qualitative tables and/or text for DFM, progression of RET approaches, R&D ROI, 450mm issues and cost of ownership for 2005 text (Hector by April 2005) oFind owner for 1X mask tables (Hector by February 2005) oSend LER white paper and references to Design and PIDS TWG (Hector) oConsider whether to include EPL tables in 2005 (Kameyama to discuss with Japan TWG) oReport back to TNSG on what % CD variation will result in 4nm and 3.5nm 3sigma CD control values (Hector by December 31, 2004) oCheck to see if +-2 degrees C water temperature control input to lithography tools is OK (Kameyama by April 2005) oYield TWG will send yield model survey results to Litho by the end of January 2005, Litho to review and provide feedback promptly (Hector) oLitho TWG to review M&S cross cut text and send comments to Modeling TWG (Hector oLitho to provide input on DFM and cost savings sections of M&S draft 2005 chapter (Hector after July meeting) oMetrology to send LWR/LER definitions to FEP, PIDS and Interconnect oPrepare proposed change to overlay requirements (Hector by February) oProvide ESH TWG range of power requirements for EUV sources (Hector) oProvide contact at Cymer for ESH TWG regarding use of Li in EUV sources (Hector)

33. 33 Possible 2005 Updates Text –Table showing progression of low k1 methods (Hector) –DFM section (Hector to complement Design chapter content) –APC detail in chapter (Vasconi) –Cost of ownership factors and throughput factors in text (formula and sensitivity) (Hector) CD control –Increase printed gate CD in resist –Consider separate flash CD control requirement (e. g. DRAM is presently >10%) (keep at 10%) Litho field size limit (presently 22by32mm, should it be larger?) Review colors and values in overall litho, resist and mask tables –Overlay split into tool-tool (same) and tool-to-itself (20% of half pitch) lines Resist table content changes Potential solutions –Each TWG to propose changes by July (preview in April) –Consider having potential solutions tables for high and low volume applications (No) (Explore some text to explain potential for two solutions)

34. 34 Example table: Increasing complexity of RET

35. 35 Proposed Changes to ITRS Lithography Requirements Consider update of tables to larger CD in resist (printed gate length) No change in 2004, subject to further discussions for 2005 Re-evaluate all colors –Examine long term coloring in context of primary solution at each node –No proposed changes to colors in Table 77b due to legitimately no known solutions to each box colored red. Overlay…

36. 36 Proposed Changes to ITRS Resist Tables Re-evaluate all colors in resist tables Input from resist suppliers toward matching capability (colors) with requirements (numbers) Re-examine defect size in resist films Spin coated resist defects saturates at 0.01 cm -2, will it really remain constant? Back surface particles updated based on FEP values Requirement for immersion-induced defects (revisit this in Julymaybe 2006) Improved LWR/LER definition and requirement values LER specification for contact holes (striations,… as opposed to lack of roundness) Resist requirements for contacts Separate line or footnote describing option of shrinking contact size in resist before etch Include statement about resist parameters applying to poly and or contacts in text Resist aspect ratio inconsistent (aspect ratio up to 3.5 possible; make sure that resist thickness matches aspect ratio requirements) Effect of resist diffusion length on tradeoff between LER/sensitivity/CD control for chemically amplified resists (address need for new resist approaches) Legend: Proposed change o In progress or – Not yet addressed

37. 37 Proposed Changes to ITRS Lithography Optical Mask Table 79a Extend tables to the 22nm half pitch node oRe-evaluate MEEF for contacts and lines oSEMATECH simulation results available for lines oLook at DOF budget to set mask blank flatness targets Re-evaluate colors for all parameters Proposed changes to be discussed at SEMATECH with mask industry reps in February 2005 (Open to all) Sent results to iTWG chair persons for further review Mask reflectivity drops too slowremoved in 2004 Relaxed CD specs for APSM may not be realistic; some error budget should be shared BIM CD control for masks important for active layer cycle time Legend: Proposed change o In progress or – Not yet addressed

38. 38 Proposed Changes to ITRS Lithography Optical Mask Table 79a (2) Definition of OPC sizes in Optical Mask Table –European iTWG to make proposal –Delay to 2005 How is linearity defined? –European iTWG to make proposal Review on 2-4-2004 concluded that linearity needs to be extended down to minimum SRAF size Magnification Propose no change at this point due to exposure tool supplier statements that no change is expected at first node with immersion oValues for inserted years based on linear interpolation, accurate formulas need to be used oFix footnote F. It is contradictory. oAdjust image placement down to 15 nm in 2004 and retain scaling from there. Legend: Proposed change o In progress or – Not yet addressed

39. 39 Proposed Changes to ITRS Lithography Mask Tables (2) EUV masks oRe-evaluate MEEF with rigorous EM simulation, including flare Propose technology parameter set on prior slide for 32nm node, will increase NA to 0.30 for later nodes Redefine parameters as needed based on recent SEMI standards updates No changes in 2004 but likely to be changes in 2005 to flatness values oUse rigorous EM simulation to quantify sidewall angle tolerances oConsider mask blank defect specifications based on FWHM and height of defects at surface of multilayer rather than PSL equivalent substrate defects oValues for inserted years based on linear interpolation, accurate formulas need to be used EPL masks Propose to remove table in 2005 due to EPL becoming regional solution 1X mask tables? PEL Nanoimprint Legend: Proposed change o In progress or – Not yet addressed

40. 40 Calculated MEEF values: 90nm node Simulations and analysis by Cinnamon Smith and Scott Hector (SEMATECH)

41. 41 Calculated MEEF values: 90nm node with APSM Simulations and analysis by Cinnamon Smith and Scott Hector (SEMATECH)

42. 42 Calculated MEEF values: 65nm node Simulations and analysis by Cinnamon Smith and Scott Hector (SEMATECH)

43. 43 Calculated MEEF values: 65nm node with APSM Simulations and analysis by Cinnamon Smith and Scott Hector (SEMATECH)

44. 44 Calculated MEEF values: 45nm node Simulations and analysis by Cinnamon Smith and Scott Hector (SEMATECH)

45. 45 Calculated MEEF values: 45nm node with APSM Simulations and analysis by Cinnamon Smith and Scott Hector (SEMATECH)

46. 46 Calculated MEEF values: 32nm node Simulations and analysis by Cinnamon Smith and Scott Hector (SEMATECH)

47. 47 Simulation Parameters Used Panoramic Technologies simulator Focus Plane –-500nm to +500nm in steps of 100nm –Allows for process windows and Depth of Focus to be measured Mask Linewidth Bias –-50nm to +50nm in steps of 10nm –-40nm to +40nm for 32nm EUV Mask in steps of 10nm –Allows for a reasonable wafer linewidth variance of 2.5nm Mask type varied –MoSiON; n=2.489+i0.661; thickness = 65.4nm –50 nm of Cr with 20 nm of CrOx for absorbers. The complex indices of refraction for Cr and CrOx were 0.8418+i1.6472 and 1.6364+i0.6502. –Used etch depth of 172nm, with fused silica index of 1.563.

48. 48 Determining the MEEF 3 pt average CD and slope Ideal case y = 1x Actual case y = 2.8125x - 162.96 3 points allow a linear measurement of a nonlinear relationship

49. 49 Parameters for MEEF determination Values for 65-nm node agreed upon by subset of the US Lithography Technical Working Group in 2003 k1 is for MPU half pitch

50. 50 MEEF simulation assumptions for 32nm node