Nios II and SOPC Builder

Nios II and SOPC Builder
頁眉 FUTURE ELECTRONICS Nios II and SOPC Builder 培训 For Internal Use Only

在这一天我们将了解到的边学边实验什么是软核CPU，使用软核CPU和传统硬核CPU的不同
頁眉在这一天我们将了解到的　　什么是软核CPU，使用软核CPU和传统硬核CPU的不同　　什么是NIOS II，使用NIOS进行系统设计的优势和好处什么是SOPC 如何使用SOPC去构建一个满足客户需求的NIOS II CPU(性能分析，器件选择，嵌入式扩展）　　如何将定制好的CPU放入FPGA，综合步线,软件程序编写调试．关于NIOS2 Avalon Switch Fabric总线用户指令模块　　NIOSII的程序存放空间问题．存储器的选择和使用　　一些成功的NIOS设计案例边学边实验 For Internal Use Only

什么是软核CPU，使用软核CPU和传统硬核CPU的不同
传统硬核处理器传统的硬核处理器件是一种已经设计固定，不可扩充不可修改的固定硬件CPU,比如ARM核，５１核，powerpc,８６０内核等，其性能，IO,嵌入式设备，中断等硬件指标都是固定芯片设计好的．当我们做一个设计时，就需要我们去在众多的处理器中选择一款适合自己项目的处理器来使用　　什么是适合自己的处理器呢？ A 运算性能 B 外围接口及嵌入式的硬件设备,存储器支持 C IO 中断资源，片内外存储器资源，DMA通道的数量等 D 功耗

NIOS软核，一种由用户来定制，量身裁减的CPU内核
頁眉 NIOS软核，一种由用户来定制，量身裁减的CPU内核 nios软核是一种利用FPGA内部逻辑资源，采用可选的Alter内核MCU IP,然后根据用户具体的应用和需要进行外围嵌入式硬件的裁减，定制而成的CPU.其性能，适用范围，外围硬件扩展能力可以完全由客户自己去选择和生成．而选择和生成所有的这一切过程都由后面将谈到的SOPC系统来完成．还是上面的问题.那什么是适合自己的处理器呢？　　A 运算性能　　　　　　 B 外围接口及嵌入式的硬件接口　　　MCU的内核结构（IP)　　　　　　　　　例如网口（MAC),I2C,SPI,SDRAM接口，DDR/DD2 　　　是可以选择的接口，flash接口，　　　　　　　　　　　　　　　　　　　　 C IO 中断资源，片内外　　 D 功耗　　存储器资源，DMA通道　整个MCU部分被放进FPGA 　　IO,中断.DMA通道数量完全是客户自己来选择的 For Internal Use Only

What is Nios II? Developed Internally By Altera Harvard Architecture
頁眉 What is Nios II? Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor Developed Internally By Altera Harvard Architecture Royalty-Free - Nios II Plus All Peripherals Written In HDL - Can Be Targeted For All Altera FPGAs - Synthesis Using Quartus II Integrated Synthesis Avalon Switch Fabric UART GPIO Timer SPI SDRAM Controller On-Chip ROM RAM Nios II CPU Debug Cache FPGA Why is Nios so attractive? Traditional approach – board level integration using discrete components

NIOS2软核更多的特殊特性和优点用户自定义硬件指令高度可配置的DSP处理性能软件逻辑硬件化实现的的ICH功能与逻辑的高度紧密集合
頁眉 NIOS2软核更多的特殊特性和优点　　用户自定义硬件指令高度可配置的DSP处理性能　　软件逻辑硬件化实现的的ICH功能　　与逻辑的高度紧密集合　　所有适合FPGA 调试的工具都能用到NIOS２的调试上来，特别是比如SignalTap™ II Logic Analyzer的使用大大简化调试的难度. For Internal Use Only

Solution: Replace External Devices with Programmable Logic
頁眉一种传统的硬件系统构架 CPU I/O Flash SDRAM I/O FPGA FPGA DSP I/O I/O I/O I/O CPU DSP Why is Nios so attractive? Traditional approach – board level integration using discrete components Solution: Replace External Devices with Programmable Logic

System-On-a-Programmable-Chip (SOPC)
頁眉 System-On-a-Programmable-Chip (SOPC) Flash SDRAM FPGA Why is Nios so attractive? Traditional approach – board level integration using discrete components CPU is a Critical Control Function Required for System-Level Integration

Standard Reference Design Block Diagram
Ethernet MAC/PHY 1MB SRAM 8MB FLASH 16MB Compact FLASH 32MB SDRAM Nios II Processor Tri-State Bridge Tri-State Bridge Compact Flash PIOs SDRAM Controller Address (32) 32-Bit Nios II Processor Read Avaln Switch Fabric Write Level Shifter UART Data In (32) ROM (with Monitor) General Purpose Timer Periodic Timer Data Out (32) Reconfig PIO IRQ LED PIO LCD PIO 7-Segment LED PIO Button PIO IRQ #(6) 8 LEDs Expansion Header J12 2 Digit Display 4 Momentary buttons On-Chip Off-Chip

User-Defined Interface
Typical Nios II System Architecture UART 0 Timer 0 SPI 0 GPIO 0 DMA 0 Memory Interface User-Defined Interface Address Decoder Avalon Master/ Slave Port Interfaces Instr. UART n On-Chip Debug Core Nios II CPU Data Interrupt Controller Timer n Wait State Generation SPI n Data in Multiplexer GPIO n Off-Chip Software Trace Memory Master Arbitration DMA n Clock Domain Crossing Memory Interface Dynamic Bus Sizing User-Defined Interface Avalon Switch Fabric

General Purpose Registers r0 to r31 Control Registers ctl0 to ctl4
Nios II Processor Block Diagram Nios II Processor Core reset Tightly-Coupled Instruction Mem clock Program Controller & Address Generation General Purpose Registers r0 to r31 JTAG interface to Software Debugger Hardware- Assisted Debug Module Instruction Cache Tightly-Coupled Instruction Mem Instruction Bus Exception Controller Control Registers ctl0 to ctl4 Interrupt Controller irq[31..0] Data Bus Data Cache Tightly-Coupled Data Mem Custom Instruction Logic Arithmetic Logic Unit Custom I/O Signals Tightly-Coupled Data Mem

Nios II Processor Architecture
Classic Pipelined RISC Machine 32 General Purpose Registers 3 Instruction Formats 32-Bit Instructions 32-Bit Data Path Separate Instruction and Data Cache (configurable sizes) Tightly-Coupled Memory Options Branch Prediction 32 Prioritized Interrupts On-Chip Hardware (Multiply, Shift, Rotate) Custom Instructions JTAG-Based Hardware Debug Unit

Benefits of Processor Integration
頁眉 Benefits of Processor Integration Unused Logic Existing FPGA Existing FPGA with Nios Core Discrete Processor Increases Design Flexibility Simplifies Inventory Management Portability to Next-Generation FPGAs Now let’s consider the benefits gained by integrating the processor functionality into the FPGA, and look at what integration really means. (By contrast, the previous slides showed how Nios helps you avoid headaches.) First, in many cases the FPGA design has over 1000 LEs left over, meaning that effectively the cost of the Nios processor is free. In general, integration offers the following benefits: Increases Design Flexibility: Bringing the CPU inside the FPGA gives you great flexibility to customize that processor to your exact system needs, and you can tweak your processor features without having to re-spin the board. Simplifies inventory management in two ways: You’re buying one chip instead of two Different flavors of Nios processor can be implemented in any given FPGA, whereas different flavors of discrete micros necessitates tracking multiple ordering codes. 3. Portability to Next-Generation FPGAs means your software investment is Obsolescence-Proof When starting the next generation of your Nios project, you have a software-compatible migration path After you create a Nios processor system, YOU own that system architecture, so YOU control the destiny of your software investment. No-one can obsolete the processor architecture on you. Even if the Altera device goes obsolete, you can create the same system architecture targeting a newer Altera FPGA family. This extends the life of your software investment through multiple generations of your product. Lower Board Costs, Fewer Components, Obsolescence-Proof

Soft Core Advantages Processor? How Many Processors?
頁眉 Soft Core Advantages Low-Cost Embedded Solution Complex Embedded System-on-a-Chip 2,910 Logic Elements Processor? How Many Processors? 179,400 Logic Elements Cyclone Series & Nios II Economy CPU < 20% of Device 20 DMIPs As Low As 35¢ Stratix II EP2S180 & Nios II Fast CPU 1% of Device 220 DMIPs (each)

Data Sharing and Mutual Exclusion
Mailboxes For Inter-Processor (and/or Multi-Threaded) Message Passing Hardware Mutex For Safe Resource Sharing Mailboxes (New in 5.0) Mutex Shared Memory

Scalable Solution Custom I/O Stream Processing Not Available in ASSPs
頁眉 I/O Processing MAC DMA Altera FPGA Packet Buffer APEX 20K Nios MAC DMA User Logic Packet Buffer Nios MAC DMA Packet Buffer Nios MAC DMA The Nios CPU can be used to process and control operations on complex, high-speed IO streams. Two points: The solution is scalable. Use as many Nios processors as you need to handle all your I/O channels. The MAC in this system is probably 10/100/1G Ethernet, but it could be anything. The designer can implement application-specific I/O processing and control that is not available in off-the-shelf ASSPs. Note that the Nios CPU is not in the data path; the CPU simply performs traffic management, directing packets through the system. Packet Buffer Nios Nios Skip… Scalable Solution Custom I/O Stream Processing Not Available in ASSPs Return…

使用NIOS进行系统设计的优势和好处高度的灵活性设计成本的降低大大的节省板上空间降低PCB的布难度更多更灵活的调试方法

Altera advanced design tools
SOPC Altera advanced design tools

SOPC= System-On-a-Programmable-Chip
一个系统化的集成设计环境

SOPC Builder – System Contents Page

使用SOPC设计一款最适合自己的NIOS MCU
Nios II /f Fast Nios II /s Standard Nios II /e Economy Pipeline 6 Stage 5 Stage None H/W Multiplier & Barrel Shifter 1 Cycle 3 Cycle Emulated In Software Branch Prediction Dynamic Static Instruction Cache Configurable Data Cache TCM (Instr / Data) Up to: 4 / 4 Up to: 4 / 0 0 / 0 Logic Usage (Logic Elements) 1200 – 1400 600 – 700 Custom Instructions Up to 256

Nios II: Faster & Smaller
4X Faster Standard 10% Smaller Over 2X Faster Economy 50% Smaller Results Based on Stratix II FPGA

Variation with FPGA Device
Fast Economy Standard Cyclone II

Processor Cost vs. Performance
Stratix II f f Stratix s Cyclone II Cyclone f s f s s e e e e

Nios II: Hard Numbers FMax Numbers Based on Reference Design Running From On-Chip Memory (Nios II/f 1.15 DMIPS / MHz)

外围扩展设备 Altera, Partner & User Cores Altera, Partner & User Cores
Processors Memory Interfaces Peripherals Bridges Hardware Accelerators Import User Logic (ie. custom peripherals) Web-Based IP Deployment Altera, Partner & User Cores Processors Memory Interfaces Peripherals Bridges Hardware Accelerators Import User Logic (ie. custom peripherals) Web-Based IP Deployment Over 60 Cores Available Today Over 60 Cores Available Today

Hardware Multiplier Support
Stratix and Stratix II DSP Blocks Cyclone II Multiplier Blocks Multiplication using 18 x 18 Multiplier Block Optional LE Implementation Enables HW multiplier support for Cyclone Device Family Can also use in Stratix and Stratix II instead of DSP Blocks Mul, Shift, Rotate (~ 8 Clocks Per Mul) Eliminates need for DSP blocks for Nios II MUL

Hardware Multiplier Acceleration
Nios II Economy version - No Multiply Hardware Uses GNUPro Math Library to Implement Multiplier Nios II Standard - Full Hardware Multiplier 32 x 32  32 in 3 Clock Cycles if DSP block present, else uses software only multiplier Nios II Fast - Full Hardware Multiplier 32 x 32  32 in 1 Clock Cycles if DSP block present, else uses software only multiplier Acceleration Hardware Clock Cycles (32 x 32  32) None 250 Standard MUL in Stratix 3 Fast 1

如何实现设计，将定制好的CPU放入FPGA，综合布线．软件程序编写调试

在SOPC环境中定制自己的CPU．产生CPU文件
将定制好的CPU调入quartus 环境，布局布线在NOIS IDE环境中编写调试软件程序（C代码）

Select & Configure Peripherals, IP
SOPC Builder Flow SOPC Builder GUI Processor Library Configure Processor Custom Instructions Peripheral Library Select & Configure Peripherals, IP IP Modules HDL Source Files Testbench Synthesis & Fitter User Design Other IP Blocks Hardware Development Quartus II Software Development Connect Blocks Nios II IDE C Header files Custom Library Peripheral Drivers Generate Altera PLD JTAG, Serial, or Ethernet Executable Code Hardware Configuration File Verification & Debug Compiler, Linker, Debugger User Code Libraries RTOS On-Chip Debug Software Trace Hard Breakpoints SignalTap® II GNU Tools

SOPC Builder - System Contents
Target Board IRQ Priorities Address Map Clock Domains Connection Panel Component

Configure the Nios II CPU
Hardware designer selects Nios II version economy, standard, or fast

Choose JTAG Debug Core Select appropriate JTAG Debug level when configuring Nios II processor core

Select Cache and TCM Settings
Adjust Size of Instruction and Data Cache Memory Can now completely disable data cache on fast core And also disable instruction cache as long as TCM used Enable Instruction / Data Tightly Coupled Memory masters Control Data Cache Width Up to 32 byte cache line width now possible for better burst support

Tightly Coupled Masters
Connected to tightly-coupled slaves through “Tightly Coupled Memory Interfaces” “Slaves” are on-chip true dual port memories They allow “Normal” data master to connect to second port, allowing reading and writing of data Regular Instruction and Data Masters Tightly-Coupled Instruction and Data Masters Nios II CPU Instruction Master TCMs Avalon Switch Fabric Avalon Slave Data Master Avalon Slave Tightly Coupled Data Master Tightly Coupled Instruction Master Slave 32 Slave Tightly Coupled Memory Interface

SOPC Builder Produces a .PTF File
Text file that records SOPC Builder edits Describes Nios II System Used by software development tools

Instantiating Top Module Into HDL Code
top_module (outa, outb, clk, rst, ina,inb,inc, <etc.> ); . // SOPC Builder Instance in Top-Level Code: SOPC_system SOPC_instance_0 ( // 1) global signals: clk, reset_n, // The_button_pio in_port_to_the_button_pio, // The_ext_ram_bus_avalon_slave be_n_to_the_ext_ram, ext_ram_bus_address, ext_ram_bus_byteenablen, ext_ram_bus_data, ext_ram_bus_readn, ior_n_to_the_lan91c111, iow_n_to_the_lan91c111, irq_from_the_lan91c111, read_n_to_the_ext_ram, reset_to_the_lan91c111, select_n_to_the_ext_flash, select_n_to_the_ext_ram, write_n_to_the_ext_flash, write_n_to_the_ext_ram, // The_lcd_display LCD_E_from_the_lcd_display, LCD_RS_from_the_lcd_display, LCD_RW_from_the_lcd_display, LCD_data_to_and_from_the_lcd_display, . // The_led_pio out_port_from_the_led_pio, // The_my_pwm pwm_out_from_the_my_pwm, // The_reconfig_request_pio bidir_port_to_and_from_the_reconfig_request_pio, // The_sdram zs_addr_from_the_sdram, zs_ba_from_the_sdram, zs_cas_n_from_the_sdram, zs_cke_from_the_sdram, zs_cs_n_from_the_sdram, zs_dq_to_and_from_the_sdram, zs_dqm_from_the_sdram, zs_ras_n_from_the_sdram, zs_we_n_from_the_sdram, // The_seven_seg_pio out_port_from_the_seven_seg_pio, // The_uart1 rxd_to_the_uart1,txd_from_the_uart1 ); . １ Note: Look into your SOPC Builder output file (eg. <my_SOPC_system>.v or .vhd file for system module definition)

Integrating Block Symbol into Schematic
Drop in component as shown below Then compile design

Using Quartus II Programmer
Launch from Quartus II after compile to program FPGA <hardware>.sof programming file generated during the Quartus II hardware compile

Some Important Peripherals for Nios II
JTAG UART Single JTAG Connection For: Device Configuration Flash Programming Code Download Debug Target STDIO (printing) Compact Flash Interface Mass Storage Support True IDE Mode Compact Flash Mode Software Supports Low-Level API MicroC/OS-II File System Support µCLinux File System Support Peripheral Now Provided with the Nios II IDE and Supported through the Nios Forum

Some Important Peripherals for Nios II
SSRAM Controller Cypress CY7C1380C Sync SRAM controller Provided to support SSRAM component on Cyclone II dev kit board Not a fully configurable general purpose controller Support for DDR/DDR2 in SOPC Builder GUI With burst adapter Sequential master to interleaved slave enhancement Separate READ/Write duplex slaves Automatically matches address of read/write slaves Arbitration logic connects read/write masters to both slaves Support for PCI and Bursting DMA in SOPC Builder GUI Higher bandwidth transfers through PCI

Nios II Software Development

Nios II IDE (Integrated Development Environment)*
Leading Edge Software Development Tool Target Connections Hardware (JTAG) Instruction Set Simulator ModelSim®-Altera Software Advanced Hardware Debug Features Software and Hardware Break Points, Data Triggers, Trace Flash Memory Programming Support * Based on Eclipse Project

Opening the Nios II IDE Launch the Nios II IDE from the SOPC Builder or from the Windows Start menu

File > switch workspace
Workspace Dialog Box Appears when you first open Nios II IDE Before main tool opens Can now open Multiple Nios II IDE sessions Pick workspace each time Nios II IDE opened Default C:\altera\kits\nios2\bin\eclipse\workspace Each “workspace” has its own settings File > switch workspace

Nios II IDE Welcome Page
Get A Tool Overview Access Tutorials Check Out New Features Open IDE Workbench

Creating a C/C++ Application
File > New > Project

Creating a C/C++ Application
Link to a System Library Select a pre-existing library Or create a new library

Nios II IDE Workbench File Viewer Window
(for C code, C++, and assembly*) List of Open Projects Outline View (view and/or open funcs, enums, classes, unions, structs, typedefs, etc.) Terminal window Note: C++ files must have extension .cpp In-line assembly code offset by asm();

This Creates Two Software Projects - Application and System Library Project
Application Project contains application source code System Library Project contains system header file, etc.

Application and System Library Projects
Application Projects build executables System Library Projects contain interface to the hardware Nios II device drivers (Hardware Abstraction Layer) Optional RTOS (MicroC/OS-II) Optional software components Eg. Lightweight TCP/IP stack, Read Only Zip File System

Adding Source Files to a Project
From within the Nios II IDE Specify Application Project folder and <file_name>.c

Adding Source Files to a Project
Or move source code directly into Application Project Right-Click and Refresh to update project

Moving Files within Windows
Can even add files from outside Nios II IDE Project Right-Click and Refresh to update project

Setting Project Properties
The Application and System Library both have project Properties pages

System Library Project Properties
Specify stdio devices Partition the memory map

Software Compilation Evaluates makefile for compiling application code
To compile a software application, highlight your project and select Build Project from the Projects menu Evaluates makefile for compiling application code

Hardware Abstraction Layer
A lightweight runtime environment for Nios II software Provides a level of abstraction between application code and low level hardware HAL libraries are generated by Nios II IDE HAL contains: device drivers initialization software file system stdio, stderr Device drivers automatically configured to match PTF

HAL References Located in the System Library Project
Each HAL project references library routines and drivers for the components included in your Nios II system Located in the System Library Project

SOPC Builder System Contents System Library Settings
HAL System Header File SOPC Builder System Contents system.h System Library Settings

system.h Hardware configuration of the peripheral Base address
Contains macro definitions for system parameters, including peripheral configuration, for instance: Hardware configuration of the peripheral Base address IRQ priority (if any) Symbolic name for peripheral Does not include: static information, function prototypes, or device structures (unlike the old excalibur.h) Located in the syslib project directory Rarely necessary to include it explicitly in your application code, which improves rebuild time

system.h - example Defines system settings and peripheral configurations: Replaces excalibur.h (from Nios) /* * system configuration * */ #define ALT_SYSTEM_NAME "std_1s10ES" #define ALT_CPU_NAME "cpu" #define ALT_CPU_ARCHITECTURE "altera_nios2" #define ALT_DEVICE_FAMILY "STRATIX" #define ALTERA_NIOS_DEV_BOARD_STRATIX_1S10_ES #define ALT_STDIN "/dev/jtag_uart" #define ALT_STDOUT "/dev/jtag_uart" #define ALT_STDERR "/dev/jtag_uart" #define ALT_CPU_FREQ #define ALT_CPP_CONSTRUCTORS #define ALT_IRQ_BASE NULL . . /* * button_pio configuration * */ #define BUTTON_PIO_NAME "/dev/button_pio" #define BUTTON_PIO_TYPE "altera_avalon_pio" #define BUTTON_PIO_BASE 0x #define BUTTON_PIO_IRQ 2 #define BUTTON_PIO_HAS_TRI 0 #define BUTTON_PIO_HAS_OUT 0 #define BUTTON_PIO_HAS_IN 1 #define BUTTON_PIO_CAPTURE 1 #define BUTTON_PIO_EDGE_TYPE "ANY" #define BUTTON_PIO_IRQ_TYPE "EDGE" #define BUTTON_PIO_FREQ

Reading/Writing Hardware in Nios II
I/O macros used to access hardware I/O macros bypass the cache for hardware accesses They use STxIO or LDxIO instructions IORD(BASE, REGNUM) Reads value at register REGNUM offset from base address BASE IOWR(BASE,REGNUM,DATA) Writes DATA to register REGNUM offset from base address BASE BASE REGNUM = 0 REGNUM = 1 BASE+8 REGNUM = 2 REGNUM = 3 BASE+16 REGNUM = 4

Header Files for Nios II Peripherals
Each Nios II peripheral has specific read/write macros for each register Example: UART (altera_avalon_uart_regs.h) #define IORD_ALTERA_AVALON_UART_RXDATA(base) IORD(base, 0) #define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) IOWR(base, 0, data) #define IORD_ALTERA_AVALON_UART_TXDATA(base) IORD(base, 1) #define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) IOWR(base, 1, data) #define IORD_ALTERA_AVALON_UART_STATUS(base) IORD(base, 2) #define IOWR_ALTERA_AVALON_UART_STATUS(base, data) IOWR(base, 2, data)

Nios II RTOS Support

Nios II Middleware Support

Micrium MicroC/OS-II Real-Time Operating System Scalable, Preemptive
Full Source Code Developer’s License Included Annual Shipper’s License Subscription Available Read-Only ZIPFS File System Lightweight IP Open Source TCP/IP Stack Works with uC/OS-II Note: Stand-alone version available on the Nios Community Forum Small Code Footprint Berkeley Sockets API Protocol Support: IP, ICMP, UDP, TCP

Software Run & Debug

Software Run and Debug Nios II Run Nios II IDE JTAG Debugger
Nios II ISS Nios II Console Third Party tools

Running Code On A Target
Nios II IDE can be used to download code to target board

Running Code On A Target
Download messages, stdout and stdin appear in console window

Nios II IDE Run Options Nios II IDE > Run > Run…

Nios II IDE JTAG Debugger
Requirements Must have JTAG Debug Core enabled in CPU

Nios II IDE Debug Perspective
Basic Debug Run Controls Stack View Active Debug Sessions Double-click to add breakpoints Variables Registers Signals Memory View

Nios II IDE Debugger Step Return Step Over Step Into Re-Run
Program Step with Filters Re-start Debugger Disconnect Terminate Suspend Resume Switch between Debug Configuration And Run Configuration

Nios II IDE Debugger Memory Registers Variables Breakpoints
Standard debug windows Memory Registers Variables Breakpoints Expressions Signals

Built-In Trace Trace is Triggered on any Breakpoint or Watchpoint

Mixed Source / Disassembly View
User Can Now View Interleaved Source and Assembly Window > Show View > Other... > Debug > Disassembly

Nios II IDE - Multi-Processor Launch

Altera and Third Party Debug Choices

Nios II / FS2 Console Command line debugger Investigate embedded hardware with or without software code running on system

Nios II / FS2 Console Launch
FS2 Console Launches then minimizes Note: can also launch from SDK Shell (nios2-console)

Avalon Switch Fabric

User-Defined Interface
Avalon Switch Fabric Proprietary interconnect specification used with Nios II Principal design goals Low resource utilization for bus logic Simplicity Synchronous operation Transfer Types Slave Transfers Master Transfers Streaming Transfers Latency-Aware Transfers Burst Transfers Nios II Processor Switch PIO Address (32) 32-Bit Nios II Processor Read Avalon Switch Fabric Write LED PIO Data In (32) Data Out (32) 7-Segment LED PIO IRQ IRQ #(6) PIO-32 User-Defined Interface ROM (with Monitor) UART Timer

Avalon Switch Fabric Contingencies are on a Per-Peripheral Basis
Custom-Generated for Peripherals Contingencies are on a Per-Peripheral Basis System is Not Burdened by Bus Complexity SOPC Builder Automatically Generates Arbitration Address Decoding Data Path Multiplexing Bus Sizing Wait-State Generation Interrupts

Avalon Master Ports Fundamental Read Fundamental Write Latency
Initiate Transfers with Avalon Switch Fabric Transfer Types Fundamental Read Fundamental Write Transfer Properties Latency Streaming Burst

Avalon Slave Ports Fundamental Read Fundamental Write Wait States
Respond to Transfer Requests from Avalon Switch Fabric Transfer Types Fundamental Read Fundamental Write Transfer Properties Wait States Latency Streaming Burst

Slave Read Transfer 0 Setup Cycles 0 Wait Cycles

Slave Read Transfer with Wait States
1 Setup Cycle 1 Wait Cycle

Slave Write Transfer 0 Setup Cycles 0 Wait Cycles 0 Hold Cycles

Multiple Clock Domains Supported
CDX Avalon Switch Fabric Arbiter Master Clock Domain 1 Clock Domain 2 Slave Master Clock Domain 1 Slave Clock Domain 2 CDX Avalon Switch Fabric Slave Clock Domain 2 CDX = Clock Domain Crossing Logic (inserted automatically by SOPC Builder)

Multi-Clock Domain Support
Master Clock Domain 2 Master Clock Domain 1 Master Clock Domain 1 Master Clock Domain 1 CDX Avalon Switch Fabric Arbiter Avalon Switch Fabric CDX Arbiter Slave Clock Domain 3 Slave Clock Domain 2 CDX = Clock Domain Crossing Logic

如何将外设与Avalon 总线关联

Concentrate Effort on Peripheral Functionality!
Creating Avalon Slave No Need to Worry about Bus Interface Implement Only Signals Needed Peripherals Adapted to by Avalon Switch Fabric Timing Handled Automatically Fabric Created for You Arbiters Generated for You Avalon Switch Fabric Register File User Logic Concentrate Effort on Peripheral Functionality!

Tri-State Peripherals
Will Require Tri-State Bridge Available as an SOPC Builder component Tri-State peripheral is defined by the presence of a bi-direction data port Off Chip Peripheral Avalon Tri-State Bridge Interface to User Logic Nios II Processor FPGA

New Component Editor

1. Create External Component Interface
To communicate with off-chip peripherals Base interface type on data sheet AMD29LV065AD CFI Flash Chip Note: Use avalon tri-state slave interface type if interfacing to an off-chip tri-state bus

2. Interface to HDL File Add HDL File - For peripheral that has been encoded for FPGA

Define Interface for Each Signal Type
Choose Interface Type: Register Slave uses native alignment Memory Slave uses dynamic alignment Control Read and Write Timing Add wait and hold states View waveforms

Address Alignment – Narrow Slave
Avalon 32-Bit Nios II Processor Peripheral Registers Base Base + 0x1 Base + 0x2 Base + 0x3 Base + 0x4 32 aa bb cc dd ee 8 8 Bit Peripheral Dynamic Address Alignment (set as “Memory Slave”) LD from Base + 0x0: dd cc bb aa LD from Base + 0x4: uu uu uu ee Native Address Alignment (set Avalon “Register Slave”) LD from Base + 0x0: uu uu uu aa LD from Base + 0x4: uu uu uu bb LD from Base + 0x8: uu uu uu cc

Address Alignment – Narrow Master
Avalon 32-Bit Nios II Processor 32 Memory Contents Base Base + 0x8 Base + 0x16 ff ee dd cc bb aa ?? ?? ?? ?? ?? ?? ?? ?? 64 64 Bit Memory Dynamic Address Alignment LD from Base + 0x0: LD from Base + 0x4: LD from Base + 0x8: bb aa 99 88 Native Address Alignment LD from Base + 0x4: bb aa 99 88 LD from Base + 0x8: ?? ?? ?? ?? High bytes are unobtainable – warning issued

Eg: Add User-Defined PWM to System
This will be added to our Nios II system in the next Lab HDL for PWM already exists with standard micro-processor type interface Avalon Nios II System

Custom Instructions 頁眉
During this section we are going to discuss adding custom instructions to our Nios system

Custom Instructions To take full advantage of the flexibility of FPGA
頁眉 Custom Instructions Add custom functionality to the Nios II design To take full advantage of the flexibility of FPGA Dramatically Boost Processing Performance With no Increase in fMAX required Application Examples Data Stream Processing (eg. Network Applications) Application Specific Processing (eg. MP3 Audio Decode) Software Inner Loop Optimization

Custom Instructions Augment Nios II Instruction Set
頁眉 Custom Instructions Augment Nios II Instruction Set Mux User Logic Into ALU Path of Processor Pipeline Nios II processor custom instructions are custom logic blocks adjacent to the ALU in the CPU’s data path. This gives system designers the ability to tailor the Nios II processor core to meet the needs of their application. System designers have the ability to accelerate time critical software algorithms by converting them to custom hardware logic blocks. The Custom Instruction featured in NIOS II processor provides system designers with an easy way to do hardware/software tradeoffs during the implementation phase of a design rather than in the specification phase

Several Levels of Customization
頁眉 Several Levels of Customization Optional Interface to FIFO, Memory, Other Logic dataa 32 datab Combinatorial result clk clk_en reset start Multi-Cycle done Internal Register File a 5 b c readra readrb writerc n 8 Extended There are different Custom Instruction architectures available for use to suit the needs of the application. They range from a simple single cycle combinatorial to an extended variable length multi-cycle custom instruction. The architecture chosen changes functionality, the hardware and software interface presented to the custom instruction. -- The original Nios allows up to five custom instructions (usr0 through usr4), each of which optionally supports an 11‑bit prefix, but Nios II has a single custom opcode which has an 8‑bit field called N. (The Nios II custom opcode also has three 5-bit fields that can be used to control the instruction.) Combinatorial Custom Instruction consists of a logic block that is able to complete in a single clock cycle. Because the logic is able to complete in a single clock there is no need for control signals. - Multi-Cycle or sequential Custom Instructions consists of a logic block that requires two or more clocks to complete an operation. Multi-cycle custom instruction can either complete in a fixed or variable number of clock cycles. You can, as such, either specify the number of clock cycles required to finish an instruction, or for variable length custom instructions, the start and done signals are used in a handshaking scheme to determine when the custom instruction execution is complete. Additional control signals are required for multi-cycle custom instructions. Extended Custom Instruction allow for a single custom logic block to output results for different operations. Extended Custom Instructions make use of the N field of the custom op-code to specify which logic operation is performed by the custom logic. The 8-bit wide N field in the op-code and allows for 256 unique custom instructions. Internal Register Access Custom instructions use the a, b, and c bits of the custom op-code to determine if I/O should take place between the NIOS II register file or an internal register file. In the case that I/O should take place with the internal register file, the A, B, and C fields of the custom op-code is used to index the register location in the register file. Currently, we can only access the internal registers using assembly language – we’ll get back to this… Note: NIOS II processor custom instructions allow for designers add their own interface to communicate with logic outside of the processor’s data path. During the custom instruction importing process, any signals that are not recognized as custom instruction signals will propagate out to the top level of the SOPC Builder module where external logic can access the signals.

Custom Instructions Tab
頁眉 Custom Instructions Tab Enabled from the Custom Instructions tab in the Nios II CPU settings in SOPC Builder

Software Interface - C #include "system.h"
頁眉 Software Interface - C NIOS II IDE generates macros automatically during build process Macros defined in system.h file #define ALT_CI_<your instruction_name>(instruction arguments) Example of user C-code that references Bitswap custom instruction: #include "system.h" int main (void) { int a = 0x ; int a_swap = 0; a_swap = ALT_CI_BSWAP(a); return 0; }

Assembly Language Interface
頁眉 Assembly Language Interface Assembler syntax for the custom instruction: custom N, rC, rA, rB Two Examples: custom 0, r6, r7, r8 custom 3, c1, r2, c4 Custom instruction opcode number Destination register for result Operand 1 Operand 2 r = Nios II processor register c = Custom instruction internal register

Why Custom Instruction?
頁眉 Why Custom Instruction? Reduce Complex Sequence of Instructions to One Instruction Example: Floating Point Multiply Typical Flow Profile Code Identify Critical Inner Loop Create Custom Instruction Logic Replace One or All Instructions in Inner Loop Import Custom Instruction Logic into Design Call Custom Instruction from C or Assembly float a, b, result_slow, result_fast; result_slow = a * b; /* Takes 266 clock cycles */ result_fast = ALT_CI_fpmult(a,b); /* Takes 6 clock cycles*/ Significantly Faster!

Verilog and VHDL Templates Available
頁眉 Verilog and VHDL Templates Available C:\altera\kits\nios2_7.2\examples\verilog\custom_instruction_template\ “ “ “ “ \VHDL\ “ …Combinatorial …Extended …Internal_Register_File …Multi-Cycle

Example: Verilog HDL Template
頁眉 Example: Verilog HDL Template // Verilog Custom Instruction Template File for Combinatorial Logic module custominstruction( dataa, // Operand A (always required) datab, // Operand B (optional) result // result (always required) ); // INPUTS input [31:0] dataa; input [31:0] datab; // OUTPUTS output [31:0] result; // Custom instruction logic (note: no external interfaces are allowed in combinatorial logic) endmodule

Multi-Cycle Custom Instructions
頁眉 Multi-Cycle Custom Instructions Port list for Multi-Cycle Custom Instructions Must have all of these ports with exact names

Extended Custom Instructions
頁眉 Extended Custom Instructions Uses n[7..0] port to select an operation to perform.

Register File Custom Instructions
頁眉 Register File Custom Instructions Custom instructions can select inputs from internal registers or dataa, datab ports Custom instructions can write results to an internal register file Custom Logic dataa[31..0] reada a[4..0] result[31..0] writec c[4..0]

頁眉 NIOS2 的程序存储和加载

Nios II 的boot过程要经历两个过程
頁眉 Nios II 的boot过程要经历两个过程 FPGA器件本身的配置过程。FPGA器件在外部配置控制器或自身携带的配置控制器的控制下配置FPGA的内部逻辑。如果内部逻辑中使用了Nios II，则配置完成的FPGA中包含有Nios II软核CPU。 Nios II本身的引导过程。一旦FPGA配置成功后，Nios II 就被逻辑中的复位电路复位，从reset地址开始执行代码。Nios II 的reset地址可以在SOPC builder的“Nios II More‘CPU’setting”页表中设置。

常见的几种加载方式 FPGA 从EPCS串行存储器中加载
几种常见的頁眉常见的几种加载方式从EPCS串行存储器中加载这种boot方式，FPGA的配置数据和Nios II的程序都存放在EPCS器件中。FPGA配置数据放在最前面，程序放在后面，程序可能有多个段，每个段前面都插有一个“程序记录”。一个“程序记录”由2个32位的数据构成，一个是32位的整数，另一个是32位的地址，分别用于表示程序段本身的长度和程序段的运行时地址。这个“程序记录”用于帮助bootloader把各个程序段搬到程序执行时真正的位置。EPCS是串行存贮器，Nios II 不能直接从EPCS中执行程序，它实际上是执行EPCS控制器的片内ROM的代码（即bootloader），把EPCS中程序的搬到RAM中执行 FPGA NIOS程序 FPGA 配置 NIOS EPCS控制器件

頁眉从EPCS中boot 用户必须在SOPC builder中添加一个EPCS控制器，无须给它分配管腿，Quartus II 会自动给它分配到专用管腿上。添完EPCS控制器后，SOPC builder会给它分配一个base address，这个地址是EPCS控制器本身携带的片上ROM在Nios II系统中的基地址，这个ROM存有一小段bootloader代码，用于引导整个过程。所以，必须在SOPC builder的“Nios II More‘CPU’setting”页表中把reset地址设置为这个基地址，使得Nios II 复位后从这个地址开始执行以完成整个引导过程整个boot过程是由nios ide软件加入到用户程序中完成. 实际上,程序也是可以直接在EPCS中运行的,但是速度非常的慢.

从外部CFI并行flash中加BOOT 这种boot方式还可以分为2种情况。
頁眉从外部CFI并行flash中加BOOT 这种boot方式还可以分为2种情况。程序直接在flash中运行。这种情况程序不需要另外的bootloader，Nios II 复位时reset地址（指向flash内部）开始执行程序，程序必须有启动代码用于搬移.rwdata段（因为.rwdata段是可读写的不能存放在flash中），同时如果.RODATA段和.EXCEPTIONS段连接时没有指定在flash中话（比如在RAM中），也会被搬到RAM中，并对.bss段清零，设置栈的指针。这些工作都在Crt0.s中完成。程序在RAM（包括On-chip Ram，SDRAM，SSRAM…泛指一般的RAM）中运行。这种情况需要有一个专门的bootloader，它把存放在flash中的各个程序段搬到程序执行时各个段真正的位置 .

FPGA FPGA EPCS NIOS程序 NIOS NIOS程序 CFI flash NIOS FPGA 配置 JTAG 頁眉 CPLD
or MCU NIOS CFI控制器件 JTAG FPGA EPCS NIOS程序 CFI flash NIOS CFI控制器件

頁眉从并行flash中boot Nios II应用常常把Nios II 程序和FPGA配置数据都存放在flash中。这就需要一个配置控制器来驱动flash输出配置数据完成FPGA的配置。配置控制器可以用一片CPLD来实现,也可以使用一个小CPU来完成。配置完成FPGA后NIOS开始准备加载程序,这时候有两中选择程序的运行方式 A 直接运行FLASH上程序 B 使用bootload程序把flash上程序搬出影射到RAM中运行

頁眉 Bootload 程序的插入整个Bootload 程序的插入的过程在NIOS2 IDE中都是由flash programmer 来自动判断完成的首先,是我们在IDE的GUI界面中分配程序运行的各个空间

頁眉

Under NiosII IDE -> Windows -> Preferences -> NiosII
頁眉当我们完成上述的分配后,再配合在SOPC中已经选定的reset指定位置,通过编译程序生成的.ELF文件里就已经存储了这些映射关系. 空间存储的信息,我们也可以通过生成.objdump文件来了解更多的内容 Under NiosII IDE -> Windows -> Preferences -> NiosII

頁眉

Under NiosII IDE -> tools -> flash programmer
頁眉如何完成程序的烧录工作使用NIOS2 IDE中的 flash programmer来自动完成这一过程 Under NiosII IDE -> tools -> flash programmer

FPGA 衍生的问题如何加密讨论 NIOS程序 NIOS 小加密存储器件 I2C FPGA 配置頁眉 CPLD or MCU
CFI控制器件

FPGA Hardware Design Flow and some solusion
頁眉 FPGA Hardware Design Flow and some solusion

Timing Analysis Gate Level Simulation Test FPGA on PC Board
tclk Timing Analysis - Verify Performance Specifications Were Met - Static Timing Analysis Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology Test FPGA on PC Board - Program & Test Device on Board - Use SignalTap II or Signal Probe for Debugging

SignalTap™ II Logic Analyzer
Up to 270 MHz Multi-Analyzer Support 1,024 Channels 128K Samples 10 Trigger Levels No Probes! Can be used simultaneously with the Nios II IDE debugger and the FS2 console! Capture the state of internal nodes In-system, at full system speeds

SignalTap™ II Logic Analyzer

Brief introduction Future Nios II development kit provides a consistent development platform which works for all Nios II embedded processor systems. A designer using our kit needs only a PC and a JTAG download cable to create a “perfect fit” in terms of processors, peripherals, memory interfaces, performance characteristics and cost. A detailed manual is intended as a tutorial to demonstrate how the Nios II soft-core processor is built and added into the default reference design which comes programmed into the future Cyclone II badge board.

DEMOBOARD’S FEATURE Integrated LCD 、VGA display controllers
Interfaces available for PS2, URAT, VGA, Touch Screen and more, for a user’s design Full programmability of custom logic and peripherals Step-by-step reference manual for the Nios II build and work process JTAG-based debug logic supports hardware breakpoints, data triggers and on- and off-chip trace Can be used ‘as-is’ as a final hardware platform

Future Nios II Development kit
Board Information Common Board Hardware in Kits Common Hardware Configuration: 5 MByte SRAM Two Serial Ports (RS-232) One Daughter Board Nec LCD control board Ps2 interface Touch screen interface 50-MHz Crystal (Socket), External Clock Input DMA channel Nine indication LEDs

Single Video Channel Input System

Multiple Video Channel Input System

頁眉 TARGET Any field need a logic function or the exact microprocessor, need complete with custom instructions and peripherals. Such as Mobile Video Conferencing System, Auto Navigation System, Professional Audio Mixing Console, Connection Module for Magic Media Protocol, Fish Finder, Mobile Radio, Automotive Diagnostic Tool ,etc. 特点合成转矩恒定，微步运行比较平稳需要两路独立PWM支持

Nios & Nios II Developers (Partial List)
頁眉 Nios & Nios II Developers (Partial List) Agilent Alcatel Boeing Bosch Canon Casio Cisco Systems Eastman Kodak EMC Fujitsu General Instrument Hewlett Packard Hitachi IBM Kodak LM Ericsson Lucent Technologies SAS Matsushita Matsushita Communications Motorola Motorola Communications NEC Nintendo Nokia Telecommunications Nortel Philips Research Philips Business Communications Philips Multimedia Rockwell Sanyo Sharp Siemens Siemens Information & Communications Sony Thomson Toshiba Project development with the Nios processor is going on at many of Altera’s biggest customers. At least one division of nearly every major Altera customer has purchased a Nios development kit. Since the initial release of the Nios Development Kit, APEX Edition in June 2000, sales of the Nios Development Kit have been stellar. Altera has shipped over 10,000 kits, breaking any previous record for IP sales and exceeding initial expectations for popularity and demand. Nios enjoys immense popularity among universities as a platform for processor/algorithm research and education. Nios is the de facto configurable processor for university research. Over 13,000 Nios Development Kits Shipped

Cisco 2600 Series Router Cisco 3600 Series Router
頁眉 Siemens WayMAX Base Station Cisco Systems Cisco 2600 Series Router Cisco 3600 Series Router 特点合成转矩恒定，微步运行比较平稳需要两路独立PWM支持

頁眉 Sanyo PLV-Z4 Home Entertainment LCD Projector 45-inch and 55-inch Rear Projection TV 特点合成转矩恒定，微步运行比较平稳需要两路独立PWM支持

Remote Meter Reading For More Details:
Customer: Wireless Reading Systems, Norway Product: Remote Energy Consumption Acquisition Processor System (RECAPS). Reasons for Choosing Nios: Control of Radio Transmitter/OCR Functions Replace FPGA & Standalone Processor with Cyclone at 1/5 Cost Increased Integration Reducing Size Decrease in System Power For More Details:

Streaming Video Interface
Customer: Media Works Technology, USA Product: Video Capture Card Reasons for Choosing Nios: Custom Processor (Exact Fit) Configurable Feature Allows Future Extensions of Wireless Interface Capability to Profile Application to Adjust Hardware & Software Partitions Custom Instruction & Hardware Acceleration Feature For More Details:

Telephony System Maintenance Development Final Product
Customer: Philips, France Product: SOPHO iS3000 series of iSPBX Reasons for Choosing Nios: Allowed Implementation of Field Upgradable ISDN Protocol Handler Reconfiguration Lowered Costs for: Maintenance Development Final Product Improved Performance & Reliability of Video Conference, IP Gateway Services & Computer Telephony Product Features For More Details:

Automotive AV System For More Details:
Customer: Johnson Controls Inc, USA Product: Automotive AV System Reasons for Choosing Nios: “For our new automotive audio video system, we have selected Altera's FPGAs because their performance, quality, & temperature specifications meet our automotive requirements. The flexibility & programmability of Altera's devices combined with its powerful Nios embedded processor provide us with the perfect solution for developing new products” For More Details:

Access Router Became Part of First Prototype For More Details:
Customer: Telena Communications, USA Product: Access Router Reasons for Choosing Nios: Nios Development Board Enabled Early Prototyping of Software Became Part of First Prototype Availability of Software & Hardware to Support LCD Interface Enabled Internal Status to Be Read Efficient On-Chip Interfacing to L2 & L3 Hardware Features of the ATM & Packet Over-SONET Design For More Details:

Industrial Control Terminal
Customer: AltaCom, France Product: Flexible Industrial Control Terminal Reasons for Choosing Nios: Flexibility to Implement Custom Options 240*128 Pixel Graphics Control 40*16 Character Mode Display Up to 512K SRAM 1 M Flash 2 UART, RS232/485 1 SPI 10-BaseT For More Details:

IP Switch Router For More Details: Customer: Marconi
Product: BXR IP & Multiservice Switch Router Reasons for Choosing Nios: Unprecedented Versatility with Stratix FPGAs Performance & Cost Savings 128-bit High-speed Transceiver Logic (HSTL) Bus at 200 MHz. “Our Development Team Determined That Altera FPGAs Were The Only Devices That Could Perform These Tasks, Given That They Combine Significant Embedded Memory With Exceptional Speed” For More Details:

Night Vision Camera Reduced Cost By 20%
Customer: Intevec Inc, USA Product: Night Vision Camera Image Processing & Control Reasons for Choosing Nios: Replace DSP with Cyclone & Nios Reduced Cost By 20% Reduce Power Consumption (1/5 Previous System) Form Factor Reduction of 50% Reduce 5 Separate Boards to One Lower Manufacturing Costs Higher Reliability Rapid Development (4 Months) Field Upgrade Enabled Expanded Roadmap For More Details:

The End

Nios II and SOPC Builder

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Nios II and SOPC Builder

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