1. George Mason University ECE 448 – FPGA and ASIC Design with VHDL High Level Language (HLL) Design Flow Reconfigurable Supercomputers ECE 448 Lecture 21

2. 2ECE 448 – FPGA and ASIC Design with VHDL Main sources Clive „Max” Maxfield, The Design Warrior’s Guide to FPGAs Chapter 11 C/C++ etc.-Based Design Flows Kris Gaj, Reconfigurable Supercomputing – tutorial @ Supercomputing 2005, Seattle Kishore Sastry, Scholarly paper, GMU, 2004 Behoviaral synthesis - Languages and Tools

3. 3ECE 448 – FPGA and ASIC Design with VHDL Behavioral Synthesis

4. 4ECE 448 – FPGA and ASIC Design with VHDL Behavioral Synthesis Algorithm I/O Behavior Target Library Behavioral Synthesis RTL Design Logic Synthesis Gate level Netlist Classic RTL Design Flow

5. 5ECE 448 – FPGA and ASIC Design with VHDL Need for High-Level Design Higher level of abstraction Modeling complex designs Reduce design efforts Fast turnaround time Technology independence Ease of HW/SW partitioning

6. 6ECE 448 – FPGA and ASIC Design with VHDL Advantages of Behavioral Synthesis Easy to model higher level of complexities Smaller in size source compared to RTL code Generates RTL much faster than manual method Multi-cycle functionality Loops Memory Access

7. 7ECE 448 – FPGA and ASIC Design with VHDL High-Level Languages C-Based System level languages Commercial SystemC -- The Open SystemC Initiative Handel C -- Celoxica Ltd. Impulse C -- Impulse Accelerated Technologies Research Streams-C -- Los Alamos National Laboratory SA-C -- Colorado State University, University of California, Riverside, Khoral Research, Inc. SpecC – University of California, Irvine and SpecC Technology Open Consortium

8. 8ECE 448 – FPGA and ASIC Design with VHDL Other High-Level Design Flows Matlab-based AccelChip DSP Synthesis -- AccelChip System Generator for DSP -- Xilinx GUI Data-Flow based Corefire -- Annapolis Microsystems Java-based Commercial Forge -- Xilinx Research JHDL – Brigham Young University

9. 9ECE 448 – FPGA and ASIC Design with VHDL SystemC - Overview C++ class library Provides hardware-oriented constructs System level modeling of Software algorithm Hardware architecture Interfaces between communicating entities System is represented as a set of interfacing processes Cycle based approach Provides stable platform for development of system level tools Supported data types include bit, bit vector, fixed point, standard scalar types Hierarchy is implemented using Module, a class that can be linked to other modules using ports Modules may contain processes and instances of other modules

10. 10ECE 448 – FPGA and ASIC Design with VHDL System C Example: Module SC_MODULE(transmit) { sc_in clock; // input ports sc_in tpackin; sc_in timeout; sc_out tpackout; // output ports sc_inout start_timer; int buffer; void send_data(); int get_data_from_app(); // Constructor SC_METHOD(send_data); sensitive << timeout; sensitive_pos << clock; … buffer = get_data_from_app(); * Examples from SystemC User Manual void transmit::send_data() { if (timeout) { … } … else { … } Timer Transmit Channel Receive Process communication

11. 11ECE 448 – FPGA and ASIC Design with VHDL SystemC -based design-flow alternatives SystemC Auto-RTL Translation Verilog / VHDL RTL RTL Synthesis SystemC Synthesis Gate-level netlist Implementation specific, relatively slow to simulate, relatively difficult to modify Alternative SystemC flows

12. 12ECE 448 – FPGA and ASIC Design with VHDL SystemC Evolution The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

13. 13ECE 448 – FPGA and ASIC Design with VHDL Handel-C Overview High-level language based on ISO/ANSI-C for the implementation of algorithms in hardware Allows software engineers to design hardware without retraining Clean extensions for hardware design including flexible data widths, parallelism and communications Based on Communicating Sequential Process model Independent parallel processes “par” construct to specify parallel computation blocks within a process Well defined timing model Each statement takes a single clock cycle Includes extended operators for bit manipulation, and high-level mathematical macros (including floating point)

14. 14ECE 448 – FPGA and ASIC Design with VHDL Handel-C based Design Flow Handel-C Auto-RTL Translation Verilog / VHDL RTL RTL Synthesis Handel-C Synthesis Gate-level netlist Implementation specific, relatively fast to simulate, relatively difficult to modify The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

15. 15ECE 448 – FPGA and ASIC Design with VHDL Handel-C Example 32 x[n] z -1 G 31 (z) G 1 (z) G 0 (z) void polyphase() { ram int IN_WIDTH pin0_0[2], pin0_1[2], pin0_2[2], pin0_3[2]; ram int IN_WIDTH pin1_0[2], pin1_1[2], pin1_2[2], pin1_3[2]; ram int IN_WIDTH pin2_0[2], pin2_1[2], pin2_2[2], pin2_3[2]; ….. while (1) { par { padd0_0[half] = (pmult0_0[half][15] @ (pmult0_0[half] \\ 7)) + (pmult0_1[half][15] @ (pmult0_1[half] \\ 7)); padd0_1[half] = (pmult0_2[half][15] @ (pmult0_2[half] \\ 7)) + (pmult0_3[half][15] @ (pmult0_3[half] \\ 7)); pmult0_0[half] = 0; pmult0_1[half] = -7 * (pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half]); pmult0_2[half] = 109 * (pin0_2[half][7] @ pin0_2[half][7] @ pin0_2[half][7] @ pin0_2[half][7] @ if (half) { par { output[0] ! (((padd0_0[1][9] @ padd0_0[1]) + (padd0_1[1][9] @ padd0_1[1])) \\ 3);

16. 16ECE 448 – FPGA and ASIC Design with VHDL Pure Untimed C/C++ Design Flow The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

17. 17ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Different Levels of C/C++ Synthesis Abstraction

18. 18ECE 448 – FPGA and ASIC Design with VHDL Mentor Graphics – Catapult C

19. 19ECE 448 – FPGA and ASIC Design with VHDL Catapult C automatically converts un-timed C/C++ descriptions into synthesizable RTL. Mentor Graphics – Catapult C

20. 20ECE 448 – FPGA and ASIC Design with VHDL Reconfigurable Supercomputers

21. 21ECE 448 – FPGA and ASIC Design with VHDL Interface  P memory  P memory... PP PP I/O Interface FPGA memory FPGA memory... FPGA... I/O Microprocessor systemReconfigurable system What is a Reconfigurable Computer?

22. 22ECE 448 – FPGA and ASIC Design with VHDL Most advanced reconfigurable computing machines currently on the market Machine Released SRC 6 from SRC Computers Cray XD1 from from Cray SGI Altix from SGI SRC 7 from SRC Computers, Inc, 2002 2005 2006

23. 23ECE 448 – FPGA and ASIC Design with VHDL Pros and cons of reconfigurable computers + can be programmed using high-level programming languages, such as C, by mathematicians & scientist themselves + facilitates hardware/software co-design + shortens development time, encourages experimentation and complex optimizations + allows sharing costs among users of various applications - high entry cost (~$100,000) - hardware aware programming - limited portability - limited availability of libraries - limited maturity of tools.

24. 24ECE 448 – FPGA and ASIC Design with VHDL Two major high-level language (HLL) programming models SRC 6 & SRC 7 from SRC Computers Cray XD1 from from Cray SGI Altix from SGI SRC MAP C programming model Mitrion-C programming model

25. 25ECE 448 – FPGA and ASIC Design with VHDL SRC Programming Model MicroprocessorFPGA main.c function_1() function_2() ANSI C function_1 function_2 macro_1(a, b, c) macro_2(b, d) macro_2(c, e) macro_3(s, t) macro_1(n, b) macro_4(t, k) FPGA Macro_1 Macro_2 a b c de MAP C (subset of ANSI C) I/O Libraries of macros VHDL macro_1 macro_2 macro_3 macro_4 ……………………….

26. 26ECE 448 – FPGA and ASIC Design with VHDL SRC Compilation Process Object files Application sources Macro sources MAP Compiler  PCompiler Logic synthesis Place & Route Linker.v files.bin files. ngofiles.o files Application executable Configuration bitstreams HDL sources Netlists.c or.f files. vhdor.v files Logic synthesis Place & Route Linker.v files.bin files. ngofiles HDL sources. or.mc or.mf files

27. 27ECE 448 – FPGA and ASIC Design with VHDL Library Development - SRC HLL (C, Fortran) HDL (VHDL, Verilog)  P system FPGA system Application Programmer Library Developer HLL (C, Fortran) HLL (C, Fortran) LLL (ASM) HLL (C, Fortran)

28. 28ECE 448 – FPGA and ASIC Design with VHDL SRC Programming Environment + very easy to learn and use + standard ANSI C + hides implementation details + very well integrated environment + mature - in production use for over 4 years with constant improvements - subset of C - legacy C code requires rewriting - C limitations in describing HW (paralellism, data types) - closed environment, limited portability of code to HW platforms other than SRC

29. 29ECE 448 – FPGA and ASIC Design with VHDL Mitrion-C Programming Model for Cray & SGI MicroprocessorFPGA main.c function_1(in1) start_fpga() ANSI C based on Mitrion API FPGA I/O RAM Application code (platform independent) Mitrion Distributed Processor Architecture (platform dependent) Mitrion Compiler & Configurator application on the distributed processor Input & output Mitrion-C VHDL function_1(in2) start_fpga()

30. 30ECE 448 – FPGA and ASIC Design with VHDL Compiling A Mitrion-C Program Processor Configurator Processor Architecture Mitrion-C Source code Processor HW-Design (VHDL IP Core) FPGA Mitrion Software Development Kit Simulator & Debugger Processor Machine-code Compiler

31. 31ECE 448 – FPGA and ASIC Design with VHDL Mitrion-C high-level parallel programming language + arbitrary sizes of operands e.g., int:24 uint:256 + parallel execution of instructions limited only by data dependencies and limited available area + focus on the area * time space utilization

32. 32ECE 448 – FPGA and ASIC Design with VHDL Mitrion-C Environment for Cray and SGI + easy to learn by high-performance computing (HPC) programmers + small amount of Mitrion-C generates large number of lines of HDL code + suitable for describing classical complex HPC problems + portable application codes - new and yet untested - non-standard, no support for legacy codes - language describes only what happens in a single FPGA - currently, no mechanisms to use HDL macros

33. 33ECE 448 – FPGA and ASIC Design with VHDL Application Development for Reconfigurable Computers

34. 34ECE 448 – FPGA and ASIC Design with VHDL Application Development for Reconfigurable Computers Program Entry Compilation Execution Platform mapping Debugging & Verification

35. 35ECE 448 – FPGA and ASIC Design with VHDL Program Program Entry

36. 36ECE 448 – FPGA and ASIC Design with VHDL Platform Mapping SW/HW Partitioning Software (executed in the microprocessor system) Hardware (executed in the reconfigurable processor system) Program

37. 37ECE 448 – FPGA and ASIC Design with VHDL SW/HW Partitioning & Coding Traditional Approach Specification SW/HW Partitioning SW Coding HW Coding SW Compilation HW Compilation SW ProfilingHW Profiling

38. 38ECE 448 – FPGA and ASIC Design with VHDL SW/HW Partitioning & Coding New Approach Specification SW/HW Coding SW Compilation HW Compilation SW ProfilingHW Profiling SW/HW Partitioning

39. 39ECE 448 – FPGA and ASIC Design with VHDL Platform Mapping FPGA mapping Software Hardware Program FPGA 1 FPGA 2 FPGA 3 FPGA 4

40. 40ECE 448 – FPGA and ASIC Design with VHDL Platform Mapping FPGA-FPGA data transfer & synchronization Software Hardware Program FPGA 1 FPGA 2 FPGA 3 FPGA 4

41. 41ECE 448 – FPGA and ASIC Design with VHDL Platform Mapping Use of Internal and External Memories Software Hardware Program FPGA 1 FPGA 2 FPGA 3 FPGA 4 OCM OCM – On-Chip Memory LM – Local Memory SM – Shared Memory SM LM

42. 42ECE 448 – FPGA and ASIC Design with VHDL Platform Mapping I/O Software Hardware Program FPGA 1FPGA 2 FPGA 3 FPGA 4 SM LM OCM SRC StarBridge

43. 43ECE 448 – FPGA and ASIC Design with VHDL Ideal Program Entry Program Entry Function

44. 44ECE 448 – FPGA and ASIC Design with VHDL Actual Program Entry SW/HW Partitioning Data Transfers & Synchronization Use of Internal and External Memories Sequence of Run-time Reconfigurations Use of FPGA Resources (multipliers, μP cores) Preferred Architectures Program Entry Function FPGA Mapping SW/HW Interface

45. 45ECE 448 – FPGA and ASIC Design with VHDL Not Supported Manual Entry Compiler Automated FPGA-FPGA Partitioning  P-FPGA Partitioning FPGA-FPGA Data Transfer  P-FPGA Data Transfer Computation-Data transfer Overlapping Choosing component version Evolution and the current status of tools.........

46. 46ECE 448 – FPGA and ASIC Design with VHDL Summary Mapping algorithms onto reconfigurable computing systems is a parallel processing problem Languages for reconfigurable computers range from high level C/Java to schematic to hardware description languages Compilers face a daunting task - extract ILP, pipeline loops, unroll, trade-off area/speed Current tool chains have many components unfamiliar to software developers