1. Flip-flops

2. Outline  Edge-Triggered Flip-flops  S-R Flip-flop  D Flip-flop  J-K Flip-flop  T Flip-flop  Asynchronous Inputs

3. Outline  Edge-Triggered Flip-flops  S-R Flip-flop  D Flip-flop  J-K Flip-flop  T Flip-flop  Asynchronous Inputs

4. Edge-Triggered Flip-flops  Flip-flops: synchronous bistable devices  Output changes state at a specified point on a triggering input called the clock.  Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal. Positive edgesNegative edges Clock signal

5. Edge-Triggered Flip-flops  S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the clock input. Positive edge-triggered flip-flops Negative edge-triggered flip-flops

6. Outline  Edge-Triggered Flip-flops  S-R Flip-flop  D Flip-flop  J-K Flip-flop  T Flip-flop  Asynchronous Inputs

7. S-R Flip-flop  S-R flip-flop: on the triggering edge of the clock pulse,  S=HIGH (and R=LOW)  SET state  R=HIGH (and S=LOW)  RESET state  both inputs LOW  no change  both inputs HIGH  invalid  Characteristic table of positive edge-triggered S-R flip-flop: X = irrelevant (“don’t care”)  = clock transition LOW to HIGH

8. S-R Flip-flop  It comprises of 3 parts:  a basic NAND latch  a pulse-steering circuit  a pulse transition detector (or edge detector) circuit  The pulse transition detector detects a rising (or falling) edge and produces a very short-duration spike.

9. S-R Flip-flop The pulse transition detector. S Q Q' CLK Pulse transition detector R Positive-going transition (rising edge) CLK CLK' CLK* CLK' CLK CLK* Negative-going transition (falling edge) CLK' CLK CLK* CLK CLK' CLK*

10. Outline  Edge-Triggered Flip-flops  S-R Flip-flop  D Flip-flop  J-K Flip-flop  T Flip-flop  Asynchronous Inputs

11. D Flip-flop  D flip-flop: single input D (data)  D=HIGH  SET state  D=LOW  RESET state  Q follows D at the clock edge.  Convert S-R flip-flop into a D flip-flop: add an inverter. A positive edge-triggered D flip-flop formed with an S-R flip-flop. S RS R Q Q' CLK D  = clock transition LOW to HIGH

12. D Flip-flop  Application: Parallel data transfer. To transfer logic-circuit outputs X, Y, Z to flip-flops Q 1, Q 2 and Q 3 for storage.

13. Outline  Edge-Triggered Flip-flops  S-R Flip-flop  D Flip-flop  J-K Flip-flop  T Flip-flop  Asynchronous Inputs

14. J-K Flip-flop  J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.  No invalid state.  Include a toggle state.  J=HIGH (and K=LOW)  SET state  K=HIGH (and J=LOW)  RESET state  both inputs LOW  no change  both inputs HIGH  toggle

15. J-K Flip-flop  J-K flip-flop  Characteristic table. J Q Q' CLK Pulse transition detector K Q(t+1) = J.Q' + K'.Q

16. Outline  Edge-Triggered Flip-flops  S-R Flip-flop  D Flip-flop  J-K Flip-flop  T Flip-flop  Asynchronous Inputs

17. T Flip-flop  T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together.  Characteristic table. Q(t+1) = T.Q' + T'.Q T Q Q' CLK Pulse transition detector

18. T Flip-flop  Application: Frequency division  Application: Counter (to be covered )

19. Outline  Edge-Triggered Flip-flops  S-R Flip-flop  D Flip-flop  J-K Flip-flop  T Flip-flop  Asynchronous Inputs

20. Asynchronous Inputs  S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred to the flip-flop’s output only on the triggered edge of the clock pulse.  Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)]  When PRE=HIGH, Q is immediately set to HIGH.  When CLR=HIGH, Q is immediately cleared to LOW.  Flip-flop in normal operation mode when both PRE and CLR are LOW.

21. Asynchronous Inputs  A J-K flip-flop with active-LOW preset and clear inputs.