1. Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department Digital Logic Design ESGD2201 Sunday, 14 th December 2008 Lecture 17 Flip Flops and Related Devices

2. 1.Latches. 2.Edge-Triggered Flip-Flops. 3.Flip-Flop Operating Characteristics. 4.Flip-Flop Applications. 5.One-Shots. 6.The 555 Timer. Agenda Flip Flops and Related Devices

3. Flip Flops and Related Devices. The Gated D Latch  Another type of gated latch is called the D latch.  It differs from the S-R latch because it has only one input in addition to EN.  This input is called the D (data) input. Figure 1 contains a logic diagram and logic symbol of a D latch.  When the D input is HIGH and the EN input is HIGH, the latch will set.  When the D input is LOW and EN is HIGH, the latch will reset.  Stated another way, the output Q follows the input D when EN is HIGH.

4. Flip Flops and Related Devices. The Gated D Latch A gated D latch. FIGURE 1, D latch

5. Flip Flops and Related Devices. The Gated D Latch The Truth Table for gated D latch. Table 1, D latch Truth Table.

6. Flip Flops and Related Devices. Example 1: The Gated D Latch Determine the Q output waveform if the inputs shown in Figure 2,a. are applied to a gated D latch. which is initially RESET.

7. Flip Flops and Related Devices. Solution: The Gated D Latch The Q waveform is shown in Figure 2 (b). When D is HIGH and EN is HIGH. Q goes HIGH. When D is LOW and EN is HIGH, Q goes LOW. When EN is LOW, the state of the latch is not affected by the D input.

8. Flip Flops and Related Devices. 2- Edge-Triggered Flip-Flops.  Flip-flops are synchronous bistable devices, also known as bistable multivibrators.  In this case, the term synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK), which is designated as a control input C, that is changes in the output occur in synchronization with the clock.

9. Flip Flops and Related Devices.  An edge-triggered flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock.  There are three types of edge-triggered flip-flops are covered in this section: 1-S-R, 2-D, 3-J-K. 2- Edge-Triggered Flip-Flops.

10. Flip Flops and Related Devices.  Although the S-R flip-flop is not available in IC form, it is the basis for the D and J-K flip-flops.  The logic symbols for all of these flip-flops are shown in Figure 2.  Notice that each type can be either positive edge triggered (no bubble at C input) or negative edge triggered (bubble at C input).  The key to identifying an edge triggered flip-flop by its logic symbol is the small triangle inside the block at the clock (C) input.  This triangle is called the dynamic input indicator: 2- Edge-Triggered Flip-Flops.

11. Flip Flops and Related Devices. 2- Edge-Triggered Flip-Flops. Fig. 2, Edge-Triggered Flip-Flops Logic symbol

12. Flip Flops and Related Devices. 1. The Edge-Triggered S-R Flip-Flop:  The S and R inputs of the S-R flip-flop are called synchronous inputs because data on these inputs are transferred to the flip-flop's output only on the triggering edge of the clock pulse.  When S is HIGH and R is LOW, the Q output goes HIGH on the triggering edge of the clock pulse, and the flip-flop is SET.  When S is LOW and R is HIGH, the Q output goes LOW on the triggering edge of the clock pulse, and the flip-flop is RESET.  When both S and R are LOW, the output does not change from its Prior state.  An invalid condition exists when both S and R are HIGH.

13. Flip Flops and Related Devices. 1. The Edge-Triggered S-R Flip-Flop: FIGURE 3, Operation of a positive edge-triggered S-R flip-flop.

14. Flip Flops and Related Devices. TABLE 2. Truth table for a positive edge triggered S-R flip-flop. 1. The Edge-Triggered S-R Flip-Flop: The Truth Table for S-R Flip-Flop.

15. Flip Flops and Related Devices. Example 1: 1. The Edge-Triggered S-R Flip-Flop: Determine the Q and output waveforms of the flip-flop in figure 4, for the S, R and CLK inputs. Assume that the positive edge triggered flip-flop is initially RESET.

16. Flip Flops and Related Devices. Solution: FIGURE 4.

17. Flip Flops and Related Devices. 2.The Edge-Triggered D Flip-Flop  The D flip-flop is useful when a single data bit (1 or 0) is to be stored.  The addition of an inverter to an S-R flip-flop creates a basic D flip-flop, as in Figure 5, where a positive edge- triggered type is shown. FIGURE 5, A positive edge triggered D flip-flop formed with an S-R flip-flop and an inverter.

18. Flip Flops and Related Devices. 2.The Edge-Triggered D Flip-Flop TABLE 3. Truth table for a positive edge triggered D flip-flop. The Truth Table for D Flip-Flop.

19. Flip Flops and Related Devices. Example 1: 2.The Edge-Triggered D Flip-Flop Given the waveforms in Figure 6 (a) for the D input and the clock. determine the Q output waveform if the flip-flop starts out RESET.

20. Flip Flops and Related Devices. Solution: FIGURE 6.

21. Flip Flops and Related Devices. 3.The Edge-Triggered J-K Flip-Flop  The J-K flip-flop is versatile and is a widely used type of flip-flop.  The functioning of the J-K flip- flop is identical to that of the S-R flip-flop in the SET RESET, and no-change conditions of operation.  The difference is that the J-K flip-flop has no invalid state as does the S-R flip-flop. FIGURE 7.The Edge-Triggered J-K Flip-Flop

22. Flip Flops and Related Devices. 2.The Edge-Triggered J-K Flip-Flop The Truth Table for J-K Flip-Flop. TABLE 4. Truth table for a positive edge triggered J-K flip-flop.

23. Flip Flops and Related Devices. 3.The Edge-Triggered J-K Flip-Flop Example 1: The waveforms in Figure 8 (a) are applied to the J, K, and clock inputs as indicated. Determine the Q output, assuming that the flip-flop is initially RESET.

24. Flip Flops and Related Devices. FIGURE 8. Solution: