1. Embedded Hardware Foundation

2. Content
CPU
Bus
Memory
I/O
Design, develop and debug

3. 1. CPU I/O programming Supervisor mode, exceptions, traps Co-processor
Busy/wait
Interrupt-driven
Supervisor mode, exceptions, traps
Co-processor
Memory System
Cache
Memory management
Performance and power consumption

4. I/O devices Usually includes some non-digital component.
Typical digital interface to CPU:
status
reg
CPU
mechanism
data
reg

5. Application: 8251 UART
Universal asynchronous receiver transmitter (UART) : provides serial communication.
8251 functions are integrated into standard PC interface chip.
Allows many communication parameters to be programmed.

6. 8251 CPU interface status (8 bit) 8251 CPU xmit/ rcv data serial
port

7. Programming I/O Two types of instructions can support I/O:
special-purpose I/O instructions;
memory-mapped load/store instructions.
Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O.
I/O instructions do not preclude memory-mapped I/O.

8. ARM memory-mapped I/O Define location for device: DEV1 EQU 0x1000
Read/write code:
LDR r1,#DEV1 ;set up device address
LDR r0,[r1] ;read DEV1
LDR r0,#8 ;set up value to write
STR r0,[r1] ;write value to device

9. peek and poke (Using C) int peek(char *location) { return *location; }
void poke(char *location, char newval) {
(*location) = newval;

10. Busy/wait output Simplest way to program device.
Use instructions to test when device is ready.
char *mystring="hello, world.";
char *current_char;
current_char = mystring;
while (*current_char != ‘\0’) {
while (peek(OUT_STATUS) != 0);
poke(OUT_CHAR,*current_char);
current_char++; }

11. Simultaneous busy/wait input and output
while (TRUE) {
/* read */
while (peek(IN_STATUS) != 0);
achar = (char)peek(IN_DATA);
/* write */
while (peek(OUT_STATUS) != 0);
poke(OUT_DATA,achar); }

12. Interrupt I/O Busy/wait is very inefficient.
CPU can’t do other work while testing device.
Hard to do simultaneous I/O.
Interrupts allow a device to change the flow of control in the CPU.
Causes subroutine call to handle device.

13. Interrupt interface intr request status reg CPU mechanism intr ack IRPC
data/address
data
reg

14. Interrupt behavior Based on subroutine call mechanism.
Interrupt forces next instruction to be a subroutine call to a predetermined location.
Return address is saved to resume executing foreground program.

15. Interrupt physical interface
CPU and device are connected by CPU bus.
CPU and device handshake:
device asserts interrupt request;
CPU asserts interrupt acknowledge when it can handle the interrupt.

16. Example: interrupt-driven input and output
void input_handler();
void output_handler();
main() {
while (TRUE) {
if (gotchar) {
while (peek(OUT_STATUS) != 0);
poke(OUT_DATA,achar);
gotchar = FALSE; }

17. Example: character I/O handlers
void input_handler() {
achar = peek(IN_DATA);
gotchar = TRUE;
poke(IN_STATUS,0); }
void output_handler()

18. Example: interrupt I/O with buffers
Queue for characters:
head
tail a
head
tail

19. Buffer-based input handler
void input_handler() {
char achar;
if (full_buffer())
error = 1;
else {
achar = peek(IN_DATA);
add_char(achar); }
if (nchars == 1) {
poke(OUT_DATA,remove_char();
poke(OUT_STATUS,1); }

20. Buffer-based output handler
void output_handler() {
if (!empty_buffer()) {
poke(OUT_DATA, remove_char());
/* send character */
poke(OUT_STATUS, 1);
/*turn device on */ }

21. Priorities and vectors
Two mechanisms allow us to make interrupts more specific:
Priorities determine what interrupt gets CPU first.
Vectors determine what code is called for each type of interrupt.
Mechanisms are orthogonal: most CPUs provide both.

22. Prioritized interrupts
device 1
device 2
device n
interrupt
acknowledge
L1 L2 .. Ln
CPU

23. Interrupt prioritization
Masking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete.
Non-maskable interrupt (NMI): highest-priority, never masked.
Often used for power-down.

24. Interrupt vectors
Allow different devices to be handled by different code.
Interrupt vector table:
Interrupt
vector
table head
handler 0
handler 1
handler 2
handler 3

25. Interrupt vector acquisition
device
interruput
request
interruput
ack.
vector
CPU

26. Interrupt vector acquisition
:CPU
:device
receive
request
receive
ack
receive
vector

27. Interrupt sequence
CPU checks pending interrupt requests and acknowledges the one of highest priority.
Device receives acknowledgement and sends vector.
CPU locates the handler using vector as index of interrupt table and calls the handler.
Software processes request.
CPU restores state to foreground program.

28. Sources of interrupt overhead
Handler execution time.
Interrupt mechanism overhead.
Register save/restore.
Pipeline-related penalties.
Cache-related penalties.

29. ARM interrupts ARM7 supports two types of interrupts:
Fast interrupt requests (FIQs).
Interrupt requests (IRQs).
Interrupt table starts at location 0.

30. ARM interrupt procedure
CPU actions:
Save PC. Copy CPSR to SPSR.
Force bits in CPSR to record interrupt.
Force PC to vector.
Handler responsibilities:
Restore proper PC.
Restore CPSR from SPSR.
Clear interrupt disable flags.

31. Exception and Trap Exception: Trap (software interrupt)
internally detected error.
Exceptions are synchronous with instructions but unpredictable.
Build exception mechanism on top of interrupt mechanism.
Exceptions are usually prioritized and vectorized.
Trap (software interrupt)
an exception generated by an instruction.
Call supervisor mode.

32. Supervisor mode
May want to provide protective barriers between programs.
Avoid memory corruption.
Need supervisor mode to manage the various programs.

33. ARM CPU modes 处理器模式 描述 用户模式(User, usr) 正常程序执行的模式 快速中断模式(FIQ, fiq)
用于高速数据传输和通道处理
外部中断模式(IRQ, irq)
用于通常的中断处理
管理模式(Supervisor, svc)
供操作系统使用的一种保护模式
数据访问中止模式
(Abort, abt)
用于虚拟存储及存储保护
未定义指令中止模式
(Undefined, und)
用于支持通过软件仿真硬件的协处理器
系统模式
用于运行特权级的操作系统任务
异常模式

34. ARM CPU modes (cont’d) SWI (Software interrupt)指令 格式
SWI{<条件码>} immed_24
SWI指令用来执行系统调用，处理器进入管理模式， CPSR保存到管理模式的SPSR中，并从地址0x08开始执行指令。<immed_24>由系统所解释。

35. Co-processor
Co-processor: added function unit that is called by instruction.
Floating-point units are often structured as co-processors.
ARM allows up to 16 designer-selected co-processors.
Floating-point co-processor uses units 1 and 2.

36. Memory System
Cache
Memory Management Unit

37. Cache Small amount of fast memory
Sits between normal main memory and CPU
May be located on CPU chip or module

38. Cache operation - overview
CPU requests contents of memory location
Check cache for this data
If present, get from cache (fast)
If not present, read required block from main memory to cache
Then deliver from cache to CPU
Cache includes tags to identify which block of main memory is in each cache slot

39. Cache operation
Many main memory locations are mapped onto one cache entry.
May have caches for:
instructions;
data;
data + instructions (unified).
Memory access time is no longer deterministic.

40. Cache organizations
Direct-mapped: each memory location maps onto exactly one cache entry.
Fully-associative: any memory location can be stored anywhere in the cache (almost never implemented).
N-way set-associative: each memory location can go into one of n sets.

42. Example Cache of 64kByte 16MBytes main memory Cache block of 4 bytes
i.e. cache is 16k (214) lines of 4 bytes
16MBytes main memory
24 bit address (224=16M)
222 blocks; 28 blocks will be mapped into one cache line on the average

43. Direct-mapped cache
Each block of main memory maps to only one cache line
i.e. if a block is in cache, it must be in one specific place
Address is in two parts
Least Significant w bits identify unique word
Most Significant s bits specify one memory block
The MSBs are split into a cache line field r and a tag of s-r (most significant)

44. Direct Mapping Address Structure
Tag s-r
Line or Slot r
Word w 14 2 8
24 bit address
2 bit word identifier (4 byte block)
22 bit block identifier
8 bit tag (=22-14)
14 bit slot or line
No two blocks in the same line have the same Tag field
Check contents of cache by finding line and checking Tag

45. Direct-mapped cache valid tag data 1 0xabcd byte byte byte ... byte
cache block
tag
index
offset =
hit
value

46. Fully-associative cache
Set-associative cache

47. Write operations Write-through: immediately copy write to main memory.
Write-back: write to main memory only when location is removed from cache.

48. Memory management units
Memory management unit (MMU) translates addresses:
main
memory
logical
address
memory
management
unit
physical
address
CPU

49. Memory management tasks
Allows programs to move in physical memory during execution.
Allows virtual memory:
memory images kept in secondary storage;
images returned to main memory on demand during execution.
Page fault: request for location not resident in memory.

50. Address translation
Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses.
Two basic schemes:
segmented;
paged.
Segmentation and paging can be combined (x86).

51. Segments and pages
memory
page 1
segment 1
page 2
segment 2

52. Segment address translation
segment base address
logical address +
segment lower bound
range
error
range
check
segment upper bound
physical address

53. Page address translation
offset
page i base
concatenate
page
offset

54. Page table organizations
descriptor
page descriptor
flat
tree

55. Caching address translations
Large translation tables require main memory access.
TLB: cache for address translation.
Typically small.

56. ARM memory management Memory region types:
section: 1 Mbyte block;
large page: 64 kbytes;
small page: 4 kbytes.
An address is marked as section-mapped or page-mapped.
Two-level translation scheme.

57. CPU performance and power consumption

58. Example: Intel XScale core
MAC is in CP0 coprocessor

59. 2. Bus 总线：CPU与存储器和设备通信的机制 四周期握手协议 总线主控器 一组组相关的电线 部件间通信的协议
启动总线传输的设备，如CPU，DMA控制器

60. 一个基本的总线连接

61. DMA DMA: Direct Memory Access
允许读写不由CPU控制的总线操作。DMA传输由DMA控制器控制，它从CPU请求总线控制。得到控制权后，DMA控制器直接在设备和内存之间执行读写操作。

62. 带DMA控制器的总线连接
附加的总线信号
总线请求
总线授权

63. 桥
高速总线和低速总线
总线互连
高速总线提供更宽的数据连接
低速设备降低成本
桥允许总线独立操作。在I/O中提供某些并行性

64. ARM总线-AMBA AMBA: Advanced Microcontroller Bus Architecture
AHB(AMBA High-performance Bus)
ASB(AMBA System Bus)
APB(AMBA Peripheral Bus)

65. 典型的基于AMBA的系统 一个典型的基于AMBA的微控制器将使用AHB或ASB总线，再加上APB总线。
ASB总线是旧版的系统总线；而AHB较晚推出，以增强对更高性能、综合及时序验证的支持

66. 3. Memory RAM ROM SRAM DRAM PROM，EPROM，EEPROM Flash ROM
Flash在嵌入式系统中的两种作用(boot ROM、hard disk)

67. 4. I/O Watchdog timer A/D & D/A Converter LCD LED Touch screen
Key board
USB ……

68. Watchdog timer 看门狗定时器是一个用来引导嵌入式微处理器脱离死锁状态的部件。是嵌入式系统中的特色部件。
在一个较好的系统中，软件将定时监视或重置看门狗定时器。如果软件和设备工作正常，看门狗定时器得到定期重置。当软件和设备无效工作时，看门狗定时器得不到重置，这样它将持续计数，直到溢出，产生中断使CPU复位。

69. Watchdog timer Watchdog timer is periodically reset by system timer.
If watchdog is not reset, it generates an interrupt to reset the host.
host CPU
interrupt
watchdog
timer
reset