1. P. Fischer, TI, Uni Mannheim, Seite 1CBM Collaboration Meeting, GSI, 11.2.2005 (FEE Session): CAM CAM Design in UMC0.18µm A CAM is required for address translation in various applications (see Ulrichs talk) Block diagram: write address tag, part1 Parity match miss match tag, part2 match

2. P. Fischer, TI, Uni Mannheim, Seite 2CBM Collaboration Meeting, GSI, 11.2.2005 (FEE Session): CAM Some Specs / Features Support up to 512 entries (rows) Operation at 500 MHz Basic unit has 16 bit word + checksum The match circuitry in one row can be powered off no more current during compare Pipelined operation for comparison of larger words is foreseen. Rows with mismatch in early comparisons are switched off in later stages to save power Possibility to disable defective rows Support two types of CAM cells: - binary (store 0/1) - ternary (store 0/1/dont care)

3. P. Fischer, TI, Uni Mannheim, Seite 3CBM Collaboration Meeting, GSI, 11.2.2005 (FEE Session): CAM Binary CAM cell Classical SRAM cell (reading is necessary only for monitoring less constraints for transistors) Comparison with wide wired – OR (bit mismatch pulls match line low) Rows can be disabled by setting power down to high. Cells draw no more current @ compare. Cell size is 5.91 µm x 2.69 µm match (precharged) power down compare write writebitwritbitb compareb

4. P. Fischer, TI, Uni Mannheim, Seite 4CBM Collaboration Meeting, GSI, 11.2.2005 (FEE Session): CAM Ternary CAM Cell match power down write Save ~20% of area by optimized design: -store 1/0 for a 1 -store 0/1 for a 0 -store 0/0 for dont care (cell does not participate in match calculation) Cell size is 10.82 µm x 2.69 µm

5. P. Fischer, TI, Uni Mannheim, Seite 5CBM Collaboration Meeting, GSI, 11.2.2005 (FEE Session): CAM Status & Plans Layouts of crucial (dense) blocks is done: CAM cells, Flipflops, row decoder (F. Giesens Diploma Thesis) Most simulations (typical parameters) are done. Speed is >500MHz for a CAM with 512 rows (parasitics of busses included) We plan to submit an 512 x 18 bit block (testing maximum speed needs full size!). Layout area of this core will be 0.3mm x 1.4mm Testing will be done by setting all input bits & reading all output bits with shift registers. Timing will be generated by several external fast strobe signals. This stuff will be synthesized (with help from Rechnerarchitektur) We are confident to be ready until April 24. : missing : done