1. Experimental results obtained from a 1.6 GHz CMOS Quadrature Output PLL with on-chip DC-DC Converter Owen Casha Department of Micro & Nanoelectronics University of Malta Co-authors: Ivan Grech, Edward Gatt, Joseph Micallef 17 th IEEE International Conference on Electronics, Circuits, and Systems ICECS 2010

2. 2 Overview  Introduction  Quadrature PLL Architecture  Linear Regulated DC-DC Converter  Chip Layout Design Considerations  Chip Measurements / Characterisation  Conclusions  Acknowledgements

3. 3 Introduction  The compliance of RF circuits with the emerging communication standards depends a lot on how the local oscillator performs in terms of phase noise, power consumption, tuning range and adaptivity to the transmission environment.  An on-chip DC-DC converter is not commonly used in a RFIC due to the possibility of interference with the RF function.  Nonetheless in this work, an on-chip DC-DC converter is employed to permit the use of low sensitivity varactors in conjunction with a switched capacitor bank to achieve the required tuning range.  Measured results – confirm that a proper regulatory scheme for the DC-DC converter limits the output voltage ripple.  Automatic Amplitude Control – VCO Adaptivity (Phase Noise versus Power Consumption)

4. 4 Quadrature PLL Architecture 1.6 GHz QPLL Chip 2 mm x 2 mm ST 130 nm HCMOS9-RF Prototype testing board designed for the QPLL chip

5. 5 Linear Regulated DC-DC Converter Ensures stability Derivative Feedback Level shifting Proportional Controller Switched Capacitor Converter 100 MHz 200 MHz ripple frequency

6. 6 Chip Layout Design Considerations  The design of the QO-VCO, PFD, charge pump and prescalar was carried out with a high degree of symmetry, where the interconnections were kept as short as possible and utilised mostly top metal layers which have a low associated sheet resistance and capacitance.  The DC-to-DC converter was placed as far as possible from the QO-VCO to limit the interference between the two circuits through the substrate. The DC-to-DC converter was surrounded with a wide guard ring to limit the radiation generated by this switching circuit.  Differential inductors were used to maintain the symmetry of the QO-VCO. The inductors were placed at a distance of about 100 μm apart from each other to reduce magnetic coupling between them which affects the quadrature lock of the oscillator. Layout of the 1.6 GHz QPLL Chip 2 mm x 2 mm ST 130 nm HCMOS9-RF

7. 7 QO-VCO Measurements (I) The QO-VCO can be continuously tuned from 1.18 GHz to 1.75 GHz, thus a tuning range of 570 MHz (38%) is available. The different curves refer to the different tuning band settings obtained by switchable capacitors.

8. 8 QO-VCO Measurements (II) IMR Measurement for QO-VCO at 1.6 GHz Measured QO-VCO buffered output signals at 1.58 GHz Quadrature Phase Error 3.56° Amplitude Mismatch 5.28%

9. 9 Phase Noise Response (I) Variation of the QO-VCO phase noise across tuning range

10. 10 Phase Noise Response (II) Phase noise response of the ( ○ ) open loop QO-VCO and the (●) quadrature PLL at operated at 1.6 GHz.

11. 11 QO-VCO Automatic Amplitude Control Variation of the phase noise response at an offset of 1 MHz with AAC reference voltage Variation of the oscillation frequency (●) and K vf ( ○ ) with AAC reference voltage

12. 12 QO-VCO Performance Summary Measurement QO-VCO Tuning Range 570 MHz 38% Phase Noise @ an offset of 1 MHz from carrier across whole tuning range < ‒ 115 dBc/Hz QO-VCO Power Consumption (including AAC circuitry and buffers) 20.4 mW @ 1.6 GHz Vtune = 0.75 V B 2 B 1 B 0 = “001” IMR ‒ 28 dB @ 1.58 GHz Quadrature Phase Imbalance 3.56º Amplitude Imbalance5.28% Variation of the QO-VCO current demand (including buffers and AAC circuitry) with the AAC reference voltage. The higher the AAC reference voltage the lower the VCO oscillation amplitude.

13. 13 DC-DC Converter  The on-chip DC-DC converter provides a constant 2.5 V output voltage: Full Load Efficiency of 53%. 2 mV output ripple voltage up to a load current of 200 μA. Consumes only 4.6% of the total PLL power demand at the optimum phase noise response. The regulatory scheme aids in reducing the degradation of the PLL spurious tone level due to the DC-DC converter.

14. 14 Effect of DC-DC Converter on Spur Tone Level Frequency synthesizer output spectrum with on-chip DC-DC converter, PFD and CP switched off, QO-VCO in open loop mode and reference clock oscillator disabled.

15. 15 Effect of DC-DC Converter on Spur Tone Level Frequency synthesizer output spectra with: (a) off chip 2.5 V linear voltage regulator and (b) on chip DC-DC converter supplying the CP and PFD (a) (b) Results confirm the negligible effect of the DC-DC converter on the spur tone level of the QPLL

16. 16 Effect of DC-DC Converter on Spur Tone Level Frequency synthesizer output spectrum with on-chip DC-DC converter, PFD and CP switched off, QO-VCO in open loop mode and reference clock oscillator switched on This test indicates that the spur at 100 MHz is possibly arising due to the chip substrate and testing board electromagnetic coupling and not due to CP injection.

17. 17 Conclusions  This paper presented the measured results and characterisation of a 1.6 GHz low voltage CMOS quadrature output PLL chip designed for a GPS tuner application.  Measurement results show that it exhibits a phase noise of less than ­115 dBc/Hz at an offset of 1 MHz from carrier and has a tuning range of 570 MHz.  Negligible effect of the on-chip linear regulated DC-DC converter on the spurious tone level of the PLL, included in order to provide a high tuning voltage swing whilst using low sensitivity MOS varactors.

18. 18 Acknowledgements  The work presented in this paper has been supported by the Telecommunication Peripherals and Automotive Groups at STMicroelectronics, Catania, Italy.  Special thanks go to Mr. Mario Paparo Mr. Salvatore Cantella

19. 19 Thank you for your attention Any Questions?

20. 20 Switched Capacitor Voltage Tripler Two identical switched capacitor converters combined in parallel and operated with complementary reference clock signals via a dead band generator. Effective output frequency is 200 MHz – low voltage ripple and facilitated filtering.