1. TRAPPISTE Tracking Particles for Physics Instrumentation in SOI Technology Prof. Eduardo Cortina, Lawrence Soung Yee Institut de recherche en mathématique et physique Center for Cosmology, Particle Physics and Phenomenology 10 November, 2011SCK-CEN Meeting1

2. Hybrid vs. Monolithic Detectors 10 November, 2011SCK-CEN Meeting2 -Integration problems -Production yield -Fragility -Sensor and electronics isolation -“Non standard” process

3. Monolithic Detector in SOI Technology Active layer: ~50nm Contains readout electronics Buried Oxide (BOX): ~200nm Insulates circuit from detector Handle wafer: ~300µm Contains the detector. The backside metal is biased to deplete the detector. p+n+ + + + - - - 10 November, 2011SCK-CEN Meeting3

4. TRAPPISTE-1 2μm Fully Depleted SOI CMOS at WINFAB at UCL Shift register to control readout column by column. 3cm 8x8 matrix of 300μmx300μm pixel cells with 3 transistor readout. 10 November, 2011SCK-CEN Meeting4

5. TRAPPISTE-2 2.5mm Transistor test area 7 column source tied transistors. Transistor test area 7 column source tied transistors. CSA test area Amplifiers chain with standard and low voltage threshold transistor. CSA test area Amplifiers chain with standard and low voltage threshold transistor. 3T Matrix Standard 3-transistor readout chain Each pixel 150µm x 150µm 3T Matrix Standard 3-transistor readout chain Each pixel 150µm x 150µm CSA Matrix Charge sensitive amplifier readout chain Each pixel 150µm x 150µm CSA Matrix Charge sensitive amplifier readout chain Each pixel 150µm x 150µm 0.2µm fully depleted (FD-SOI) CMOS by OKI Semiconductor, Japan 10 November, 2011SCK-CEN Meeting5

6. Pixel Matrix A matrix of pixels with three transistor readout. - Readout controlled by a shift register to activate on column at a time - Different shaped implants to improve breakdown voltage 10 November, 2011SCK-CEN Meeting6

7. Readout Chain RfRf CfCf Charge Sensitive Amplifier Vth C dif R dif R int C int Shaping AmplifierDigitizer Detector 10 November, 2011SCK-CEN Meeting7

8. Amplifier Measurements Injected charge (1MIP) Output of shaper Output of CSA ParametersSpecification Power supply V DD +1.8 Detector Capacitance C d 0.25pF Detector Signal1 MIP ( 23.000e - ) Feedback resistance R F >100MΩ Feedback capacitance C F 37.57fF TRAPPISTE-2 Data 10 November, 2011SCK-CEN Meeting8

9. CSA DC Sweep DC Sweep Characterizations - Simulations match measurements - Shift of transfer curve with bias ring voltage 10 November, 2011SCK-CEN Meeting9

10. Test System FPGA board to program test routines. Main board: - Voltage and current sources - DACs to set appropriate biases - ADC to read output voltages Daughter board to accommodate test devices and package types. 10 November, 2011SCK-CEN Meeting10

11. Schedule 10 November, 2011SCK-CEN Meeting11 Start of TRAPPISTE project2008 TRAPPISTE-12009 TRAPPISTE-22011 TRAPPISTE-3 Laser and beam tests L. Soung Yee PhD 2012 TRAPPISTE-4 P. Alvarez PhD (UAB) 2013 TRAPPISTE-5 (engineering model)2015 Manpower required: 1 Post-doc + 1 PhD

12. Backup Slides 10 November, 2011SCK-CEN Meeting12

13. Measurement of Transistor Characteristics Influence of back bias on transfer curves and transistor parameters. 10 November, 2011SCK-CEN Meeting13

14. Discriminator Measurements Discriminator measurements - Output for various threshold voltages - Influence of bias on detector ring 10 November, 2011SCK-CEN Meeting14