2 STAFF Lecturers: (Part 1) Mr. Aaron Tan Tuck Choy S16, #06-16 email@example.com firstname.lastname@example.org (Part 2) Dr Tulika Mitra S16, #06-12 email@example.com firstname.lastname@example.org Tutors and Lab TAs –To be updated.
4 COURSE DESCRIPTION This is a first module in digital systems and computer organisation. The aim of this module is to familiarise students with the fundamental building blocks of digital computers. Students learn to specify and design small and medium-sized digital circuits using systematic design procedure, and the basic building blocks of a computer system. This module covers The basic building blocks and design methods used in the construction of synchronous digital systems A variety of representations of digital systems, such as truth tables, logic gates, timing diagrams, state diagrams, etc. Basic organisation and von Neumann model. Overview of assembly language programming.
5 SYLLABUS OUTLINE Part I Number systems and information coding Boolean Algebra & Function Simplification Combinational Circuits Performance/Benchmarking Part II Basic processor organisation I/O Devices and Buses Control- and data-path Instruction set and Assembly Language Pipelining Memory organisation and hierarchy
6 RECOMMENDED TEXTS Main texts: (For Part 1) Digital Logic Design by Aaron Tan, McGraw-Hill. (For Part 2) Computer Organization & Design by David A. Patterson and John L. Hennessy, 3rd ed, Morgan Kaufmann.
7 ASSESSMENTS Tentative Final Exam: 50% Term test 1: 15% (tentative) Term test 2: 15% (tentative) Lab Assignments: 10% (tentative) Tutorial Assignments: 10% (tentative)
8 COURSE WEBSITE More details at http://www.comp.nus.edu.sg/~cs1104http://www.comp.nus.edu.sg/~cs1104
9 POLICIES (1/4) Communication: e-mail, IVLE and website. Check these out regularly. E-mail: For urgent matters. Official e-mail address: @comp.nus.edu.sg or @nus.edu.sg No outside addresses like yahoo, hotmail, etc. IVLE (https://ivle.nus.edu.sg/): Discussion and announcements.https://ivle.nus.edu.sg/ Course website: Course information, updates and announcements.
10 POLICIES (2/4) Notes and handouts Download from course website. Additional handouts may be distributed in class. Attendance No unofficial swapping of class. Absentism Submit MC or reason (endorsed by recognized authority) to your tutor for record.
11 POLICIES (3/4) Switching of class. You are to stick to your allocated group. To make up for a missed class (with valid reason), please inform your tutor. Late Submission. Deadline of assignments must be strictly adhered to. Plagiarism. Penalty: zero mark, name will be submitted to undergraduates office.
12 POLICIES (4/4) Preparation for classes. Tutorials – prepare answers to present in class. Labs – prepare diagrams and fill in lab reports before lab. Be serious and assume responsibility for your learning.
13 ANNOUNCEMENTS On-line tutorial registration – please check out http://www.cors.nus.edu.sg/http://www.cors.nus.edu.sg/ Course begins from Chapter 2: Number Systems and Codes. Tutorials and labs start on week 3.
16 LOGIC TRAINER (3/4) A common group +5V The other 19 points are connected to +5V
17 LOGIC TRAINER (4/4)... A common group 74LS00 A chip
18 LAB PREPARATION Video –Visit IVLE –Click on “Multimedia Webcast” “Media” “CS1104 Lab” Demo lab (Lab #0) –22 nd January 2007. –Venues: Micro-lab and Logic lab, located on S16 level 7. –According to your lab timing.