1. Introduction To Embedded System Design Embedded Systems Architecture : A Comprehensive Guide for Engineers and Programmers - An Elsevier Science Publication N ame of University - Class Title

2. N ame of University - Class TitleOverview What is an Embedded System? Embedded Systems Design –Embedded Systems Design & Development Lifecycle Model What is an Embedded Systems Architecture? –The 6 Stages of Creating an Embedded Architecture. Stage 1 : Have a Strong Foundation –Know Your Standards –Embedded Software Putting It All Together –Stages 2-6 of Creating an Architecture

3. N ame of University - Class Title What Is An Embedded System ? A type of computer system. Some of the Most Common Traditional Definitions : –Embedded systems are more limited in hardware and/or software functionality then the PC. –An embedded system is designed to perform a dedicated function –… Why don’t these definitions entirely apply, today?

4. N ame of University - Class Title What is an Embedded System [Continued]? Automotive –i.e. : Ignition Systems, Engine Control, Antilock Braking System, … Consumer Electronics –i.e. : TVs, STBs, appliances, toys, automobiles, cell phones … Industrial Control –i.e. : robotics, control systems… Medical –i.e. : Infusion Pumps, Dialysis Machines, Prosthetic Devices,Cardiac Monitors, … Networking –i.e. : routers, hubs, gateways, … Office Automation –i.e. : fax machines, photocopiers, printers, monitors, … ** Aside from being types of computer systems, there is no single definition or characterization of embedded systems reflecting them all. **

5. N ame of University - Class Title Embedded Systems Design Embedded Systems Design and Development Lifecycle Model Product Concept Preliminary Requirements Analysis Creation of Architecture Design Develop Version of Architecture Deliver Version of Architecture Review & Obtain Feedback Incorporate Feedback Deliver Final Version of Architecture Develop [Implement] the System Review and Test the System Deliver & Maintain the System Incorporate Feedback Phase 1 : Creating The Architecture Phase 2 : Implementing the Architecture Phase 3 : Testing the System Phase 4 : Maintaining the System

6. N ame of University - Class Title What is Embedded Systems Architecture? An abstraction of the embedded device that represents the embedded system as some combination of interacting elements. - physically represented as structures - many types of structures Layered, Kernel, Decomposition, Client/Server, Process, … Sum of Structures = Embedded Architecture Why care about the architecture of an embedded system?

7. N ame of University - Class Title 6 Stages of Creating an Embedded Architecture Many industry popular methodologies for creating architectures (adaptable to embedded systems) –Rational Unified Process (RUP), Attribute Driven Design (ADD), Object Oriented Process (OOP), … More Pragmatic Approach [the best of all worlds] –Stage 1 : Having a Solid Technical Base –Stage 2 : Understanding the ABCs of Embedded Systems –Stage 3 : Defining the Architectural Patterns & Reference Models –Stage 4 : Creating the Architectural Structures –Stage 5 : Documenting the Architecture –Stage 6 : Analyzing & Evaluating the Architecture

8. Stage 1 : Having a Strong Technical Base S tanford University - EE109

9. N ame of University - Class Title Embedded Systems Model Hardware Layer System Software Layer Application Layer Embedded System

10. N ame of University - Class Title EE109 Platform and the Embedded Systems Model System Layer Application Layer MemoryManagementDrivers Hardware Cypress EZ-USB FX-2 Xilinix FPGA 16 MB DRAM....... USB Drivers Interrupt Drivers User Interface...CameraApplication

11. N ame of University - Class Title Know Your Standards Market Specific –Consumer Electronics, Medical, Industrial Automation & Control, Networking & Communications, Automotive, Aerospace & Defense, Office Automation, … General Purpose –Networking, Programming Language, Security, Quality Assurance, … Hardware Layer System Software Layer Application Software Layer Market Specific Standards MHP ATSC DTV HAVi FDA … General Purpose Standards PJava J2ME SSL128 … Ethernet TCP/IP HTTP …

12. N ame of University - Class Title How can a Programming Language Spec Add to An Embedded System’s Architecture ? Target [Embedded System] Hardware Layer System Software Layer Application Layer Host [Development System] Compiler Linker … Preprocessor System Software Layer Hardware Layer Application Layer Translating Code –Interpretation, Just-in-Time (JIT), Way-Ahead-of-Time (WAT)/Ahead-of-Time (AOT) Garbage Collection –Copying, Mark&Sweep, Generational, …

13. N ame of University - Class Title Translation of Code on Host : Compiling C Source File (s) C Header File (s) C Compiler Preprocessing Compiling C Object File (s) Linker C Executable File C System Libraries Embedded System Host Computer

14. N ame of University - Class Title Translation of Code on Target Source File (s) Compiler Byte Code File (s) Source L1 Source L2 Source L3 Source L4 Source L5 Source L6 Target Code for Source L1 Target Code for Source L2 Target Code for Source L3 …………. vtab Byte Code 1 Byte Code 2 Byte Code 3 …. Byte Code 1 Parsing & Interpreting Byte Code 1 JIT Compiling Byte Code 2 Parsing & Interpreting Byte Code 2 JIT Compiling … Compiled Byte Code 3 … Compiled Byte Code 2 Compiled Byte Code 1 First Pass of Processing Byte Code 2nd and Additional Passes of Processing Byte Code vtab Byte Code 1 Byte Code 2 Byte Code 3 …. Byte Code 1 Parsing Byte Code 1 Interpreting Byte Code 2 Parsing Byte Code 2 Interpreting … Interpretation Just-In-Time [JIT] JVM WAT Compiler.class File Byte Code 1 Byte Code 2 Byte Code 3 …. object File JVM Linker Runtime Libraries executables 1 2 Way-Ahead-of- Time/Ahead-Of-Time [WAT/AOT] Host

15. N ame of University - Class Title Garbage Collection : Copying Copying Garbage Collector Memory Before GC Object 1 Object 2 Object 3 Object 4 Memory After GC Object 1 Object 2 Object 4

16. N ame of University - Class Title Garbage Collection : Mark&Sweep Mark & Sweep Garbage Collector  [Mark] Memory Before GC Object 1 Object 2 Object 3 Object 4    Memory After GC Object 1 Object 2 Object 4 [Sweep]

17. N ame of University - Class Title Garbage Collection : Generational Older Generation Mark (Sweep) & Compact GC Mark,Sweep, & Compact Garbage Collector  [Mark] Memory Before GC Object 1 Object 2 Object 3 Object 4    Memory After GC Mark & Sweep Object 1 Object 2 Object 4 [Sweep] Memory After GC Compaction Object 1 Object 2 Object 4 [Compact] Copying Garbage Collector Memory Before GC Object 1 Object 2 Object 3 Object 4 Memory After GC Object 1 Object 2 Object 4 Youngest Generation [Nursery] Copying GC

18. N ame of University - Class Title How can Java Add to An Embedded System’s Architecture ? Embedded Java –Standards (pJava, J2ME, Embedded Java, …) –Processing Bytecode (Interpretation, JIT, WAT/AOT) –Garbage Collection (Copying, Mark&Sweep, …) JVM part of System layer i.e. : Skelmir’s Cee-J, Esmertec/Insignia’s Jeode and Jbed, Tao’s Intent, Kava’s KavaVM … JVM in Hardware i.e. : ARM’s Gazzelle, AJile’s aj100,… JVM compiled in application i.e. Esmertec’s Jbed, Kava’s KavaVM, IBM’s J9 … Hardware Layer System Software Layer Application Layer JVM Hardware Layer System Software Layer Software Layer Application Layer Hardware Layer System Software Layer Application Layer Java Processor Java Device Drivers JVM

19. N ame of University - Class Title How can.NetCE Add to An Embedded System’s Architecture ?.NetCE Compact Framework –Standard = Common Language Specification –Processing Bytecode (Interpretation/JIT) –Garbage Collection ( Generational) System Software Layer CLR [JIT] Execution Engine BCL/Platform Extension Libraries Application Layer MSIL Application Class Loader.NET Compact Framework GC Hardware Layer Memory

20. N ame of University - Class Title How can Scripting Languages Add to An Embedded System’s Architecture ? Scripting Languages –Perl, JavaScript, HTML, … –Processing Bytecode (Interpretation) Hardware Layer Application Software Layer Browser Real Audio HTML4.0 DOM 0 SSL 128 Bit Encryption CSS 1 … Java Script HTTP System Software Layer

21. N ame of University - Class Title How can Networking Add to an Embedded System’s Architecture ? Network 2 – Client/Server ArchitectureNetwork 1 – Peer-to-Peer Architecture Client A Networking Components Client B Networking Components Server Client C Networking Components Device A Networking Components Device B Networking Components Device C Networking Components Transmission Medium Distance Network ‘s Overall Structure

22. N ame of University - Class Title Open Systems Interconnection (OSI) Model Hardware Layer System Software Layer Application Software Layer Physical Layer Data-Link Layer Network Layer Transport Layer Session Layer Presentation Layer Application Layer OSI Model

23. N ame of University - Class Title Networking Layers Transmission Medium Layer 7 Layer 1 Physical Layer Data Link Layer Network Layer Transport Layer Session Layer Presentation Layer Application Layer Layer 7 Layer 1 Physical Layer Data Link Layer Network Layer Transport Layer Session Layer Presentation Layer Application Layer Data Header 2 DataHeader 1 DataHeader 3 DataHeader 4 DataHeader 5 Data Application Presentation Session Transport Network Data Link Physical

24. N ame of University - Class Title OSI and Real-World Networking Models : TCP/IP Hardware Layer System Software Layer Network Access Layer Internet Layer Transport Layer Application Software Layer Application Layer TCP/IP Model Physical Layer Data-Link Layer Network Layer Transport Layer Session Layer Presentation Layer Application Layer OSI Model

25. N ame of University - Class Title OSI and Real-World Networking Models : WAP Hardware Layer System Software Layer Application Software Layer Physical Layer Data-Link Layer Network Layer Transport Layer Session Layer Presentation Layer Application Layer OSI Model Transaction Layer Session Layer Application Layer WAP Model Security Layer Transport Layer

26. N ame of University - Class Title OSI and Real-World Networking Models : Bluetooth Hardware Layer System Software Layer Application Software Layer Transport Protocol Group Middleware Protocol Group Application Protocol Group Bluetooth Model Physical Layer Data-Link Layer Network Layer Transport Layer Session Layer Presentation Layer Application Layer OSI Model TCP/IP WAP

27. N ame of University - Class Title OSI Layer 1 : Physical Layer Hardware Layer System Software Layer Application Software Layer WAN Wireless CDMA TDMA EIA/TIA 232 (RS-232) ATM (SONET,…) Wired LAN WirelessWired IEEE802.11 Wireless Radio & IR Bluetooth Radio and Broadband IEEE 802.3 Ethernet IEEE 802.5 Token Ring ARCnet FDDI… TDMA GPRS GSM CPDP … … EIA/TIA 449 (RS-449) X.21 EIA/TIA 232 (RS-232) …

28. N ame of University - Class Title Device 1Device 2 Physical Layer Processing Transmission Medium Layer 1Physical Layer Data Link Layer 1001110101110 Layer 2 Layer 1Physical Layer Data Link Layer 0111010111001

29. N ame of University - Class Title OSI Layer 2 : Data-Link Layer Hardware Layer Application Software Layer System Software Layer WAN Wireless PPP NS X.25 PSTN LAPB PPP Wired LAN WirelessWired IEEE 802.3 Ethernet IEEE 802.5 Token Ring ARCnet BSSGP RFCOMM … … HDLC SLIP ATM … IEEE 802.2 LLC/SNAP Physical Layer IEEE802.11 MAC Bluetooth LMP, L2CAP, Baseband … … IEEE802.2 LLC/SNAP FDDI

30. N ame of University - Class Title Data-link Layer Processing Layer 3Network Layer Layer 1Physical Layer Data Link Layer Layer 2 Datagram 1110111000110 1 Data-link Headers Stripped [data] Data-Link Headers Appended to Data Field DataLink Frame 110110101101110111011101110001100111000001100101000111 [Start of frame] [source addr][dest addr ][admin][data] [ error chk][end of frame]

31. N ame of University - Class Title OSI Layer 3 : Network Layer Hardware Layer System Software Layer ISDN…. Data-link Layer Physical Layer RIP IP BGP…OSPFICMP TCP/IP Stack VIP …RTPICP Banyan/VINES BSSMAPBSSAPSCCP GPRS Application Software Layer

32. N ame of University - Class Title Network Layer Processing Layer 4Transport Layer Layer 2Data-link Layer Network Layer Layer 3 Packet Network Headers Stripped [data] Network Header Appended to Data Field Network Datagram 11011011001101110001100001101101110111011101110001100111000001100101000111 [IP Version] [header len][data type][data len][frag info] [# hops][upper layer][checksum][source IP][dest IP][data] Datagram

33. N ame of University - Class Title OSI Layer 4 : Transport Layer Hardware Layer Application Software Layer System Software Layer Data-link Layer Physical Layer Network Layer UDPTCP… TCP/IP Stack DTAPBSSMAP… GSMWAP WDP…

34. N ame of University - Class Title Transport Layer Processing Layer 5 Session Layer Layer 3 Network Layer Transport Layer Layer 4 Message/Pscket Transport Headers Stripped [data] Transport Header Appended to Data Field TCP Packet 11011011001101110001100001101101110111011101110001100111000001100101000111 [Src Port][Dest Port][Seq #][Ack #][H Len][Res][Uflag][Pflag][Rflag][Sflag][Fflag][WinSz][Chksum][UP[O] [Data] Packet

35. N ame of University - Class Title OSI Layer 5 : Session Layer Hardware Layer System Software Layer Data-link Layer Physical Layer Network Layer Transport Layer Application Software Layer NFSDNS… TCP/IP Stack WAP Stack WSP… …

36. N ame of University - Class Title Session Layer Processing Layer 6 Presentation Layer Layer 4 Transport Layer Session Layer Layer 5 Message Session Headers Stripped [data] Session Header Appended to Data Field L2CAP Packet 1101101100110111000110000110 [Length][Destination Channel ID][Data] Message/Packet

37. N ame of University - Class Title OSI Layer 6 : Presentation Layer Hardware Layer System Software Layer Data-link Layer Physical Layer Network Layer Transport Layer Application Software Layer MIDIJPEG… Session Layer SSLMPEG

38. N ame of University - Class Title Presentation Layer Processing Layer 7 Application Layer Layer 5 Session Layer Presentation Layer Layer 6 Message [data] Presentation Header Appended to Data Field Bluetooth Message 1101101100110111000110000110 [Length][Destination Channel ID][Data] Messag e Message conversion

39. N ame of University - Class Title OSI Layer 7 : Application Layer Application Software Layer Hardware Layer System Software Layer Data-link Layer Physical Layer Network Layer Transport Layer IMAP4POP3 HTTP Session Layer SMTPFTP Presentation Layer … Telnet BootpSNMPRLOGIN MIME MIMENFS Finger NCPAPPCBT-SDP

40. Embedded Hardware S tanford University - EE109

41. N ame of University - Class Title Many Many Many Embedded Processors To Choose From ArchitectureProcessorManufacturer AMDAu1xxxAdvanced Micro Devices,… ARMARM7, ARM9, …ARM, … C16XC167CS, C165H, C164CI,…Infineon,… ColdFire5282, 5272, 5307, 5407, …Motorola,… I960 Vmetro, … M32/R32170, 32180, 32182, 32192, …Renesas/Mitsubishi, … M CoreMMC2113, MMC2114, …Motorola MIPS32R3K, R4K, 5K, 16, …MTI4kx, IDT, MIPS Technologies, … NECVr55xx, Vr54xx, Vr41xxNEC Corporation, … PowerPC (PPC)82xx, 74xx,8xx,7xx,6xx,5xx,4xxIBM, Motorola,… 68k680x0 (68K, 68030, 68040, 68060,…),683xxMotorola, … SuperH (SH)SH3 (7702,7707, 7708,7709), SH4 (7750)Hitachi, … SHARC Analog Devices, Transtech DSP, Radstone, … strongARM Intel, … SPARCUltraSPARC IISun Microsystems, … TMS320C6xxx Texas Instruments, … x86X86 [386,486,Pentium (II, III, IV)…]Intel, Transmeta, National Semiconductor, Atlas, … TriCoreTriCore1, TriCore2, …Infineon,… ………

42. N ame of University - Class Title ISA Models Application Specific –Controller –Datapath –Finite State Machine with Datapath [FSMD] –Java Virtual Machine –…. General Purpose –Complex Instruction Set Computing [CISC] –Reduced Instruction Set Computing [RISC] Instruction Level Parallelism –Single Instruction Multiple Data [SIMD] –Superscaler Machine –Very Long Instruction Word (VLIW) Computing –….

43. N ame of University - Class Title Implementing an ISA & Von-Neumann data from cpu or input devices stored in memory until a cpu or output device request controls usage and manipulation of data Master Processor Memory OutputInput brings data into the embedded systemgets data out of the embedded system 5 system components commonly connected via buses embedded system board OutputInput Memory CPU

44. Embedded Software S tanford University - EE109

45. N ame of University - Class Title Embedded Software : The System Software Layer Hardware Layer System Software Layer Application Software Layer Device Driver Layer Hardware Layer System Software Layer Application Software Layer Device Driver Layer Operating System Layer Hardware Layer System Software Layer Application Software Layer Device Driver Layer Middleware Layer Hardware Layer System Software Layer Board Support Package Layer Device Drivers Operating System Layer Application Software Layer Hardware Layer System Software Layer Application Software Layer Device Driver Layer Operating System Layer Middleware Layer Hardware Layer System Software Layer Application Software Layer Operating System Layer Middleware Device Drivers Hardware Layer System Software Layer Application Software Layer Operating System Layer Middleware Device Driver Layer Hardware Layer System Software Layer Board Support Package Layer Device Drivers Application Software Layer Operating System Layer Middleware Hardware Layer System Software Layer Board Support Package Layer Device Drivers Application Software Layer Operating System Layer Middleware Layer …………

46. N ame of University - Class Title What are Device Drivers? Hardware Layer System Software Layer Application Layer Device Drivers I/O Ethernet (SCC1) RS-232 (SMC2) BusesMemory… PCMCIA … I2C DMA (IDMA)Interrupts T1/E1 (TDM) ISDN (TDM) … MMU L1 Cache Timers … Generic (Architecture and Board Specific Driver)Architecture Specific Device Drivers Hardware Layer System Software Layer Application Software Layer Device Driver Layer r Higher-layer Interface ----------------------- Hardware Interface Higher-layer Interface Hardware Interface

47. N ame of University - Class Title Most Common Types of Device Drivers Routines Hardware Startup, initialization of the hardware upon power-on or reset. Hardware Shutdown, configuring hardware into its power-off state. Hardware Disable, allowing other software to disable hardware on-the-fly. Hardware Enable, allowing other software to enable hardware on-the-fly. Hardware Acquire, allowing other software gain singular (locking) access to hardware. Hardware Release, allowing other software to free (unlock) hardware. Hardware Read, allowing other software to read data from hardware Hardware Write, allowing other software to write data to hardware Hardware Install, allowing other software to install new hardware on-the- fly Hardware Uninstall, allowing other software to remove installed hardware on-the-fly

48. N ame of University - Class Title Embedded Operating Systems Process Management. –Process Implementation –Scheduling –Intertask Communication & Synchronization Interrupt Handling, Error Detection, … –… Memory Management. –Segmentation –Paging –Virtual Memory –System Security –… I/O System Management. –File System –… Embedded OS Middleware (optional) Device Drivers (Optional) Kernel Memory Management Process Management I/O System Management Interrupt/Error Handling Security System Management

49. N ame of University - Class Title OS Models Hardware Monolithic Kernel I/O Drivers Memory Drivers Interrupt Drivers file I/OMemory Management Process Management Higher-level Software (Middleware, Applications) The Operator User Program Operator Process Communication Input/Output Management Memory & Drum Management Processor Allocation and Multiprogramming Layered OS Layer 5 Layer 4 Layer 3 Layer 2 Layer 1 Layer 0 Device Drivers Hardware Microkernel I/OMemoryInterrupt Memory Management Process Management Higher-level Software (Middleware, Applications)

50. N ame of University - Class Title Process Management What is a process? Tasks vs. Threads Program 1 OS Task Program 1 Task Registers Task Stack Program 1 Program 2 … OS (ie:..) Task 1 Program 1 Task 1 Registers Task 1 Stack Task 2 Program 1 Task 2 Registers Task 2 Stack Task 3 Program 2 Task 3 Registers Task 3 Stack Thread 1 Program 1 Thread 1 Registers Thread 2 Program 2 Thread 2 Registers Thread 3 Program 3 Thread 3 Registers Memory

51. N ame of University - Class Title Unitasking vs. Multitasking OSes Program 1 Program 2 … Multitasking OS Task 1 Program 1 Task 1 Registers Task 1 Stack Process 2 Program 1 Task 2 Registers Task 2 Stack Process 3 Program 2 Task 3 Registers Task 3 Stack Program 1 Unitasking OS Task Program 1 Task Registers Task Stack

52. N ame of University - Class Title The OS Multitasking Illusion OS How? –Implementation –Scheduling –Synchronization –Inter-task Communication

53. N ame of University - Class Title Process Implementation & the Task Hierarchy OS Initial Task Task Task Creation Task Deletion Task Suspension Task Resumption

54. N ame of University - Class Title Task Creation and Fork/Exec > fork System Call 1. Parent task makes fork system call to create child task Memory Parent Task TCBTCB Process Table Parent Task stackParent Program Memory Child Task TCBTCB Process Table Parent Task stackParent Program Child Task [Parent Task Clone] stackParent Program exec System Call 3. Parent task makes exec system call to load child task’s program Memory Child Task TCBTCB Parent Task stackParent Program Child Task stackChild Program 4. The child task program loaded into memory.

55. N ame of University - Class Title Task Creation & Spawn > Spawn System Call 1. Parent task makes spawn system call to create child task 2. Child Task loaded into memory, including program, TBC, stack, etc. Memory Child Task TCBTCB Memory Parent Task TCBTCB Process Table Parent Task stackParent Program Parent Task stackParent Program Child Task stackChild Program

56. N ame of University - Class Title Task Deletion System Call Garbage Collection I 1 3 2 4

57. N ame of University - Class Title Resuming & Suspending Tasks : Task States 3 Main States –Ready : The process is ready to be executed at anytime, but is waiting for permission to use the CPU. –Running : The process has been given permission to use the CPU, and can execute. –Blocked or Waiting: The process is waiting for some external event to occur before it can be “ready” to “run”. Task States and Queues

58. N ame of University - Class Title Process State Transition Models When a task that is moved from one of the queues (READY or BLOCKED/WAITING) into the RUNNING state, it is called a context switch.

59. N ame of University - Class Title Scheduling in OSes Non-preemptive Schedulers –First-Come-First-Serve (FCFS)/ Run-To-Completion –Shortest Process Next [SPN]/ Run-To-Completion –Co-operative T N …….. T 3 T 1 T 2 Scheduler Master CPU T1 T2 Current Task No Context Switching After This Point T N …….. T 3 T 1 T 2 Scheduler Master CPU T2 T1 T3 Current Task Time T1 = 10ms Time T3 = 2ms Time T2 = 20 ms T N …….. T 3 T 1 T 2 Scheduler Master CPU T1 T2 Current Task Only Running Task can force a context switch before completion

60. N ame of University - Class Title Scheduling in OSes [Continued] Preemptive Schedulers –Round Robin/FIFO (First-in-First out) Scheduling Priority Time HIGH LOW KEY = preemption | = task completion Task 1 Task 2Task 3Task 2Task 1Task 3 Time slice

61. N ame of University - Class Title Scheduling in OSes [Continued] Preemptive Schedulers [Continued] –Priority [Preemptive] Scheduling Priority Time HIGH LOW KEY = preemption | = task completion Task 1 Task 2 Task 3 Task 2 Task 1

62. N ame of University - Class Title Scheduling in OSes [Continued] Preemptive Schedulers [Continued] –EDF (Earliest Deadline First)/Clock Driven Scheduling What is an RTOS? –A preemptable kernel! –Deterministic r p2p3p1 p2p3qp1 r p2p3qp1 r admit r?

63. N ame of University - Class Title Intertask Communication & Synchronization Memory Sharing Message Passing Signaling –Interrupt Handling Memory Shared Data Process 1 Process 2 Process N

64. N ame of University - Class Title Memory Management User vs. Kernel Memory Space User Memory Space Divided Into Partitions –Segments –Pages –What is Virtual Memory? User Memory Allocation and Deallocation Scheme Depends on Programming Language

65. N ame of University - Class Title What is a BSP [Board Support Package] ?

66. N ame of University - Class Title Middleware & Application Software Hardware Layer System Software Layer Application Software Layer Video-On-Demand e-mail browser Web server Navigation Hardware Layer System Software Layer Application Software Layer Middleware Layer

67. N ame of University - Class Title Middleware Examples Networking Middleware Hardware Layer System Software Layer Application Software Layer Physical Layer Data-Link Layer Network Layer Transport Layer Session Layer Presentation Layer Application Layer OSI Model Hardware Layer Middleware Layer pJava 1.1.8 JVM java.net Socket API Application Layer IP TCP UDP

68. N ame of University - Class Title Application Layer Examples Hardware Layer System Software Layer Application Software Layer …HTTPFTP Hardware Layer System Software Layer Application Layer JVM Hardware Layer System Software Layer Application Software Layer Browser Real Audio HTML4.0 DOM 0 SSL 128 Bit Encryption Encryption CSS 1 Java Script HTTP

69. Putting It All Together S tanford University - EE109

70. N ame of University - Class Title 6 Stages Creating An Embedded System’s Architecture Stage 1 Having a solid technical base [Software & Hardware] Stage 2 Understanding the ABCs of Embedded Systems Stage 3 Defining the architectural patterns & reference models Stage 4 Creating the architectural structures Stage 5 Documenting the architecture Stage 6 Analyzing and evaluating the architecture.

71. N ame of University - Class Title Stage 2 : Understanding the ABCs [Architecture Business Cycles] of Embedded Systems Influences on Architecture Architecture System Stakeholders Technical Requirements Engineers Managers Customers …. Sales & Marketing Requirements Quality Assurance Requirements Industry Standard Requirements …… Embedded System Architecture Business Cycle

72. N ame of University - Class Title What are General ABC Requirements? - Business (Sales & Marketing) : sellability (how the device will sell), time-to-market (when will the device be delivered), costs (development, overhead, etc.), device lifetime (how long the device will be available on the market), target market (what type of device it is), schedule & features (schedule of versions to be released with associated features), etc. - Technical : performance, user friendliness (usability), modifiability (how simple it is to modify the various functional elements), security, reliability, portability, testability, availability, technical industry standards (see industry standards below), etc. - Industry : typically are a result of industry standards (introduced at start of presentation), which may be market specific (i.e. TV standards, medical device standards, etc.) or general purpose across different families of devices (programming language standards, networking standards, etc.) - Quality Assurance : testability (how easily the system can be tested), availability (when the system is available for testing), schedule & features (schedule of versions to be tested with associated features), QA industry standards (ie : ISO9000, ISO9001, and so on – see industry requirements above), etc. ….

73. N ame of University - Class Title Performance Scenerio Internal Stimulus Sources (other internal system elements) External Stimulus Sources (user, data over network, etc.) Performance Stimuli (periodic events, one-time events, etc.) Effected Element (Entire Embedded System) System Response (events processed in timely manner, etc) Environment (normal, high network traffic, etc.) System Response Measures (throughput, latency, data loss, etc.)

74. N ame of University - Class Title How to Derive System Components from Performance Requirements? Internal Stimulus Sources (other internal system elements) External Stimulus Sources (user, data over network, etc.) Performance Stimuli (periodic events, one-time events, etc.) Embedded System System Response (events processed in timely manner, etc) System Response Measures (throughput, latency, response timedata loss, etc.) Tactic : Resource Management RequestsArbitration…… Operating System - Process events concurrently reducing response times -Scheduler manages requests and arbitration of resources to events -…. response time decrease

75. N ame of University - Class Title Security Scenerio External Stimulus Sources (user, data over network, etc.) Security Stimuli (system shutdown, altering data, copying data, etc.) Effected Element (Data in Memory of Embedded System, other accessible system services) System Response (recovering, detecting, resisting attacks, etc) Environment (normal, connected/disconnected to network, data uploads/ downloads, etc.) System Response Measures (latency in system recovery, effectiveness of system fix for previously encountered stimuli,etc.)

76. N ame of University - Class Title How to Derive System Components from Security Requirements? External Stimulus Sources (user, data over network, etc.) Security Stimuli (system shutdown, altering data, copying data, etc.) Embedded System System Response (recovering, detecting, resisting attacks, etc) System Response Measures (latency in system recovery, effectiveness of system fix for previously encountered stimuli,etc.) Tactic : Managing Resource Access AuthenticationAuthorization …… Operating System - Memory Management - Security Management -…. fewer security breeches Java [JVM] - Garbage Collector - Cryptography - Authentication - Authorization - Security “Sandbox” -….

77. N ame of University - Class Title Testability Scenerio Internal Stimulus Sources (other internal system elements) External Stimulus Sources (user, data over network, etc.) Testability Stimuli (hardware/software completed, hardware/software update, etc.) Effected Element (Some or all software/hardware elements within Embedded System) System Response (easily controlled and observable responses to tests,, etc) Environment (development, production, in field, etc.) System Response Measures (testing times, number of tests performed, accuracy of tests, etc.)

78. N ame of University - Class Title How to Derive System Components from Testability Requirements? Embedded System Tactic : Internal Monitoring VisibilityAccessibility …… Processor - Built-In Monitor easier testing Debug System Software Subroutines - Manipulate Variables - Memory Dumps - Single-step through executing code …. Internal Stimulus Sources (other internal system elements) External Stimulus Sources (user, data over network, etc.) Testability Stimuli (hardware/software completed, hardware/software update, etc.) System Response (easily controlled and observable responses to tests,, etc) System Response Measures (testing times, number of tests performed, accuracy of tests, etc.)

79. N ame of University - Class Title Stage 3 : Defining the Architectural Patterns & Reference Models Create the system profile Make a matrix to determine if components meet cost, time- to-market, performance... requirements Requirement 1Requirement 2Requirement 3Requirement …Requirement “N” Product 1 YES Features … NONOT YET Next Year …… Product 2 YES Features … YES Features … YES Features … …… Product 3NO YES Features … NO…… Product 4 YES Features … NOT YET In 3 Months NOT YET In 6 Months …… Product ……. … Product “N”……………

80. N ame of University - Class Title Selecting a Programming Language Real-TimeFast PerformanceMHP-SpecATVEF-SpecBrowser Application … AssemblyYES NOT Required … CYES Slower then assembly NOT Required … C++YES Slower then C NOT Required ….NetCE (C#)NO WinCE NOT RTOS Depends on processor, slower then C on less powerful processors NOT Required … JVM (Java)Depends on JVM’s Garbage Collector and is OS ported to is RTOS Depends on JVMs byte code processing scheme (WAT almost as fast as C where interpretation requires more powerful processor i.e. 200+ MHz), slower then C on slower processors YESNOT Required … HTML (Scripting)Depends on what language written in, and the OS (an RTOS in C/assembly OK,.NetCE platform no, Java depends on JVM Slower because of the interpretation that needs to be done but depends on what language interpreter written in (see above cells of this column) NOT RequiredYES … …………………

81. N ame of University - Class Title Selecting an OS Questions to ask : –1. What type of systems typically use or require an OS? –2. Is an OS needed to fulfill system requirements? –3. What is needed to support an OS in a design? –4. How to select the OS that best fits the requirements? ToolsPortabilityNon-kernelProcessorScheduling Scheme … vxWorksTornado IDE, SingleStep debugger, … BSPDevice Drivers w/ BSP, graphics, networking, … x86, MIPS, 68K, ARM, strongARM, PPC … Hard Real-Time, Priority- based … … LinuxDepends on vendor for development IDE, gcc, … Depends on vendor, some with no BSP Device Drivers graphics, networking, … Depends on vendor (x86, PPC, MIPS, …) Depends on vendor, some are hard real-time, others soft- real time … … JbedJbed IDE, Sun Java compiler, …BSPDevice Drivers – the rest depends on JVM specification (graphics, networking, …) PPC, ARM, …EDF Hard Real Time Scheduling … … …………………

82. N ame of University - Class Title Selecting a Master Processor Tools Java-specific Features OS Support … aJile aj100 Java Processor (Application Specific ISA)JEMBuilder, Charade debugger, J2ME/CLDC JVMNOT Needed… Motorola PPC823 (General Purpose ISA)Tornado tools, Jbed Tools, Sun tools, Abatron BDM… Implemented in software (Jbed, PERC, CEE-J, …) Coming Soon -- Linux, vxWorks, Jbed, Nucleus Plus, OSE, … … Hitachi Camelot Superscaler SoC(Instruction Level Parallel ISA)Tornado Tools, QNX Tools, JTAG, … Coming Soon -- Implemented in software (IBM, OTI, Sun VMs..) Coming Soon -- QNX, vxWorks, WinCE, Linux,.... … …………… Select processor on requirements and its impact on the remainder of the system (especially software). Why ? –The master processor essentially impacts what enhancements are implementable in software, and what constraints are placed upon the software

83. N ame of University - Class Title Stage 4 : Define the Architectural Structures “4+1” Model LogicalProcessDevelopmentDeployment ModuleComponent & Connector Allocation Validation - Logical Scenarios - Process Scenarios - Development Scenarios - Deployment Scenarios

84. N ame of University - Class Title Stage 5 : Document the Architecture Step 1 : A document outlining the entire architecture. Step 2 : A document for each structure. Step 3 : An architecture glossary. UML Sequence DiagramUML Use Case Diagram UserEmbedded Device ……. User opens application via user interface OS task spawned loading application into memory and begins to execute User selects option X in application Rough/Informal Sequence Diagram

85. N ame of University - Class Title Stage 6 : Analyze and Evaluate Architecture Step 1- Members of the evaluation team obtain copies of the architecture documentation from the responsible architect (s), and it explained to the various team members the evaluation process, as well as, the architecture information within the documentation to be evaluated. Step 2 - A list of the architectural approaches and patterns is compiled based upon feedback from the members of the evaluation team after they have analyzed the documentation. Step 3 – The architect (s) and evaluation team members agree upon the exact scenarios derived from the requirements of the system (the team responding with their own inputs of the architect’s scenarios : changes, additions, deletions, etc.), as well as, the priorities of the various scenarios are agreed upon in terms of both importance and difficulty of implementation. Step 4 - The (agreed upon) more difficult and more important scenarios are where the evaluation team spends the most time on evaluating, because these scenarios introduce the greatest risks. Step 5 – Results of evaluation team should include (at the very least) the 1) uniformly agreed upon list of requirements/scenarios, 2) benefits (i.e. the ROI – Return-On-Investment aka. the ratio of benefit to cost), 3) risks, 4) strengths, 5) problems, and 6) any of the recommended changes to the evaluated architectural design.