1. 2015/9/4System Arch 2008 (Fire Tom Wada) 1 SEMICONDUCTOR TECHNOLOGY -CMOS- Fire Tom Wada

2. 2015/9/4System Arch 2008 (Fire Tom Wada)2 What is semiconductor and LSIs Huge number of transistors can be integrated in a small Si chip. The size of the chip is roughly the size of nails. Currently, 10M transistors can be integrated. 1000 times integration comparing to 20 yrs ago. The cost of the chip is roughly same. All electronic equipments are powered by LSIs. PCs, Cellular phones, 3D graphics, Internet.

3. 2015/9/4System Arch 2008 (Fire Tom Wada)3 PC mother board Large Scale Integration

4. 2015/9/4System Arch 2008 (Fire Tom Wada)4 SONY PLAYSTATION 2 MAINBOARD Rendering LSI High Speed Memory Graphics LSI Direct RDRAM

5. 2015/9/4System Arch 2008 (Fire Tom Wada)5 Mobile Phone Mainboard Memory, Logic, Analog

6. 2015/9/4System Arch 2008 (Fire Tom Wada)6 Key device is LSI INTEL Pentium III module

7. 2015/9/4System Arch 2008 (Fire Tom Wada)7 This is a packaged LSI -Pentium III 300MHz Cache LSI- 15 mm 20 mm

8. 2015/9/4System Arch 2008 (Fire Tom Wada)8 Si chip is molded in the package. 2 million transistor Chip is connected to the pins thru wires.

9. 2015/9/4System Arch 2008 (Fire Tom Wada)9 6 inches Si wafer

10. 2015/9/4System Arch 2008 (Fire Tom Wada)10 8 inches Si wafer Hundreds of Chips on a Si Wafer

11. 2015/9/4System Arch 2008 (Fire Tom Wada)11 Several hundreds of chips are fabricated on a wafer simultaneously.

12. 2015/9/4System Arch 2008 (Fire Tom Wada)12 Chip photo - Motion Estimation Chip for HDTV camera - 9.1 mm 8.6 mm Your small finger ’ s nail size. 200M transistors.

13. 2015/9/4System Arch 2008 (Fire Tom Wada)13 Scanning Electron Microscope photo - Cross-section of the LSI - 0.5 micron

14. 2015/9/4System Arch 2008 (Fire Tom Wada)14 Structure Of CMOS LSI Isolation PN-Isolation, Local oxidation Si Substrate Bulk, epitaxial, SOI Well Structure N-type well in P-type Substrate Latch Up PNP Bipolar Transistor and NPN Bipolar Transistor Fabrication Process Technology

15. 2015/9/4System Arch 2008 (Fire Tom Wada)15 Cross-section of the LSI P-type Si substrate N-type well N+ P+ Metal wiring Poly-silicon N-type MOS transistor P-type MOS transistor Si wafer

16. 2015/9/4System Arch 2008 (Fire Tom Wada)16 Transistor module （ FEP) 65nm Lithography(VUV, EPL) Mask CMPplanarizatio n Low Resistance Contact with High Aspect ratio High κ Gate insulator Fine Cu interconnect Low κ interdielectric SiGe/Metal gate Multi-level Metalization Module （ BEP) Low Resistance Ultra shallow junction Low stress Shallow Trench Isolation Advanced Process Development

17. 2015/9/4System Arch 2008 (Fire Tom Wada)17 LSI integration trend - Moore ’ s law - Wide-TV, PHS phone DVD player DVD-ROM DVD-RAM DVD recorder Source: SEMATEC 81 10B 1B 100M 10M 1M 100K 10K 1K 8385878991939597990103050709 0.80.50.30.18 CHANNEL LENGTH (MICRON) 0.13 Digital HDTV receiver Number of transistors on a chip The number of transistors are increasing by 58% per year. - Moore ’ s Law -

18. 2015/9/4System Arch 2008 (Fire Tom Wada)18 Communications and Consumer Products Drive Semiconductor Sources: Applied Materials Corporate Marketing estimates, Dataquest 35% 30% 25% 20% 15% 10% 5% 0% 5%10%15%20%25%30%35% CAGR % (1997-2002) Semiconductor Industry Application Market Growth SC Content (As % of Equipment Cost) 3rd Generation 2nd Generation 1st Generation Color TV Car Radio Video Camera Video Camera Portable Computing Switching & LAN Switching & LAN HDTV Multimedia PC Advanced Desktop PC and Workstation Automotive Applications/GPS DVD Player Set-Top Box Internet Game Consoles Smart Cards/Kiosks Smart Appliance-Phone Digital Camera 40%45%50%55% 40% 45% Cellular Phones

19. 2015/9/4System Arch 2008 (Fire Tom Wada)19 Fabrication Process Issues

20. 2015/9/4System Arch 2008 (Fire Tom Wada)20 Ultra Clean Room

21. 2015/9/4System Arch 2008 (Fire Tom Wada)21 Basic LSI process Layer Deposition lithography etching cleaning M1 M2 M3 M4 M5 M6 M7 SEM photo of Logic LSIs

22. 2015/9/4System Arch 2008 (Fire Tom Wada)22 Projection A A A A A A A A A A A A A A A A A A A A A A A A A A Lens Si Wafer Mask Lens Light Source X Y Stage

23. 2015/9/4System Arch 2008 (Fire Tom Wada)23 Wafer Test scribing Chips Mounting Bonding Enclosing marking Final Test I Burn-In Ex.)Vcc:7V ， Temp.:125 ℃, 24 ～ 42hrs Remove Process defect Chips Functional Test ， DC Test Assembly Flow Shipping Test Final Test II Packaging & Test Sample Wafer Functional Test ， DC/AC Test Functional Test(at Speed) ， DC/AC Test Pre Test Testing

24. 2015/9/4System Arch 2008 (Fire Tom Wada)24 Large Scale Integration NMOS, PMOS and Wiring All Logic Function can be made Memory Element Can be made Billions of Transistors and wiring make LSI!

25. 2015/9/4System Arch 2008 (Fire Tom Wada)25 CMOS NOT (Inverter)

26. 2015/9/4System Arch 2008 (Fire Tom Wada)26 CMOS NAND と NOR ABf 001 011 101 110 ABf 001 010 100 110

27. 2015/9/4System Arch 2008 (Fire Tom Wada)27 Classification Of LSI 1. Logic LSI: Micro Processor, Digital Signal Processor (DSP), FPGA 2. Memory LSI: RAM (DRAM, SRAM), ROM (Flash Memory) 3. Analog LSI: ADC, DAC, Filter, Amplifier Micro Processor (PC ’ s central processing Unit) Perform Digital computation according to the program in Memory Integration in 7000 times in 25 years, (Moor ’ s Law) Clock Speed : 700 times in 25 years Memory LSI: Dynamic Random Access Memory: Main memory for Computer, 4-times density in 4 years Static Random Access Memory : work memory for mobile equipments Flash Memory : Nonvolatile memory, Digital Camera Storage Analog LSI: Used for interface, high speed RF interface, Analog to Digital Conversion, Digital to Analog Conversion

28. 2015/9/4System Arch 2008 (Fire Tom Wada)28 Analog to Digital Conversion ADC LSI Analog to Digital Sample the analog wave Convert to Digital format in Binary Same as f(t) to An Continuous time Discrete time

29. 2015/9/4System Arch 2008 (Fire Tom Wada)29 SoCFlash Memory Chip photo