1. Digital Integrated Circuits© Prentice Hall 1995 Introduction The Devices

2. Digital Integrated Circuits© Prentice Hall 1995 Introduction The Diode n p p n BA SiO 2 Al A B A B Cross-section of pn-junction in an IC process One-dimensional representationdiode symbol

3. Digital Integrated Circuits© Prentice Hall 1995 Introduction Depletion Region

4. Digital Integrated Circuits© Prentice Hall 1995 Introduction Diode Current

5. Digital Integrated Circuits© Prentice Hall 1995 Introduction Forward Bias

6. Digital Integrated Circuits© Prentice Hall 1995 Introduction Reverse Bias

7. Digital Integrated Circuits© Prentice Hall 1995 Introduction SPICE Parameters

8. Digital Integrated Circuits© Prentice Hall 1995 Introduction

9. Digital Integrated Circuits© Prentice Hall 1995 Introduction Two Terminal MOS Structure

10. Digital Integrated Circuits© Prentice Hall 1995 Introduction nMOS Transistor - Structure

11. Digital Integrated Circuits© Prentice Hall 1995 Introduction The MOS Transistor

12. Digital Integrated Circuits© Prentice Hall 1995 Introduction Carriers and Current l Carriers always flow from the Source to Drain l NMOS: Free electrons move from Source to Drain.  Current direction is from Drain to Source. PMOS: Free holes move from Source to Drain.  Current direction is from Source to Drain.

13. Digital Integrated Circuits© Prentice Hall 1995 Introduction IGFET l The dimension of SiO2 layer is about 0.02 to 0.1 micron. l Gate is isolated thus Insulated-Gate FET l Due to insulation the current flowing through the gate terminal is extremely small of the order of 10^-15 A. l Drain is always kept as more positive than the source. l The current flows from the Drain to Source l P-n junctions are kept under the reverse bias conditions l Typically the Length of the device is from 1 to 10 micron.

14. Digital Integrated Circuits© Prentice Hall 1995 Introduction MOS Transistor structure  Polysilicon –Heavily doped noncrystalline silicon.  Polysilicon allows the dimensions of the transistor to be realized accurately.  Gate Oxide – Silicon dioxide.  Thickness of gate oxide – 7 to 20nm.  No d.c. through gate.  Normally, p substrate is connected to 0V in digital circuits and to negative voltage in analog circuits.

15. Digital Integrated Circuits© Prentice Hall 1995 Introduction Symmetry The transistor is symmetric: The Drain (which is equivalent to a BJT’s Collector) and the Source (which is equivalent to a BJT’s Emitter) are fully symmetric and therefore interchangeable

16. Digital Integrated Circuits© Prentice Hall 1995 Introduction All MOS p-n Junctions Unlike a BJT transistor, in which one of the p-n junctions is typically forwardly biased, and the other reversely biased, in a MOSFET all p-n junctions must always be kept reversely biased!

17. Digital Integrated Circuits© Prentice Hall 1995 Introduction The MOSFET Channel l Under certain conditions, a thin channel can be formed right underneath the Silicon- Dioxide insulating layer, electrically connecting the Drain to the Source. The depth of the channel (and hence its resistance) can be controlled by the Gate’s voltage. The length of the channel (shown in the figures above as L) and the channel’s width W, are important design parameters.

18. Digital Integrated Circuits© Prentice Hall 1995 Introduction REGION OF OPERATION CASE-1 (No Gate Voltage) l Two diodes back to back exist in series. l One diode is formed by the pn junction between the n+ drain region and the p-type substrate l Second is formed by the pn junction between the n+ source region and the p-type substrate l These diodes prevent any flow of the current. l There exist a very high resistance.

19. Digital Integrated Circuits© Prentice Hall 1995 Introduction

20. Digital Integrated Circuits© Prentice Hall 1995 Introduction

21. Digital Integrated Circuits© Prentice Hall 1995 Introduction REGION OF OPERATION Creating a channel l Apply some positive voltage on the gate terminal. l This positive voltage pushes the holes downward in the substrate region. l This causes the electrons to accumulate under the gate terminal. l At the same time the positive voltage on the gate also attracts the electrons from the n+ region to accumulate under the gate terminal.

22. Digital Integrated Circuits© Prentice Hall 1995 Introduction

23. Digital Integrated Circuits© Prentice Hall 1995 Introduction

24. Digital Integrated Circuits© Prentice Hall 1995 Introduction

25. Digital Integrated Circuits© Prentice Hall 1995 Introduction REGION OF OPERATION Creating a channel l When sufficient electrons are accumulated under the gate an n-region is created, connecting the drain and the source l This causes the current to flow from the drain to source l The channel is formed by inverting the substrate surface from p to n, thus induced channel is also called as the inversion layer. l The voltage between gate and source called vgs at which there are sufficient electron under the gate to form a conducting channel is called threshold voltage Vth.

26. Digital Integrated Circuits© Prentice Hall 1995 Introduction MOS Channel Formation

27. Digital Integrated Circuits© Prentice Hall 1995 Introduction Current-Voltage Relations

28. Digital Integrated Circuits© Prentice Hall 1995 Introduction MOS Transistor Current direction  The source terminal of an n-channel(p-channel) transistor is defined as whichever of the two terminals has a lower(higher) voltage.  When a transistor is turned ON, current flows from the drain to source in an n-channel device and from source to drain in a p-channel transistor.  In both cases, the actual carriers travel from the source to drain.  The current directions are different because n- channel carriers are negative, whereas p-channel carriers are positive.

29. Digital Integrated Circuits© Prentice Hall 1995 Introduction Threshold Voltage: Concept

30. Digital Integrated Circuits© Prentice Hall 1995 Introduction MOS I/V For a NMOS, a necessary condition for the channel to exist is:

31. Digital Integrated Circuits© Prentice Hall 1995 Introduction REGION OF OPERATION Applying small Vds l Now we applying some small voltage between source and drain say 0.3V. l The voltage Vds causes a current to flow from drain to gate. l Now as we increase the gate voltage, more current will flow. l Increasing the gate voltage above the threshold voltage enhances the channel, hence this mode is called as enhancement mode operation.

32. Digital Integrated Circuits© Prentice Hall 1995 Introduction MOSFET Current-Voltage Relationships The DC gate current is always zero: I G = 0 Therefore, when a channel is created, the drain current equals the source current: I D =I S

33. Digital Integrated Circuits© Prentice Hall 1995 Introduction MOS Transistor - Symbols pMOS TransistornMOS Transistor

34. Digital Integrated Circuits© Prentice Hall 1995 Introduction Operation – nMOS Transistor  Accumulation Mode - If V gs < 0, then an electric field is established across the substrate.  Depletion Mode -If 0<V gs < V tn, the region under gate will be depleted of charges.  Inversion Mode – If V gs > V tn, the region below the gate will be inverted.

35. Digital Integrated Circuits© Prentice Hall 1995 Introduction Operation – nMOS Transistor

36. Digital Integrated Circuits© Prentice Hall 1995 Introduction V =0 Operation – nMOS Transistor

37. Digital Integrated Circuits© Prentice Hall 1995 Introduction Operation – nMOS Transistor

38. Digital Integrated Circuits© Prentice Hall 1995 Introduction Operation – nMOS Transistor

39. Digital Integrated Circuits© Prentice Hall 1995 Introduction Operation – nMOS Transistor

40. Digital Integrated Circuits© Prentice Hall 1995 Introduction Operation – nMOS Transistor