1. EMC of IC models Model of the die : Model of the package :
The model of an IC can be derived from its physical architecture.
It includes the core and package model.
Model of the die :
internal activity (core)
on-chip decoupling
supply network
I/O structure
Core
Core IC
Model of the package :
R,L,C
Transmission line
Package

2. Extraction of internal current waveform
IC model
Model core activity : extract noise source
16 bit
processor
16 MHz
32 bit
processor
500 MHz
Extraction of internal current waveform I I
3 A
100 mA
62.5 ns
time
time
2 ns
1st order assumption : model core activity by triangular waveform current source

3. IC model Model core activity: noise source
Physical Transistor level (Spice)
Huge simulation
Limited to analog blocks
Interpolated Transistor level
Difficult adaptation to usual tools
Limited to 1 M devices
Simple, not limited
Fast & accurate
Gate level Activity (Verilog)
Activity estimation from data sheet
Very simple, not limited
Immediate, not accurate
time (ns)
200
400
600
800
1000
1200 20 40 60 80
100
120
140
Activity
Equivalent
Current generator
Extraction

4. Silicium voltage drop map
IC model
Model core activity: Tool example - PowerSI
Layout
Silicium voltage drop map
PowerSI - Real-time voltage noise simulation (right), including on-chip decoupling capacitors, shows a more stable on-chip power supply © Sigrity
Accurate but high level of complexity

5. Package model Input Buffer I/O specification
(IBIS) – R,L,C for each pin
[Component] Fx45H725
[Manufacturer] Finex
[Package]
| variable typ min max |
R_pkg 800m 500m 950m
L_pkg 6nH 5.5nH 7.5nH
C_pkg 8pF 4pF 10.5pF
[Pin] signal model R_pin L_pin C_pin
1 /1OE in m 7.25nH 10.1pF
2 1Y1 out 1 916m 7.17nH 9.94pF …

6. EMC model example ICEM model Conducted/Radiated emission prediction
dBµV
MHz
Emission spectrum
measurement
simulation
ICEM model

7. Package model with 13 leads
EMC model example
Near-field emission prediction
Scan area
Package model with 13 leads
Simulation of H field at 32 MHz
Measurement of H field at 32 MHz

8. Design issues EMC for Integrated Circuits requires various expertise
High frequency measurement
High frequency modelling
2D, 3D modelling
Electrical modelling
IC design
IC floorplan

9. 6. EMC guidelines

10. Basic concepts to reduce emission and susceptibility
Remember the influent parameters on emission and susceptibility
Emission:
Susceptibility:
Control effect of PCB interconnections (decoupling)
Control effect of IC interconnections (decoupling)
Control Impedance of IC nodes
Reduce non linear effects of active devices
Improve block own susceptibility
Control IC internal activity
Minimize circuit output load
Control effect of IC interconnections (decoupling)
Control effect of PCB interconnections (decoupling)
Techniques used to reduce emission and/or susceptibility issues are based on these principles

11. Golden Rules for Low Emission
Rule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
Inductance is a major source of resonance
Each conductor acts as an inductance
Ground plane modifies inductance value (worst case is far from ground)
Reducing inductance decreases voltage bounce !!
Lead: L=0.6nH/mm
Bonding: L=1nH/mm

12. Golden Rules for Low Emission
Rule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
Leadframe package:
L up to 10nH
Die of the IC
bonding
Long leads
Far from ground
PCB
Flip chip package:
L up to 3nH
Short leads
Die of the IC
balls
Close from ground
Requirements for high speed microprocessors : L < 50 pH !

13. Golden Rules for Low Emission
Rule 1: Power supply routing strategy
B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs
Correct
Fail
9 I/O ports

14. Golden Rules for Low Emission
Rule 1: Power supply routing strategy
C) Place supply pairs close to noisy blocks
Layout view
Current density simulation
Memory
PLL
Digital core
VDD / VSS
The good solution consists in the placement of VDD/VSS pad pairs. VDD/VSS rails should also be routed as close as possible. This increases decoupling capacitance. Also, multiple pairs significantly reduce the internal loops.

15. Golden Rules for Low Emission
Rule 1: Power supply routing strategy
D) Place VSS and VDD pins as close as possible
Current loop
EM field
to increase decoupling capacitance that reduces fluctuations
to reduce current loops that provoke magnetic field
Added contributions
Reduced contributions
Die
Lead
current
EM wave
The second important rule consists is placing VDD and VSS supply as close as possible from each others. This reduces the surface of the current loop which provokes immediate parasitic emission, in radiated mode.
A very bad pin assignment consists in one VDD supply on one side, one VSS supply on the other side. This lead to a maximum emitted parasitic energy.
Consequently, the current wires placed together almost cancel the magnetic field and significantly reduce the radiated signature of the IC. Gains higher than 20dB have been observed in TEM cell measurements.
currents

16. Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 1:
Case 1 : Infineon Tricore
Case 2 : virtex II
Worst case
not enough supply pairs,
bad distribution & dissymmetry
Not ideal
Not enough supply for IOs :
(core emission is lower than IO one)

17. Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 2:
2 FPGA , same power supply, same IO drive, same characteristics
Supply strategy very different !
More Supply pairs for IOs
Better distribution
courtesy of Dr. Howard Johnson, "BGA Crosstalk",

18. Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 2:
Case 1: low emission due to a large number of supply pairs well distributed
Case 2: higher emission level (5 times higher)
courtesy of Dr. Howard Johnson, "BGA Crosstalk",

19. Golden Rules for Low Emission
Rule 2: Add decoupling capacitor
Customer’s specification
Keep the current flow internal
Local energy tank
Reduce power supply voltage drops
Parasitic emission (dBµV) 80
Volt
No decoupling
10 – 15 dB 70 60
nF decoupling
time 50
time 40
Efficient on one decade 30 20
Internal voltage drop 10
-10
The most popular and efficient solution !!! 1 10
100
1000
Frequency (MHz)

20. Golden Rules for Low Emission
Rule 2: Add decoupling capacitor on power distribution network
Power supply
Electrolytic bulk capacitor
HF ceramic capacitor
On chip interconnections
PCB planes
Voltage regulator
Ferrite bead
Vdd
Vss
Ground
1 µF – 10 mF
100 nF – 1 nF
DC – 1 KHz
1 KHz – 1 MHz
1 MHz – 100 MHz
> 100 MHz
Z Vdd - Vss
Power distribution network design :
Target impedance Zt (0.25 mΩ)
Freq range
Frequency

21. Golden Rules for Low Emission
Rule 2: Add decoupling on-chip capacitor
Very high efficient decoupling above 100 MHz (where PCB decoupling capacitors become inefficient) …
… But space consuming
Fill white space with decap cells
Use MOS capa. or Metal-Insulator-Metal (MIM) capa.
Intrinsic on-chip supply capacitance
100nF
65nm
90nm
10nF
0.18µm
0.35µm
1.0nF
100pF
Devices on chip
10pF
Example: in 65nm technology, for a 200 Million devices on chip the intrinsic capacitance is 10nF
100K 1M
10M
100M 1G
On chip decoupling capacitance versus technology and complexity
Capa cell for local decoupling

22. Golden Rules for Low Emission
Rule 3: Reduce core noise
Reduce operating supply voltage
Reduce operating frequency
Reduce peak current by optimizing IC activity, using distributed clock buffers, turning off unused circuitry, avoiding large loads, creating several operation mode

23. Golden Rules for Low Emission
Rule 3: Reduce core noise
Add a controlled jitter on clock signal to spread the noise spectrum
Clock in
Clock out
T+/-Δt
Spread spectrum frequency modulation T
Pseudorandom noise f P
+/-Δf
+/-Δf
1/T
specification f

24. Golden Rules for Low Emission
Rule 3: Reduce core noise
Asynchronous design spreads noise on all spectrum (10 dBµV reduction)
data
data
request
acknowledgment
clock
Synchronous block
Asynchronous block
1/T
specification f

25. Golden Rules for Low Emission
Rule 4: Reduce I/O noise
Minimize the number of simultaneous switching lines (bus coding)
Reduce di/dt of I/O by controlling slew rate and drive
Tr1
Tr2 SR
Emission level f
1/Tr2
1/Tr1

26. Golden Rules for Low Susceptibility
Rule 1: Add decoupling capacitance
Immunity level
(dBm)
DPI aggression of a digital core
Reuse of low emission design rules for susceptibility
Efficiency of on-chip decoupling combined with resistive supply path
Decoupling capacitance
Substrate isolation
No rules to reduce susceptibility
Work done at Eseo France
(Ali ALAELDINE)
Frequency

27. Golden Rules for Low Susceptibility
Rule 2: Isolate Noisy blocks
Analog
Standard cells
Noisy blocks
Far from noisy blocks
Bulk isolation
Separate supply
Why ?
To reduce the propagation of switching noise inside the chip
To reduce the disturbance of sensitive blocks by noisy blocks (auto-susceptibility)
How ?
by separate voltage supply
by substrate isolation
by increasing separation between sensitive blocks
By reducing crosstalk and parasitic coupling at package level

28. Golden Rules for Low Susceptibility
Rule 3: Reduce desynchronisation issues
Synchronous design are sensitive to propagation delay variations due to jitter (dynamic errors)
Improve delay margin to reduce desynchronization failures in synchronous design
Asynchronous logic design is less sensitive to delay compared to synchronous design
15 dB
Work done at INSA Toulouse/TIMA Grenoble
(Fraiddy BOUESSE)

29. Golden Rules for Low Susceptibility
Rule 4: Improve noise immunity of IOs
Add Schmitt trigger on digital input buffer
Use differential structures for digital IO to reject common mode noise (as Low Voltage Differential Signaling I/Os)
2 dB
Schmitt trigger

31. Case study
StarChip #1
Your definitive solution for embedded electronics,16 bit MPU with 16 MHz external quartz,
on-chip PLL providing internal 133MHz operating clock.
128Kb RAM, 3 general purpose ports (A,B,C, 8bits)
4 analog inputs 12 bits, CAN interface
Emission
Susceptible
SIGNAL
Description
VDD
Positive supply
VSS
Logic Ground
VDD_OSC
Oscillator supply
VSS_OSC
Oscillator ground
PA[0..7]
Data port A (programmable drive)
PB[0..7]
Data port B (programmable drive)
PC[0..7]
Data port C (programmable drive) external 66MHz data/address
ADC In [0..3]
4 analog inputs (12 bit resolution)
CAN Tx
CAN interface (high power, 1MHz)
CAN Rx
XTL_1, XTL_2
Quartz oscillator 16MHz
CAPA
PLL external capacitance
RESET
Reset microcontroller

32. Case study
StarChip #1
Initial floorplan

33. Case study
StarChip #1
Your floorplan

34. 7. Conclusion / Future of EMC

35. Future of EMC Scaling leads to an increase of transient currents
90 nm
65 nm
45 nm 50
100
150
200
250
300
Total Peak Current (A)
Technology
32 nm
25 nm
350
400

36. Future of EMC
Towards complex systems, system on chip, system on package
Critical frequency bands
Emission dBµV
100
New frequency band
(1-10GHz) 20 40 60 80
System on chip
32 bits
16 bits
10MHz
100MHz
1GHz
10GHz
Frequency

37. Noise margin or static margin
Future of EMC
Less noise margin
Supply voltage
10V
External voltage
90nm
0.25m 1V
45nm
32nm
0.18m
0.13m
22 nm
18 nm
65nm
Internal voltage
Noise margin or static margin
0.1V
Year
1995
2000
2005
2010
2015

38. Immunity suddenly decreases? Immunity increases with Freq
Future of EMC
Susceptibility trends vs frequency
Immunity suddenly decreases?
Immunity increases with Freq
Barber, Herke, IEE Electromagnetic Hazard, 1994

39. Future of EMC Most of EMC measurement methods are limited to 1 GHz
IEC
(TEM : 1GHz)
IEC /6
(Near field scan, 5GHz)
IEC
(1/150 ohm, 1 GHz)
IEC
(BCI, 1 GHz)
IEC
(WBFC, 1 GHz)
IEC
(Mode Stirred Chamber: 18 GHz)
(GTEM 18 GHz)
IEC
(DPI, 1 GHz)
How characterizing accurately emission and susceptibility of ICs up to 10 GHz?

40. Future of EMC System-In-Package Models become more and more complex
Circuits more complex (System-on-chip, System-in-package)
Power distribution networks become larger, more and more IOs
More and more parasitic coupling paths (substrate coupling, package coupling)
Modeling at high frequency ? How ensure accuracy and efficiency ?
Radiation
Chip stacking
Passive devices
Flip-chip
System-In-Package
Crosstalk via
Vdd
resonance
Vss
Substrate

41. Future of EMC Developing new design guidelines
Customers requirements are more and more constraining
Off-chip decoupling capacitor are limited to several hundred MHz
New technologies require less and less power distribution network impedance
Need of efficient techniques to reduce emission and improve immunity
Electromagnetic bandgap
Active noise cancellation
High density MOS capacitance

42. Conclusion
With technology scale down, ICs become more sensitive and emissive.
EMC of ICs has become a major concerns for ICs suppliers
Standardization groups are working on EMC characterization method (need to address high frequency)
Needs for simulation models and tools to predict ICs EMC performances before fabrication
New EMC oriented design rules and techniques have to be developed to ensure future ICs EMC compliance