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Semiconductor Processing (front-end) Stuart Muter 617.371.3853 smuter@ahh.com 12/02/2002
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2 Semiconductor Processing Agenda: An overview of the key steps in semi- conductor processing (how to make one of Stuart’s wafers). A lot of information is in the packet, we will not be able to cover it all.
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3 Section AIntroduction to Semiconductor Manufacturing Section BKey Processing Steps - Deposition - Etch - Lithography - Doping and Anneal - CMP Section CFuture Trends Table of Contents
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SECTION A: Introduction to Semiconductor Manufacturing
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5 Deposition - CVD - PVD - Oxidation Etch Lithography Doping and Anneal - Diffusion - Ion Implant - RTP CMP Front End Processing Key Steps
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6 Moore’s Law Source: www.intel.com Wafer Sizes Source: Design News Transistor density doubles every 2 years
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7 IC Feature Size Trends
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8 0.13 micron critical dimension (human hair diameter is approx. 100 microns). 7 metal layers 25 mask steps 300 - 400 process steps State of the Art Semi Device
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9 300mm wafers $2-3 billion cost wafer cycle time: 30 -80 days WIP: 20 - 40K wafers Full material automation Cleanroom: Class 10 or 100 Mini-environment: Class 0.1 State of the Art Fab
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10 Market Segmentation Semi and Semi-Equipment Industries Worldwide Semiconductor Market Source: WSTS 11/01
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11 Wafer Fab Equipment Spending Semi-Equipment Industries WFE Revenue Forecast by Equipment Segment ($ Millions) Source: Gartner Dataquest (July 2002)
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12 Device Manufacturing Fab0.5µ CMOS Process Flow
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13 Integrated Circuit Manufacturing Process The “big picture” process
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SECTION B: Key Processing Steps
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15 Typically PVD or MCVD Blanket Metal Deposition
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16 Preferred conductor deposition technology Barrier and seed layer for Cu DC/RF magnetron sputtering Conductors: - Al (interconnect), Ti, TiN, TiW (barrier and ARC), W (vias), Cu Physical Vapor Deposition
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