1. ECE668.1 Csaba Andras Moritz UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Computer Architecture ECE 668 Review of MMU and Virtual Memory

2. ECE668.2 Background  Program must be brought into memory and placed within a process for it to be run. Assume (for the time being) that the program must fit in memory or the program itself needs to deal with when not. This is different from virtual memory (will be covering later) when this problem (i.e. fit or not in memory) will be managed by the OS!  User programs go through several steps before being run. Let us review these steps….

3. ECE668.3 Logical vs. Physical Address Space  The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.  Logical address – generated by the CPU; also referred to as virtual address.  Physical address – address seen by the memory unit.

4. ECE668.4 Memory-Management Unit ( MMU )  Hardware device that maps virtual address to physical address.  In a simple MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory.  There are many different methods for accomplishing such a mapping, as we will see later.  The user program deals with logical addresses; it never sees the real physical addresses.

5. ECE668.5 Dynamic relocation using a relocation register

6. ECE668.6 Paging  Logical address space of a process can be non-contiguous; process is allocated physical memory whenever the latter is available.  Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes).  Divide logical memory into blocks of same size called pages.  Keep track of all free frames.  To run a program of size n pages, need to find n free frames and load program.  Set up a page table to translate logical to physical addresses.  Internal fragmentation possible.

7. ECE668.7 Address Translation Scheme  Address generated by CPU is divided into:  Page number (p) – used as an index into a page table which contains base address of each page in physical memory.  Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

8. ECE668.8 Address Translation Architecture

9. ECE668.9 Paging Example

10. ECE668.10 Paging Example Address in physical memory of 32 bytes Frame size of 4 bytes Address in logical memory Page size of 4 bytes

11. ECE668.11 Free Frames Before allocation After allocation

12. ECE668.12 Implementation of Page Table  Page table is kept in main memory.  Page-table base register (PTBR) points to the page table.  Page-table length register (PRLR) indicates size of the page table.  In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction!  The two memory access problem can be solved by the use of a special fast-lookup hardware cache called translation look-aside buffers (TLBs)

13. ECE668.13 Paging Hardware With TLB

14. ECE668.14 Memory Protection  Memory protection implemented by associating protection bit (called valid bit) with each frame.  Valid-invalid bit attached to each entry in the page table:  “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page.  “invalid” indicates that the page is not in the process’ logical address space.

15. ECE668.15 Valid (v) or Invalid (i) Bit In A Page Table

16. ECE668.16 Page Table Structure  Hierarchical Paging  Hashed Page Tables  Inverted Page Tables

17. ECE668.17 Two-Level Paging Example  A logical address (on 32-bit machine with 4K page size) is divided into:  a page number consisting of 20 bits.  a page offset consisting of 12 bits.  Since the page table is paged, the page number is further divided into:  a 10-bit page number.  a 10-bit page offset.  Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table. page number page offset pipi p2p2 d 10 12

18. ECE668.18 Two-Level Page-Table Scheme

19. ECE668.19 Address-Translation Scheme  Address-translation scheme for a two-level 32-bit paging architecture

20. ECE668.20 Hashed Page Tables  Common in address spaces > 32 bits.  The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.  Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

21. ECE668.21 Hashed Page Table

22. ECE668.22 Inverted Page Table  One entry for each real page of memory.  Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page.  Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs.  Use hash table to limit the search to one — or at most a few — page-table entries.

23. ECE668.23 Inverted Page Table Architecture

24. ECE668.24 Segmentation  Memory-management scheme that supports user view of memory.  A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays

25. ECE668.25 User’s View of a Program

26. ECE668.26 Logical View of Segmentation 1 3 2 4 1 4 2 3 user spacephysical memory space

27. ECE668.27 Segmentation Architecture  Logical address consists of a two tuple:,  Segment table – maps two-dimensional physical addresses; each table entry has:  base – contains the starting physical address where the segments reside in memory.  limit – specifies the length of the segment.  Segment-table base register (STBR) points to the segment table’s location in memory.  Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR.

28. ECE668.28 Segmentation Architecture (Cont.)  Relocation.  dynamic  by segment table  Sharing.  shared segments  same segment number  Allocation.  first fit/best fit  external fragmentation

29. ECE668.29 Segmentation Architecture (Cont.)  Protection. With each entry in segment table associate:  validation bit = 0  illegal segment  read/write/execute privileges  Protection bits associated with segments; code sharing occurs at segment level.  Since segments vary in length, memory allocation is a dynamic storage-allocation problem.  A segmentation example is shown in the following diagram

30. ECE668.30 Segmentation Hardware

31. ECE668.31 Example of Segmentation

32. ECE668.32 Sharing of Segments

33. ECE668.33 Segmentation with Paging – MULTICS  The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments.  Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment, but rather the base address of a page table for this segment.

34. ECE668.34 MULTICS Address Translation Scheme

35. ECE668.35 Segmentation with Paging – Intel 386  As shown in the following diagram, the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.

36. ECE668.36 Intel 30386 Address Translation

37. ECE668.37 Virtual Memory - Background  Virtual memory – separation of user logical memory from physical memory (even size does not need to match).  Only part of the program needs to be in memory for execution.  Logical address space can therefore be much larger than physical address space.  Allows address spaces to be shared by several processes.  Allows for more efficient process creation.  Virtual memory can be implemented via:  Demand paging  Demand segmentation

38. ECE668.38 Virtual Memory That is Larger Than Physical Memory

39. ECE668.39 Demand Paging  Bring a page into memory only when it is needed.  Less I/O needed  Less memory needed  Faster response  More users  Page is needed  reference to it  invalid reference  abort  not-in-memory  bring to memory

40. ECE668.40 Transfer of a Paged Memory to Contiguous Disk Space

41. ECE668.41 Valid-Invalid Bit  With each page table entry a valid–invalid bit is associated (1  in-memory, 0  not-in-memory)  Initially valid–invalid bit is set to 0 on all entries.  Example of a page table snapshot.  During address translation, if valid–invalid bit in page table entry is 0  page fault. 1 1 1 1 0 0 0 Frame #valid-invalid bit page table

42. ECE668.42 Page Table When Some Pages Are Not in Main Memory

43. ECE668.43 Page Fault  If there is ever a reference to a page, first reference will trap to OS  page fault (BDW can we get a page fault in a non-demand based paging environment?)  OS looks at another table to decide if what happened is an:  Invalid reference  abort.  Or page just not in memory.  What happens during a fault?  Get empty frame.  Swap page into frame.  Reset tables, validation bit = 1.  Restart instruction: Least Recently Used  But what happens during a block move instruction –(e.g., in PDP11 was such an instruction)? Page fault in the middle of transfer… things get complicated as some memory locations are already changed.

44. ECE668.44 Steps in Handling a Page Fault

45. ECE668.45 What happens if there is no free frame?  Page replacement – find some page in memory, but not really in use, swap it out.  algorithm  performance – want an algorithm which will result in minimum number of page faults.  Same page may be brought into memory several times.

46. ECE668.46 Architectural Support for VM From Jacob et al Micro 2005 paper

47. ECE668.47 MIPS R10000

48. ECE668.48 Alpha 21164

49. ECE668.49 Power PC604

50. ECE668.50 PA-RISC

51. ECE668.51 Ultra Sparc I

52. ECE668.52 Pentium II

53. ECE668.53 Backup Slides

54. ECE668.54 Performance of Demand Paging  Page Fault Rate 0  p  1.0  if p = 0 no page faults  if p = 1, every reference is a fault  Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + swap page out + swap page in + restart overhead) Page Fault Service time

55. ECE668.55 Demand Paging Example  Memory access time = 100 nsec = 0.1usec  Page fault service time = 25 msec = 25,000usec EAT (usec) = (1 – p) x 0.1 + p (25,000)  Assuming we have p=0.1 (10% of the case page fault)  EAT(usec) = 0.9 x 0.1 + 0.1* 25,000 ~2500usec=2.5msec

56. ECE668.56 Page Replacement  Prevent over-allocation of memory by modifying page-fault service routine to include page replacement.  Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk.  Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.

57. ECE668.57 Need For Page Replacement

58. ECE668.58 Basic Page Replacement 1.Find the location of the desired page on disk. 2.Find a free frame: - If there is a free frame, use it. - If there is no free frame, use a page replacement algorithm to select a victim frame. 3.Read the desired page into the (newly) free frame. Update the page and frame tables. 4.Restart the process.

59. ECE668.59 Page Replacement

60. ECE668.60 Page Replacement Algorithms  Want lowest page-fault rate.  Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string.  In all our examples, the reference string is 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5.

61. ECE668.61 Graph of Page Faults Versus The Number of Frames

62. ECE668.62 First-In-First-Out (FIFO) Algorithm  Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5  3 frames (3 pages can be in memory at a time per process)  4 frames  FIFO Replacement – Belady’s Anomaly  more frames  less page faults? 1 2 3 1 2 3 4 1 2 5 3 4 9 page faults 1 2 3 1 2 3 5 1 2 4 5 10 page faults 4 43

63. ECE668.63 FIFO Page Replacement

64. ECE668.64 FIFO Illustrating Belady’s Anomaly

65. ECE668.65 Optimal Algorithm  Replace page that will not be used for longest period of time.  4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5  How do you know this?  Used for measuring how well your algorithm performs. 1 2 3 4 6 page faults 4 5

66. ECE668.66 Optimal Page Replacement

67. ECE668.67 Least Recently Used (LRU) Algorithm  Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5  Counter implementation  Every page entry has a counter; every time page is referenced through this entry, copy the clock into the counter.  When a page needs to be changed, look at the counters to determine which are to change. 1 2 3 5 4 4 3 5

68. ECE668.68 LRU Page Replacement

69. ECE668.69 LRU Algorithm (Cont.)  Stack implementation – keep a stack of page numbers in a double link form:  Page referenced: »move it to the top »requires 6 pointers to be changed  No search for replacement

70. ECE668.70 Use Of A Stack to Record The Most Recent Page References

71. ECE668.71 LRU Approximation Algorithms  Reference bit  With each page associate a bit, initially = 0  When page is referenced bit set to 1.  Replace the one which is 0 (if one exists). We do not know the order, however.  Second chance  Need reference bit.  Clock replacement.  If page to be replaced (in clock order) has reference bit = 1. then: »set reference bit 0. »leave page in memory. »replace next page (in clock order), subject to same rules.

72. ECE668.72 Second-Chance (clock) Page-Replacement Algorithm

73. ECE668.73 Counting Algorithms  Idea:  Keep a counter of the number of references that have been made to each page.  LFU (Least Frequently Used) Algorithm: replaces page with smallest count.  Argument is that an actively used bae should have a large reference count  MFU (Most Frequently Used) Algorithm: replaces page with the largest count  based on the argument that the page with the smallest count was probably just brought in and has yet to be used.

74. ECE668.74 Allocation of Frames  How are we allocating the frames to multiple processes? (For example, simplest is to partition memory equally between processes, but are there any constraints that prevent us doing this….?)  Each process needs minimum number of pages.  Example: IBM 370 – 6 pages to handle SS MOVE instruction: »instruction is 6 bytes, might span 2 pages. »2 pages to handle from. »2 pages to handle to.  Two major allocation schemes in general.  fixed allocation (equal or proportional)  priority allocation (use priorities)

75. ECE668.75 Fixed Allocation  Equal allocation – e.g., if 100 frames and 5 processes, give each 20 pages.  Proportional allocation – Allocate according to the size of process.

76. ECE668.76 Priority Allocation  Use a proportional allocation scheme using priorities rather than size.  If process P i generates a page fault,  select for replacement one of its frames.  select for replacement a frame from a process with lower priority number.

77. ECE668.77 Global vs. Local Allocation  Global replacement –  process selects a replacement frame from the set of all frames; one process can take a frame from another.  Local replacement –  each process selects from only its own set of allocated frames.

78. ECE668.78 Thrashing  If a process does not have “enough” pages, the page-fault rate is very high. This leads to:  low CPU utilization.  operating system thinks that it needs to increase the degree of multiprogramming.  another process added to the system.   Thrashing  a process is busy swapping pages in and out. 

79. ECE668.79 Thrashing  Why does paging work? Locality model  Process migrates from one locality to another.  Localities may overlap.  Why does thrashing occur?  size of locality > total memory size

80. ECE668.80 Locality In A Memory-Reference Pattern

81. ECE668.81 Working-Set Model   working-set window  a fixed number of page references Example: 10,000 instruction  WSS i (working set of Process P i ) = total number of pages referenced in the most recent  (varies in time)  if  too small will not encompass entire locality.  if  too large will encompass several localities.  if  =   will encompass entire program.  D =  WSS i  total demand frames  if D > m  Thrashing  Policy if D > m, then suspend one of the processes.

82. ECE668.82 Working-set model

83. ECE668.83 Keeping Track of the Working Set  Approximate with interval timer + a reference bit  Example:  = 10,000  Timer interrupts after every 5000 time units.  Keep in memory 2 bits for each page.  Whenever a timer interrupts copy and sets the values of all reference bits to 0.  If one of the bits in memory = 1  page in working set.  Why is this not completely accurate?  Improvement = 10 bits and interrupt every 1000 time units.

84. ECE668.84 Page-Fault Frequency Scheme  Establish “acceptable” page-fault rate.  If actual rate too low, process loses frame.  If actual rate too high, process gains frame.

85. ECE668.85 Other Considerations  Prepaging  Page size selection  fragmentation  table size  I/O overhead  locality

86. ECE668.86 Other Considerations (Cont.)  TLB Reach - The amount of memory accessible from the TLB.  TLB Reach = (TLB Size) X (Page Size)  Ideally, the working set of each process is stored in the TLB. Otherwise there is a high degree of page faults.

87. ECE668.87 Increasing the Size of the TLB  Increase the Page Size. This may lead to an increase in fragmentation as not all applications require a large page size.  Provide Multiple Page Sizes. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation.

88. ECE668.88 Other Considerations (Cont.)  Program structure  int A[][] = new int[1024][1024];  Each row is stored in one page  Program 1 for (j = 0; j < A.length; j++) for (i = 0; i < A.length; i++) A[i,j] = 0; 1024 x 1024 page faults  Program 2 for (i = 0; i < A.length; i++) for (j = 0; j < A.length; j++) A[i,j] = 0; 1024 page faults