1. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.

2. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR MOSFET gate as capacitor Basic structure of gate is parallel-plate capacitor: (A good reference on this is www4.ncsu.edu:8030/~vmisra/MOS.ppt and physics of MOSFET is http://ece-www.colorado.edu/~bart/book/book/chapter2/ch2_6.htm ) gate substrate SiO 2 x ox VgVg + - ++++++++++++ ------------ inversion

3. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR MOS as a parallel plate capacitance n Formula for parallel plate capacitance/unit area: C ox =  ox / x ox, where x ox is the thickness of the SO 2 in cm, and  ox is its permittivity:  ox = 3.46 x 10 -13 F/cm n Gate to substrate capacitance helps determine the characteristics of a channel which forms an inversion region (region devoid of dopant carriers in the substrate) between the source and drain of a MOS transistor. In particular, it plays a critical role in the determination of the threshold voltage of a MOS transistor.

4. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Threshold voltage The threshold voltage, V t0, when the source to substrate voltage is 0. V t0 = V fb +  s + Q b /C ox + V II Components of V t0 are: n V fb = flatband voltage between gate and substrate, i.e., the work function difference between gate and substrate. The work function is the energy required to remove an electron from the Fermi energy to the vacuum level.  s is the surface potential which is equal to twice the Fermi potential where n i is the intrinsic carrier (electron or hole) concentration of the substrate, kT/q is the thermal voltage, and N a is the hole concentration in the substrate. n Q b /C ox is the voltage across the capacitor, where, q is the charge of an electron,  si is the permittivity of silicon, n V II is the voltage adjustment = qD I /C ox, where D I is the ion implantation concentration (body effect)

5. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Threshold voltage n The flat-band voltage between gate and substrate depends on the difference in the work function between gate and substrate (  gs ) and on fixed surface charge (Q f ): n assuming that the gate is doped with n-type carriers with the concentration of N dp n When the source to substrate voltage is not 0 then the threshold voltage is shifted by a differential voltage, called the body effect:

6. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Body effect n Reorganize threshold voltage equation: V t = V t0 +  V t n Threshold voltage is a function of source/substrate voltage V sb. Body effect  is the coefficient for the V sb dependence factor. n (I am skipping this slide as it is replicated in my changes)

7. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Example 2-3 (pp-56-57): Threshold voltage of a transistor V t0 = V fb +  s + Q b /C ox + V II = -0.91 V + 0.58 V + (1.4E-8/1.73E-7) + 0.92 V = 0.68 V Body effect  n = sqrt(2q  Si N A /C ox ) = 0.1  V t =  n [sqrt(  s + V sb ) - sqrt(V s )] = 0.16 V

8. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Example 2-3 (pp-56-57): Threshold voltage of a transistor

9. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR More device parameters Process transconductance k’ =  C ox. (  denotes the mobility of channel electrons or holes) Device transconductance  = k’W/L. Saturation Current: I d = 0.5k’ (W/L)(V gs - V t ) 2 = 0.5  (V gs - V t ) 2

10. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Channel length modulation length parameter  describes small dependence of drain current on V ds in saturation. n Factor is measured empirically. n New drain current equation: –I d = 0.5k’ (W/L)(V gs - V t ) 2 (l  -  V ds ) n Equation has a discontinuity between linear and saturation regions---small enough to be ignored. Note: I use  instead of  to avoid confusion with channel parameter 

11. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Gate voltage and the channel gate drainsource current IdId V ds < V gs - V t V gs > V ds + V t gate drainsource current IdId gate drainsource IdId V ds = V gs - V t V gs = V ds + V t V ds > V gs - V t V gs < V ds + V t Linear region Saturation region Inversion layer current Pinch off dI d /dV ds decreases Channel transconductance decreases Inversion layer shrinks

12. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Leakage and subthreshold current n A variety of leakage currents draw current away from the main logic path. n The sub-threshold current is one particularly important type of leakage current. n (When the gate voltage is just below the threshold voltage, the point of weak- inversion)

13. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Types of leakage current. n Weak inversion current (sub-threshold current). n Punch-through currents. (When the drain to source voltage gets to be too high, the source and drain regions may be shorted.) n Gate oxide tunneling-- Hot carriers (For short channels, electrons may accumulate into the gate oxide, leading to changes in threshold conditions. ) n Reverse-biased pn junctions n Drain-induced barrier lowering (Shift in threshold level to increase in drain voltage-- higher current flow near cut-off when the drain voltage increases) n Gate-induced drain leakage (As gate oxide layer becomes very thin, channel current may leak into the gate-- non-ideal capacitor)

14. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Subthreshold current Subthreshold current: www4.ncsu.edu:8030/~vmisra/MOS.ppt and physics of MOSFET when V ds >> q/kT S is called the sub-threshhold swing; smaller values of S are desirable

15. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR The modern MOSFET Features of deep submicron MOSFETs: –epitaxial layer for heavily-doped channel; –(both n and p wells over an epitaxial layer) –reduced area source/drain contacts for lower capacitance; –lightly-doped drains to reduce hot electron effects; –silicided poly, diffusion to reduce resistance.

16. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Circuit simulation n Circuit simulators like Spice numerically solve device models and Kirchoff’s laws to determine time-domain circuit behavior. n Numerical solution allows more sophisticated models, non-functional (table- driven) models, etc.

17. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Spice MOSFET models n Level 1: basic transistor equations of Section 2.2; not very accurate. n Level 2: more accurate model (effective channel length, etc.). n Level 3: empirical model. n Level 4 (BSIM): efficient empirical model. n New models: level 28 (BSIM2), level 47 (BSIM3). (BSIM4-July 2005- for submicron MOS simulation--Level 54)

18. Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Some (by no means all) Spice model parameters L, W : transistor length width. KP : transconductance. GAMMA : body bias factor. AS, AD : source/drain areas. CJSW : zero-bias sidewall capacitance. CGBO : zero-bias gate/bulk overlap capacitance.