Cosimo Carriero Analog Dialogue Seminar November 2011

Cosimo Carriero Analog Dialogue Seminar November 2011
A/D and D/A Conversion Cosimo Carriero Analog Dialogue Seminar November 2011

Agenda Fundamentals of sampled data systems
A/D Converters Architectures SAR Sigma-Delta Flash Pipelined D/A Converters Architectures 1 Bit DAC The Kelvin Divider or String DAC Thermometer DAC Binary-Weighted DAC R-2R Ladder DAC Segmented DAC Oversampling Interpolating DAC Multiplying DAC A/D and D/A Converters State of the Art

Imagine a world without ADCs
4/20/2017 Imagine a world without ADCs Digital... ... storage ... display ... manipulation ... communication in other words... ..the Digital World Voltage Current Impedance Time* in other words... ...the Analog World Sound Light intensity Temperature Force pH... in other words... ...the Real World Sensor ADC

Analog vs. Digital Options ... back to the future
4/20/2017 Analog vs. Digital Options ... back to the future Analog Digital Storage (& retrieval !!!) Magnetic tape Chart recorder Hard disk drive Memory Card.. Display Cathode Ray Oscilloscope Moving coil meters Optical indicators Digital Oscilloscope LCD Displays 7-segment display Manipulation Amplifiers Analog Computers Digital Signal Processing Communication 4-20mA loop FM radio transmission Ethernet USB, GSM

Fundamentals of Data Converters
Analog Devices Confidential – © 2008 – Version 1a

Sampled Data System fs fs DSP fa LPF OR BPF N-BIT ADC N-BIT DAC LPF OR
AMPLITUDE QUANTIZATION DISCRETE TIME SAMPLING fa The next part of the seminar concentrates on dynamic aspects of data converters. Discrete Time Sampling and Amplitude Quantization are the two fundamental processes which occur in a typical sampled data system. This shows a "real-time" system, but for data analysis and many signal processing applications, the signal is digitized and never converted back to analog. First we will look at the sampling process. 1 fs Ts= t t Ts 2Ts 3Ts 4Ts 5Ts 6Ts 7Ts

Aliasing in the Time Domain
ALIASED SIGNAL = fs – fa INPUT = fa If a signal is not sampled a rate greater than twice its frequency, aliasing will occur. This shows an analog signal with a frequency of fa sampled at a frequency fs, where fa is slightly less than fs. This clearly violates the Nyquist criteria, and the aliased signal is shown in RED. We are not taking enough samples to reproduce the original signal correctly. The frequency of the alias signal is fs – fa. 1 fs t NOTE: fa IS SLIGHTLY LESS THAN fs

Sampling Theorem If the Fourier Transform of a function f(t) is zero above a certain frequency ωc, F(ω) = 0 for |ω| > ωc, then f(t) can be uniquely determined from its values at a sequence of equidistant points, distance π/ωc, apart. In fact f(t) is given by Back in the 1920s Harry Nyquist wrote a couple of seminal papers on this topic and establish the Nyquist sampling theorem. In essence it states that a signal with a maximum frequency Fa, must be sampled at a rate Fs, which is greater than two times Fa, in order to avoid losing information about that signal due to aliasing. Further the aliasing will occur when ever the sampling rate is less than two times FA. No further extension of this, describes that a band limited signal with frequency components between FA and FB must be sampled at a rate FS > 2 x (FB-FA) in order to prevent alias components from overlapping the signal frequencies. These three criteria, the two accurately sample the signal you must do so with a sampling rate greater than twice the highest frequency of interest, and that failing to do so will result in aliasing, and that you can treat the bands limited signal in the same way, place important constraints on your system. <Next >

Nyquist's Criteria A signal with a maximum frequency fa must be sampled at a rate fs > 2fa or information about the signal will be lost because of aliasing. Aliasing occurs whenever fs < 2fa A signal which has frequency components between fa and fb must be sampled at a rate fs > 2 (fb – fa) in order to prevent alias components from overlapping the signal frequencies The concept of aliasing is widely used in communications applications such as direct IF-to-digital conversion. Back in the 1920s Harry Nyquist wrote a couple of seminal papers on this topic and establish the Nyquist sampling theorem. In essence it states that a signal with a maximum frequency Fa, must be sampled at a rate Fs, which is greater than two times Fa, in order to avoid losing information about that signal due to aliasing. Further the aliasing will occur when ever the sampling rate is less than two times FA. No further extension of this, describes that a band limited signal with frequency components between FA and FB must be sampled at a rate FS > 2 x (FB-FA) in order to prevent alias components from overlapping the signal frequencies. These three criteria, the two accurately sample the signal you must do so with a sampling rate greater than twice the highest frequency of interest, and that failing to do so will result in aliasing, and that you can treat the bands limited signal in the same way, place important constraints on your system. <Next >

Aliasing in the Frequency Domain
fa A I I I I 0.5fs fs 1.5fs 2fs 2.5fs 1st Nyquist Zone 2nd Nyquist Zone 3rd Nyquist Zone 4th Nyquist Zone 5th Nyquist Zone B I fa I I I 0.5fs fs 1.5fs 2fs 2.5fs

Aliasing in the Frequency Domain
fa A 0.5fs fs 1.5fs 2fs 2.5fs 1st Nyquist Zone 2nd Nyquist Zone 3rd Nyquist Zone 4th Nyquist Zone 5th Nyquist Zone B 0.5fs fs 1.5fs 2fs 2.5fs

Oversampling Relaxes Requirements on Baseband Antialiasing Filter
Kfs f - f f a a f s - f a a DR We can make our situation more manageable from a filter perspective, by increasing the sampling rate as is shown in figure B. to the right. Here is an example we call oversampling. Where instead of sampling at the original sampling rate FS, instead we sample at a multiple of FS, KFS, where K. is the oversampling ratio. Now the Nyquist bandwidth is still one half of the actual sampling rate, so the quantization noise, equal to Q. over the square root of 12, uniformly distributes itself over this bandwidth. Since the quantity of noise is the same in both instances, the quantization noise floor is lowered. In fact for every doubling of sampling rate, we can achieve a 3 dB improvement in the SNR. Now in this case are anti-alias filter can be made with a much more relaxed rolloff and depending on the oversampling ratio, may be able to attenuate aliased images to below the level of quantization noise, as shown in figure B. <Next > fs 2 f Kfs 2 Kfs s STOPBAND ATTENUATION = DR TRANSITION BAND: fa to fs - fa CORNER FREQUENCY: fa STOPBAND ATTENUATION = DR TRANSITION BAND: fa to Kfs - fa CORNER FREQUENCY: fa

Quantization: The Size of a Least Significant Bit (LSB)
RESOLUTION N 2-bit 4-bit 6-bit 8-bit 10-bit 12-bit 14-bit 16-bit 18-bit 20-bit 22-bit 24-bit 2N 4 16 64 256 1,024 4,096 16,384 65,536 262,144 1,048,576 4,194,304 16,777,216 VOLTAGE (10V FS) 2.5 V 625 mV 156 mV 39.1 mV 9.77 mV (10 mV) 2.44 mV 610 mV 153 mV 38 mV 9.54 mV (10 mV) 2.38 mV 596 nV* ppm FS 250,000 62,500 15,625 3,906 977 244 61 15 4 1 0.24 0.06 % FS 25 6.25 1.56 0.39 0.098 0.024 0.0061 0.0015 0.0004 0.0001 dB FS – 12 – 24 – 36 – 48 – 60 – 72 – 84 – 96 – 108 – 120 – 132 – 144 It is useful to consider just how small an LSB can become in a high resolution converter. This example uses 10V for fullscale, but most modern ADC use an input range which is less than 5V. The magnitude of an LSB is expressed in voltage, ppm FS, %FS, and dBFS. *600nV is the Johnson Noise in a 10kHz BW of a 2.2kW 25°C Remember: 10-bits and 10V FS yields an LSB of 10mV, 1000ppm, or 0.1%. All other values may be calculated by powers of 2.

Quantization Noise as a Function of Time
Digital output e(t) +q 2 SLOPE = s analog input t q = 1LSB –q 2 error –q 2s +q 2s ERROR = The RMS value of the quantization noise waveform is easily calculated in this slide. The result is q/12. MEAN-SQUARE ERROR = ROOT-MEAN-SQUARE ERROR =

Theoretical Quantization Noise Ideal N-Bit Converter

Quantization Noise Spectrum
SPECTRAL DENSITY q RMS VALUE = q = 1 LSB 12 fs MEASURED OVER DC TO 2 q / 12 fs / 2 This slide shows the increase in theoretical SNR by limiting the measurement bandwidth. The increase is sometimes called "process gain." This is exactly the same thing as oversampling a signal of bandwidth BW. Sqrt(12) =c. 3.46 fs BW 2 f s SNR = 6.02N + 1.76dB + 10log10 FOR FS SINEWAVE 2• BW Process Gain

Quantization: The Size of a Least Significant Bit (LSB)
RESOLUTION N 2-bit 4-bit 6-bit 8-bit 10-bit 12-bit 14-bit 16-bit 18-bit 20-bit 22-bit 24-bit 2N 4 16 64 256 1,024 4,096 16,384 65,536 262,144 1,048,576 4,194,304 16,777,216 VOLTAGE (10V FS) 2.5 V 625 mV 156 mV 39.1 mV 9.77 mV (10 mV) 2.44 mV 610 mV 153 mV 38 mV 9.54 mV (10 mV) 2.38 mV 596 nV* ppm FS 250,000 62,500 15,625 3,906 977 244 61 15 4 1 0.24 0.06 % FS 25 6.25 1.56 0.39 0.098 0.024 0.0061 0.0015 0.0004 0.0001 Ideal SNR dB FS 13.8 25.84 37.88 49.92 61.96 74 86.04 98.08 110.12 122.16 134.2 146.24 It is useful to consider just how small an LSB can become in a high resolution converter. This example uses 10V for fullscale, but most modern ADC use an input range which is less than 5V. The magnitude of an LSB is expressed in voltage, ppm FS, %FS, and dBFS. *600nV is the Johnson Noise in a 10kHz BW of a 2.2kW 25°C Remember: 10-bits and 10V FS yields an LSB of 10mV, 1000ppm, or 0.1%. All other values may be calculated by powers of 2.

Basic ADC and DAC ADC DAC SAMPLING CLOCK VDD VREF
EOC, DATA READY, ETC. ANALOG INPUT ADC DIGITAL OUTPUT VREF (ANALOG INPUT) VDD DAC <Chris> Thanks Rick. Okay so let’s kick right off talking about A/D converters. Here we show a basic A/D with the analog input, voltage reference, sampling clock, digital output lines and the supplies. <Next> VSS GND ANALOG OUTPUT DIGITAL INTPUT VSS GND

Transfer Functions for Ideal 3-Bit DAC and ADC
A DAC puts out a discrete voltage (or current) related to the digital code. The DAC cannot put out voltages between its codes. An ADC converts an analog signal to a digital code – the code is valid for a range of analog inputs.

Static (DC) Errors in Converters
FS FS ACTUAL ACTUAL IDEAL IDEAL OFFSET ERROR GAIN ERROR FS ACTUAL 0.5LSB DNL=-0.5LSB IDEAL LINEARITY ERROR 1.5LSB DNL=+0.5LSB INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

Transfer Functions for Non-Ideal 3-Bit DAC and ADC

Quantifying Data Converter Dynamic Performance
Signal-to-Noise Ratio (SNR) Harmonic Distortion Worst Harmonic Total Harmonic Distortion (THD) Total Harmonic Distortion Plus Noise (THD + N) Signal-to-Noise-and-Distortion Ratio (SINAD) Effective Number of Bits (ENOB) Analog Bandwidth (Full-Power, Small-Signal) Spurious Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion (IMD) Multi-tone Intermodulation Distortion Noise Power Ratio (NPR) Adjacent Channel Leakage Ratio (ACLR) Noise Figure Settling Time, Overvoltage Recovery Time Next we will focus on ADC and DAC dynamic performance issues. Testing techniques for static and dynamic specifications are described in detail in Chapter 5 of the book. As shown in the list, most are frequency-domain specifications which require FFT analysis of the ADC output. Although manufacturers of data converters have generally agreed on standard definitions for these parameters, the rule of RTFDS must still be applied!

Sample-and-Hold Function Required for Digitizing AC Signals
SAMPLING CLOCK TIMING ANALOG INPUT ADC ENCODER N SW CONTROL C ENCODER CONVERTS DURING HOLD TIME Most ADCs today are used to process AC signals, and therefore there must be a sample-and-hold (SHA) function. Many ADCs of the 1970s required external SHAs, but today the function is built in to practically all ADCs. This allows the ADC to be completely specified for DC and AC performance, and the user does not need to worry about interfacing a discrete SHA to a separate ADC (encoder). HOLD SW CONTROL SAMPLE SAMPLE

Input Frequency Limitations of Non-Sampling ADC (Encoder)
ANALOG INPUT N-BIT SAR ADC ENCODER CONVERSION TIME = 8µs N 2N v(t) = q sin (2 f t ) 2 dv dt 2N q 2 f cos (2 f t ) = 2 fs = 100 kSPS dv dt q 2(N–1) 2 f = EXAMPLE: dv = 1 LSB = q dt = 8µs N = 12, 2N = 4096 fmax = 9.7 Hz max dv dt Let’s start looking at the sampling aspect. Let’s consider a simple nonsampling encoder, and apply an analog input to it. What is the highest frequency that we can resolve to within an LSB error given a certain clock? In this example will assume a sampling clock of 100 k samples per second, which gives a sampling interval (dt) of 8 µs. Further will assume a 12 bit device, which therefore has 4096 discrete quantized levels. Working through the math on the left-hand side starting with a sine wave input, we can work out that the maximum frequency that can be applied to the input and still be resolved within one LSB is just 9.7 Hz. This is not very fast given a 100 ksps clock , and speaks to the need to sample the analog input signal. We’ll come back to the implications of this in part two of the seminar. For now will assume are sampling takes place instantaneously. <Next > max fmax = 2(N–1) 2 q dv dt max fmax = q 2N

Aperture Time – Aperture Delay Time

Effective Aperture Delay Time Measured with Respect to ADC Input
+FS ANALOG INPUT ZERO CROSSING SI NE WA VE V -FS This shows how aperture delay time can be measured with respect to the ADC analog input and sampling clock input. Simply offset the sampling clock from the zero-crossing of the sinewave until the ADC output code reads midscale. The difference between the leading edge of the sampling clock and the actual zero crossing of the sinewave input is equal to the aperture delay time. ' – t ' + t e e SAM PL ING CL OC K ' t e

Effects of Aperture Jitter and Sampling Clock Jitter
ADC ADC Analog Input Sampling Clock SNR Digital Output Analog Input Sampling theory requires at least 2x over sampling of desired signal bandwidth SNR performance is a function of input clock jitter and input center frequency Trade off SNR over given signal bandwidth vs clock jitter vs input frequency As mentioned earlier, the Nyquist theorem suggests that for accurate and complete digital representation of an analog signal, the sampling rate must be at least two times the bandwidth of the analog signal. In other words for example a 3G UMTS channel is 3.84MHz wide, so the required minimum sample rate required is 7.6Msps in order to accurately represent the information content within that WBCDMA signal. The sample rate is determined by the *bandwidth* of the information, so if the 3.84MHz signal is centered at 200MHz, then in theory it still would only take a 7.6Msps ADC to digitize this signal. In reality this type of signal is sampled at a rate faster than the Nyquist theorem requires, typically 10 times the required sample rate. This is done to make it easier to design the analog filters and derive the information content (symbols) in the digital domain. The sampling clock for the ADC, which in most cases is the input clock, can directly affect the ADC performance. On the right hand side, you can see the time domain effect of jitter on the input clock and how this uncertainty creates uncertainty in the resulting captured sample of the high speed analog input. There is a direct correlation to the amount of jitter on the input clock of an ADC to the resulting SNR of that ADC for a given input frequency. In the upper left hand side, you can see how different amounts of clock jitter will affect SNR (on the vertical axis) based on the analog input signal frequency (on the horizontal axis). For example, if a signal band of interest is centered at 200MHz, the overall clock jitter performance needs to be in the order of 200fsec (fempto seconds) in order to achieve an SNR of 72dB. As you can see, if the desired input center frequency is lowered, then the input clock jitter requirements can be relaxed. There is a clocking slide that we will highlight later to talk more about this and ADI’s solutions to this jitter challenge. So, we’ve talked about architectures, sample rates, input signal bandwidths and input clocks. All elements in the analog domain for the most part. Now let’s turn our attention the digital domain. (Next slide)

Spurious Free Dynamic Range - SFDR

DAC Settling Time ERROR BAND SETTLING TIME (OUTPUT) t = 0 ERROR BAND
If we take a look at the data output as shown here you can see why the DAC is so complex. As the DAC is required to transition from one level to another, it doesn’t do so instantaneously, nor does it do so precisely. Just as with a amplifier there are slew rate limitations, as well as settling time issues of both length of time, overshoot, and settling that have to be dealt with. So where A/D converter needs to get the sampling rate at one instant, contact needs to get the sampling rate the whole time. This makes the DAC perhaps much more difficult device to make than an ADC. <Next> DEAD SLEW RECOVERY LINEAR TIME TIME TIME SETTLING SETTLING TIME (INPUT TO OUTPUT)

DAC Signal Construction – Glitch Impulse Area
SAMPLED SIGNAL t RECONSTRUCTED SIGNAL 1 fc t IDEAL TRANSITION TRANSITION WITH TRANSITION WITH UNIPOLAR (SKEW) GLITCH DACs may seem simple since their function is basically to take a digital word and output a voltage or current that corresponds uniquely to that word. As we’ll see in part two, there a number of ways of achieving this, but in the end it’s largely a simple voltage passed through a switch. But in that simplicity there is complexity. The top graph shows the A/D converter representation of the sampled signal, whereas the middle graph shows the reconstructed signal at the output of the DAC. You’ll notice a few things – one of the most noticeable is that the output is a staircase. The DAC function, rather than being an impulse, is the zero order hold function. As you can see the output is a bit chunky, that’s not the biggest contributor to performance degradation’s. At the output of the switch will we would like to see is the ideal transition from one voltage level to another as shown in the left-hand bottom graph. But because of the nature of switches, you have to deal with a variety of glitches caused by charge injection among other things. These glitches can cause both harmonics and nonlinearities in the output of the DAC. <Next> DOUBLET GLITCH t t t

DAC sin x/x Roll Off (Amplitude Normalized)
RECONSTRUCTED SIGNAL t 1 fc 1 A = sin  f fc –3.92dB A This graph shows a couple of things that are important to realize about DACs. The first thing to notice about the bottom graph is that just as with the A/D converter, the DAC has aliases and its output. When we’re working with a DAC we typically refer to these as images rather than aliases, but it’s an equivalent process. The images reflect around the sampling rate and the harmonics of the sampling rate, just as they did with the ADC. The second thing to realize is that the output spectrum of the DAC has a unique attenuation pattern, known as sinX/X rolloff. Since the DAC output is a zero hold transfer function, the output spectra is defined over frequency by the sinX/X. Therefore, images will be attenuated to the extent of this envelope. <Next> IMAGES IMAGES IMAGES f 0.5fc fc 1.5fc 2fc 2.5fc 3fc FS – FOUT FS + FOUT 2FS – FOUT 2FS + FOUT

LPF Required to Reject Image Frequency
Just as with an ADC’s anti-alias filter, the output of the DAC needs to have its images rejected with image reject filter. The design of these filters can range from simple to quite complex, due to the need to accommodate the high slew rate of the DAC. Similar design requirements to the anti-aliasing filter of flat passband, linear phase, and sufficiently fast roll off are desired. <Next>

Analog Filter Requirements for fo = 10MHZ: fc = 30MSPS, and fc = 60MSPS
PF f CLOCK = 30MSPS d B f o IMAGE IMAGE IMAGE IMAGE 10 20 30 40 50 60 70 80 FREQUENCY (MHz) B And once again just like with the ADC, we can make life easier for ourselves in designing our image reject filter if we oversample. In the top example you can see that in the case of sampling at 30 MSPS, and synthesizing a 10 MHz signal, the low pass filter requirements are very steep in order to attenuate the image which is reflected around the sample rate. In the bottom graph we have doubled the sample rate to 60 MSPS, and made the filter about four times easier to make. I should also point out that, just like with the A/D converter, we can purposefully use the images of the DAC output to create high-frequency output. Of course in that case you have to redesign your filters similarly to the way we did with the A/D. However due to the Sin X /X roll off attenuation, these applications typically require compensation by way of an inverse sine X/x filter, to help mitigate the attenuation. But in these oversampled examples, there is a problem. The data rate increases linearly with the sampling rate. Not only that but the digital calculations needed to insert points in between is not trivial at these higher data rates. <Next> f CLOCK = 60MSPS d B f o A N AL OG LPF IMAGE IMAGE 10 20 30 40 50 60 70 80

Analog to Digital Converters
Architectures Analog Devices Confidential – © 2008 – Version 1a

ADC Architectures, Applications, Resolution, Sampling Rates
High Speed Data Conversion Overview ADC Architectures, Applications, Resolution, Sampling Rates Precision : ≤ 10MSPS High Speed: > 10MSPS 24 INDUSTRIAL MEASUREMENT 22 VOICEBAND, AUDIO - 20 DATA ACQUISITION VIDEO, IF SAMPLING, SOFTWARE RADIO, ETC. - 18 RESOLUTION (BITS) 16 SAR 14 Four key ADC Market segments: Data Acquisition, Precision Industrial Measurement, Voiceband and Audio, and High Speed High Speed" implying sampling rates greater than approximately 10MSPS—although this line of demarcation is somewhat arbitrary. A 2MSPS 16-bit SAR ADC is definitely "high speed" in its class. A basic understanding of the three most popular ADC architectures is valuable in selecting the proper ADC for a given application. It is very unwise to treat an ADC as simply a "black box." The dotted line represents the approximate state-of-the art today (2006). Even though there is considerable overlap between the coverage of the various architectures, the applications themselves differentiate between the specific architecture required. The Sigma-Delta architecture dominates the precision industrial measurement, voiceband, and audio application space. The focus of this part of the seminar will be on the SAR and Pipeline ADC architectures. CURRENT STATE-OF-THE-ART (APPROXIMATE) 12 PIPELINE 10 8 10 100 1k 10k 100k 1M 10M 100M 1G SAMPLING RATE (Hz)

Speed and Resolution of ADC Types
24 22 20 18 16 14 12 10 8 Oversampled SAR Resolution (ENOB) Fast ΣΔ CT ΣΔ Precision ΣΔ SAR Pipelined k 10k 100k 1M 10M 100M 1G Usable Bandwidth (Hz)

The Comparator: A 1-Bit ADC
LATCH ENABLE + DIFFERENTIAL ANALOG INPUT LOGIC OUTPUT – COMPARATOR OUTPUT "1" No comparator may be the simplest ADC. It’s a one bit ADC, and operating by itself doesn’t give us much resolution. <next> VHYSTERESIS "0" DIFFERENTIAL ANALOG INPUT

Basic Successive Approximation ADC
High Speed Data Conversion Overview Basic Successive Approximation ADC CONVERT START TIMING ANALOG INPUT SHA COMPARATOR EOC, DRDY, OR BUSY CONTROL LOGIC: SUCCESSIVE APPROXIMATION REGISTER (SAR) The SAR ADC performs conversions on command. On the assertion of the CONVERT START command (called other things) the sample-and-hold (SHA) is placed in the hold mode. All the bits of the successive approximation register (SAR) are reset to "0" except the MSB which is set to "1". The SAR output drives the internal DAC. If the DAC output is greater than the analog input, this bit in the SAR is reset, otherwise it is left set. The next most significant bit is then set to "1". If the DAC output is greater than the analog input, this bit in the SAR is reset, otherwise it is left set. The process is repeated with each bit in turn. When all the bits have been set, tested, and reset or not as appropriate, the contents of the SAR correspond to the value of the analog input, and the conversion is complete. These bit "tests" can form the basis of a serial output version SAR-based ADC. Some SARs have parallel outputs also. The basic accuracy of the SAR ADC is determined by the internal DAC. DAC OUTPUT

Successive Approximation ADC Algorithm Analogy Using Binary Weights
ASSUME X = 45 TEST IS X  32 ? YES  RETAIN 32  1 IS X  (32 +16) ? NO  REJECT 16  0 IS X  (32 +8) ? YES  RETAIN 8  1 The basic "balance scale" algorithm for SAR ADCs was known by mathematicians in the 1500s. It was used to determine unknown weights using a minimum number of known weights and a minimum sequence of weighing operations. Gordon patented a vacuum tube logic circuit block which accomplished this function in his "Datrac" ADC. AMD and National later introduced SAR ICs which performed the function in a single chip. Bell Labs implemented 5-bit, 8kSPS vacuum tube SAR ADCs in the 1940s. IS X  ( ) ? YES  RETAIN 4  1 IS X  ( ) ? NO  REJECT 2  0 YES  RETAIN 1  1 IS X  ( ) ? TOTALS: X = = =

High Speed Data Conversion Overview
Typical SAR ADC Timing SAMPLE X SAMPLE X+1 SAMPLE X+2 CONVST CONVERSION TIME TRACK/ ACQUIRE CONVERSION TIME TRACK/ ACQUIRE EOC, BUSY The end of conversion is generally indicated by an end-of-convert (EOC), data-ready (DRDY), or a busy signal (actually, not-BUSY indicates end of conversion). The polarities and name of this signal may be different for different SAR ADCs, but the fundamental concept is the same. At the beginning of the conversion interval, the signal goes high (or low) and remains in that state until the conversion is completed, at which time it goes low (or high). The trailing edge is generally an indication of valid output data, but the data sheet should be carefully studied—in some ADCs additional delay is required before the output data is valid. An N‑bit conversion takes N steps. The exact labels assigned to these functions can vary from converter to converter, but are generally present in most SAR ADCs. Some SAR ADCs require an external high frequency clock in addition to the CONVERT START command. In most cases, there is no need to synchronize the two. The frequency of the external clock, if required, generally falls in the range of 1MHz to 30MHz. Other SAR ADCs have an internal oscillator which is used to perform the conversions and only require the CONVERT START command. Because of their architecture, SAR ADCs generally allow single-shot conversion at any repetition rate from dc to the converter's maximum conversion rate. Note that at the end of the conversion time, the data corresponding to the sampling clock edge is available with no "pipeline" delay. Unlike most "pipelined" ADCs, the SAR ADC generally has no "minimum" specified sampling rate. SAR ADCs can be operated continuously, or in a "single-shot" mode. This feature is extremely useful in multiplexed applications. The basic SAR is a serial output device. Although parallel output versions are available, the trend is toward the serial interface (SPI, I2C, etc.) because of reduced pin count, package size, and cost. OUTPUT DATA DATA X DATA X+1

4-Bit Switched Capacitor ADC
High Speed Data Conversion Overview 4-Bit Switched Capacitor ADC + _ Vin Vref C C/2 C/4 C/8 Comparator S1 S2 S3 S4 S5 S6 S7 Sample Mode The accuracy and linearity of the internal DAC determines the accuracy and linearity of the overall SAR ADC. Early SAR ADCs, such as the industry standard AD574, used thin film laser wafer trimmed internal DACs. Today, this approach has been replaced by switched capacitor (often called charge redistribution) CMOS DACs shown here. The capacitor matching is controlled by the precise lithography, and extra capacitors and switches can be added for trimming either at the factory or as part of autocalibration routines run at the system level after installation. The operation of the capacitor DAC is similar to an R-2R resistive DAC. When a particular bit capacitor is switched to VREF, the voltage divider created by the bit capacitor and the total array capacitance (2C) adds a voltage to node A equal to the weight of that bit. When the bit capacitor is switched to ground, the same voltage is subtracted from node A.

4-Bit Switched Capacitor ADC
High Speed Data Conversion Overview 4-Bit Switched Capacitor ADC + _ Vin Vref C C/2 C/4 C/8 Comparator S1 S2 S3 S4 S5 S6 S7 Hold Mode -Vin AD7626 – 16-Bit -10MSPS 16 steps required for one Conversion 160MHz internal frequency 6.25ns each step. + _ Vin Vref C C/2 C/4 C/8 Comparator S1 S2 S3 S4 S5 S6 S7 Redistribution Mode 0V The accuracy and linearity of the internal DAC determines the accuracy and linearity of the overall SAR ADC. Early SAR ADCs, such as the industry standard AD574, used thin film laser wafer trimmed internal DACs. Today, this approach has been replaced by switched capacitor (often called charge redistribution) CMOS DACs shown here. The capacitor matching is controlled by the precise lithography, and extra capacitors and switches can be added for trimming either at the factory or as part of autocalibration routines run at the system level after installation. The operation of the capacitor DAC is similar to an R-2R resistive DAC. When a particular bit capacitor is switched to VREF, the voltage divider created by the bit capacitor and the total array capacitance (2C) adds a voltage to node A equal to the weight of that bit. When the bit capacitor is switched to ground, the same voltage is subtracted from node A.

Driving the AD7944 – 18b 1.33MSPS

First-Order Sigma-Delta ADC
å ò + - +VREF –VREF DIGITAL FILTER AND DECIMATOR _ CLOCK Kfs VIN N-BITS fs A B 1-BIT DATA STREAM 1-BIT DAC LATCHED COMPARATOR (1-BIT ADC) 1-BIT, SIGMA-DELTA MODULATOR INTEGRATOR Vref -Vref Vin VB VA CK t Noise shaping and oversampling is accomplished in the sigma-delta modulator. This is a simple first-order single-bit modulator, and the output is a 1-bit stream of data. Because of feedback, the signal at B must (on the average) equal VIN. This ADC is inherently linear and monotonic because of the 1-bit ADC and 1-bit DAC. If VIN is zero (midscale), there are an equal number of "1"s and "0"s in the output data stream. The DC value of the input is equal to the ratio of the "1"s in the output stream to the total number of samples in the same interval.

Oversampling, Digital Filtering, Noise Shaping, and Decimation
fs QUANTIZATION NOISE = q / 12 q = 1 LSB Nyquist Operation ADC fs 2 Oversampling + Digital Filter + Decimation fs B Kfs fs DIGITAL FILTER ADC DIGITAL FILTER DEC REMOVED NOISE fs 2 Kfs 2 Kfs This slide shows the fundamental concepts of sigma-delta ADCs: Oversampling, Noise Shaping, Digital Filtering, and Decimation. (A): This is standard "Nyquist" operation for an ADC. (B): Oversampling by a factor of K reduces the quantization noise within the bandwidth of interest, and it can be removed with a digital filter. The output rate of the digital filter can be reduced (decimated) to the original fs. Each time K is doubled, the noise in the fs/2 bandwidth is reduced by 3dB. (C): The addition of the sigma-delta modulator shapes the quantization noise and pushes most of it outside the bandwidth of interest. This greatly increases the SNR within the DC to fs/2 bandwidth. Oversampling + Noise Shaping + Digital Filter + Decimation C Kfs fs REMOVED NOISE SD MOD DIGITAL FILTER DEC fs 2 Kfs 2 Kfs

Noise Shaping Σ Σ Σ Analog Filter H(f)=1/f ò Q (1/F)(X-Y) + X X-Y + +
Vin Y + - ò CK 1-Bit DAC Digital Filter

Multi-Bit Sigma-Delta ADC
CLOCK Kfs fs INTEGRATOR DIGITAL FILTER AND DECIMATOR VIN N-BITS ò å A + n-BIT Flash ADC _ fs B n-BIT, Kfs We’ll finish up looking at Sigma Delta converters. Sigma-Delta converters use three fundamental concepts - oversampling, noise shaping, and digital filtering to achieve their very high resolution, with 24 bits being available. Here we see a first-order Sigma Delta ADC showing the modulator front-end followed by the digital filter. The modulator consists of a loop filter, in this case an integrator, followed by a quantizer – in this case a comparator, which controls a DAC, whose output is feed back to the input. The input comes into a summing point where the value from the DAC is subtracted off, and presented through the integrator to the comparator, which in this case is comparing the input to ground. The comparator drives the DAC in an attempt to force the integrator output to be zero. In the process, a stream of comparator results, ones and zeros, not only goes to the DAC, but this stream of data also goes to the digital filter. By looking at a moving average of the ones density over time, the filter can determine the signal level. For a static signal, the more data is averaged, the higher the resolution. In the case of the Sigma Delta converters the sampling is done at the comparator, while quantization is a function of both the comparator and the DAC. <Next> n-BIT DAC n-BIT DATA STREAM SIGMA-DELTA MODULATOR

AD719x – Application Example Weigh Scale Loadcell or Pressure Sensor Measurement
+5V 2 mV/V Sensitivity IN+ OUT- OUT+ IN- Exceptional precision for low speed & high speed Weigh Scale applications 8.5 nV rms noise (Gain = 128, 4.7 Hz Output Update Rate) 16 bits of noise free resolution (Gain =128, 2.4 kHz Output Update Rate) Lowest Offset 5 nV/°C Power Save Mode via programmable Bridge Power Down Switch (BPDSW) 48 48

3-Bit All-Parallel (Flash) Converter
High Speed Data Conversion Overview 3-Bit All-Parallel (Flash) Converter STROBE ANALOG + INPUT – +V REF 1.5R R + – R + A KEY BUILDING BLOCK FOR PIPELINED ADCs – PRIORITY N DIGITAL ENCODER + OUTPUT R AND LATCH – R + The flash converter is a building block in pipelined ADCs. The flash converter makes use of parallel comparators, each operating at a slightly different reference voltage determined by the resistor ladder network. An N-bit flash converter requires 2N – 1 latched comparators. Therefore, the technique is rarely used beyond 8-bits because of power dissipation and die size (cost). The comparators are latched simultaneously; therefore, a separate SHA is not generally required. However, mismatches in timing between the comparators may require an external SHA for optimum performance at high input slew rates. The output of the comparator bank is a thermometer code, which is decoded into the proper binary code by the decoding logic. Conceptually, the decoding logic is a priority encoder, but it may be more complicated to correct for comparator metastable state errors. IC flash ADCs became extremely popular in the 1980s especially in the 8-bit, 20MSPS to 100MSPS sampling range. Today, however, standalone flash ADCs are mostly used at sampling rates of 1GSPS or higher for six to eight bits of resolution, and are high-power GaAs devices. Even at 1GSPS, interleaved pipelined ADCs are used rather than GaAs. Low resolution flash ADCs are still used as building blocks in various subranging pipelined ADCs and in multi-bit sigma-delta ADCs. – R + – R + – 0.5R

6-Bit Two-Stage Subranging ADC
High Speed Data Conversion Overview 6-Bit Two-Stage Subranging ADC RESIDUE SIGNAL ANALOG INPUT _ SAMPLE AND HOLD N1-BIT (3-BIT) SADC N1-BIT (3-BIT) SDAC N2-BIT (3-BIT) SADC +  G SAMPLING CLOCK CONTROL OUTPUT REGISTER Subranging ADCs were first documented in the mid 1950s as shown by this patent reference. This diagram shows a two-stage subranging ADC, but the concept can be continued to more than two stages. There is a "coarse" conversion of N1 bits followed by a "fine" conversion of N2 bits. The individual sub-ADCs (labeled SADC) are generally flash converters, but do not have to be. Subranging ADCs do not necessarily have to exhibit pipeline delay, but most do, in practice. On the other hand, a pipelined ADC is almost always subranging. The N1-bit coarse conversion is converted back to analog by an N1 bit SDAC, subtracted from the held analog signal, amplified, and applied to the N2-bit SADC. Note that the N1 bit SADC and SDAC must be accurate to better than N1 + N2 bits, even though their resolution is less. This type of ADC can be analyzed better by examining the "residue signal" into the second stage. N1 MSBs (3) N2 LSBs (3) DATA OUTPUT, N-BITS = N1 + N2 = = 6 See: R. Staffin and R. Lohman, "Signal Amplitude Quantizer," U.S. Patent 2,869,079, Filed December 19, 1956, Issued January 13, 1959

Residue Waveforms at Input of N2 SADC
High Speed Data Conversion Overview Residue Waveforms at Input of N2 SADC R = RANGE OF N2 SADC (A) IDEAL N1 SADC MISSING CODES The residue waveform into the second N2 SADC must exactly fill the range of the N2SADC as shown in (A). Otherwise, as shown in (B), there will be nonlinearities in the overall transfer function, and possibly missing codes. These nonlinearities can come from the N1SADC, the N1SDAC, or gain or offset errors in the summation amplifier, G. It is difficult to construct two-stage subranging ADCs with overall resolutions of greater than eight bits because of the effects of the first stage errors. We will see shortly how expanding the resolution of the second stage ADC and the use of digital error correction techniques can minimize the effects of the first stage conversion errors on the overall ADC transfer function. X R Y (B) NON LINEAR N1 SADC MISSING CODES

6-Bit Subranging Error Corrected ADC - N1 = 3, N2 = 4
High Speed Data Conversion Overview 6-Bit Subranging Error Corrected ADC - N1 = 3, N2 = 4 OFFSET RESIDUE SIGNAL ANALOG INPUT + SAMPLE AND HOLD N1 3-BIT SADC N1 3-BIT SDAC N2 4-BIT SADC –  G OFFSET SAMPLING CLOCK MSB CONTROL ADDER ( ) CARRY The concept of digital error correction in a subranging ADC was implemented in the mid-1960s as shown in this reference. This figure shows a 6-bit subranging error corrected ADC with three bits in the first stage and four bits in the second stage. The extra bit in the second stage adds the additional range. The second stage MSB controls the digital adder. In practice, rather than adding or subtracting 001 to the MSBs, an offset can be added to the residue signal so that the MSBs are either passed through to the output unmodified, or with 001 added to them. This simplifies the logic. There is no theoretical reason why more bits can't be added to the second stage, thereby allowing more errors in the first stage, but practical design considerations and tradeoffs come into play here. OVERRANGE LOGIC AND OUTPUT REGISTER DATA OUTPUT SEE: T. C. Verster, "A Method to Increase the Accuracy of Fast Serial-Parallel Analog-to-Digital Converters," IEEE Transactions on Electronic Computers,EC-13, 1964, pp

Generalized Pipeline Stages in a Subranging ADC with Error Correction
High Speed Data Conversion Overview Generalized Pipeline Stages in a Subranging ADC with Error Correction (A) T/H + – + + SADC N1 BITS SDAC N1 BITS + SADC N2 BITS SDAC N2 BITS –  – T/H, 1  T/H, 2 – TO ERROR CORRECTING LOGIC (B) T/H + – The pipelined architecture shown in this figure is a digitally corrected subranging architecture in which each stage operates on the data for one-half the sampling clock cycle and then passes its residue output to the next stage in the pipeline, prior to the next half cycle. The interstage track-and-hold (T/H) serves as an analog delay line—timing is set such that it enters the hold mode when the first stage conversion is complete. This gives more settling time for the internal SADCs, SDACs, and amplifiers, and allows the pipelined converter to operate at a much higher overall sampling rate than a non-pipelined version. The term "pipelined" architecture refers to the ability of one stage to process data from the previous stage during any given phase of the sampling clock cycle. At the end of each phase of a particular clock cycle, the output of a given stage is passed on to the next stage using the T/H functions, and new data is shifted into the stage. Of course this means that the digital outputs of all but the last stage in the "pipeline" must be stored in the appropriate number of shift registers so that the digital data arriving at the correction logic corresponds to the same sample. Pipelined subranging ADCs usually have a number of identical stages in the pipeline. SADC N1 BITS S MDAC N1 BITS T/H + SADC N2 BITS S MDAC N2 BITS – TO ERROR CORRECTING LOGIC

ADC Output Configurations
4/20/2017 ADC Output Configurations PARALLEL SERIAL LVDS SerDes N ADC ADC DCO ADC Fdata FCLK Fdata Fdata DCO PLL PLL Fs Fs Fs Parallel CMOS Fdata max = 150 MSPS DDR LVDS Fdata max = 420 MSPS Interface available in lower cost FPGAs Pins = ADC resolution plus DCO High pin count Fdata max = 840Mbps? Serial LVDS Fs max = Fdata * # of data lanes / ADC resolution On chip PLL required Higher-end FPGA typically required Pins = # of data lanes plus Frame CLK and Data CLK Fdata = 3.125Gbps+ Encoded serial CML Fs max = data packet length + overhead On chip PLL required High-end FPGA required Clock recovery Slower customer adoption rate 2 pins 54

TRX System Architectures
4/20/2017 TRX System Architectures Today’s solution Solution with JESD204A Serial Interface Tight timing requirements Minimum # of I/Os Relaxed Timing requirements Large # of I/Os Serdes? 32 wires FPGA CPRI/ OBSAI FPGA 2 to 4 Serial pairs CPRI/ OBSAI Dual 16B DAC To Antenna 1 Dual16B DAC To Antenna 1 SERDES chip 16 wires 1 Serial pair 14B ADC 14B ADC We should test our assumption of 2 antenna’s per FPGA. It would be good to understand exactly how customers implement this functions across multiple FPGAs (e.g. where does the DPD observation ADC feed in?) ADC = 16-bit LVDS DDR means 8 pairs of LVDS for data and 1 pair for the DCO 32 wires 2 to 4 Serial pairs Dual 16B DAC To Antenna 2 Dual 16B DAC To Antenna 2 18 wires 1 Serial pair 14B ADC 14B ADC FPGA FPGA 55 55

IF Sampling and IF Synthesis
IF Sampling Rx CLOCK GEN/DIST In a third type of architecture, also called the IF Sampling architecture, the demodulation is all done in the digital domain. We therefore notice that the DEMODULATOR block is missing. In the scenario shown here, we go through two stages of the down conversion in the receiver chain, using two mixers. The signal follows from the second mixer straight into the ADC for conversion to the digital domain. The parallel transmit side, shows IF Synthesis Transmission, where the modulation has also been done digitally, and the intermediate frequency, is upconverted to RF by the mixer. Here you can notice the absence of the Modulator block. Depending on the application one if working, one of the above architecture or a combination of two are generally used. The choice of architecture if determined by performance and cost considerations. IF Sampling and Direct Conversion architectures reduce the number of blocks used in the signal chain, and therefore maybe cost effective. For the purpose of our discussion today, and to introduce you to all the possible solutions Analog Devices has to offer, we will look the single stage Superheterodyne architecture, and follow the signal as it moves from the antenna to the FPGA. IF Synthesis Tx POWER MANAGEMENT & SUPERVISORY

Why would you choose a ... Successive Approximation Converter
4/20/2017 Why would you choose a ... Successive Approximation Converter Why not? It is the most common and easy to use type of converter, with practically all combinations of speed, resolution, channel count, input interface, output interface, size and cost. AD7626 is the fastest 16 bit SAR at 10MSPS AD7690 is the highest SNR 101.5dB AD7468 is the lowest power (570uW at 200kSPS, lower if run slower) AD7276 is a good all-rounder, 12 bits, 3MSPS, TSOT-6, 3.6mW Unbeatable for high resolution measurements with low-delay Unbeatable for multiplexed applications Can be optimised for low-power (sleep mode between conversions) Can be optimised for low noise (averaging or filtering the output)

Why would you choose a ... Precision Sigma Delta converter
4/20/2017 Why would you choose a ... Precision Sigma Delta converter Low noise and accuracy for DC measurements Best is AD7190, AD7191, AD7195 Integrated Sensor conditioning and System-on-chip AD779x family have buffers, muxes, current sources, reference inputs to suit various temperature, pressure and other sensors. Low power at low data rates AD7171 needs only 330uW for full operation (but SAR can be even lower power if put to sleep between conversions at very low sample rates) Robustness AD7190 has 50/60Hz rejection of 120dB

Why would you choose a ... Fast Sigma Delta converter
4/20/2017 Why would you choose a ... Fast Sigma Delta converter Accurate DC and AC measurements, stable over temperature e.g. AD7764 has offset & gain drift <1ppm/°C Flat frequency response over the pass band AD7764 filter has 0.1dB ripple Wide Dynamic range over a wide bandwidth AD7764 has 115dB Dynamic range Robustness AD7764 has excellent anti-aliasing performance

Why would you choose a ... Pipelined Converter
4/20/2017 Why would you choose a ... Pipelined Converter When you need to retain good AC performance over wide bandwidths or at high signal freqencies AD9434 is a 12 bit 500 MSPS converter. ENOB = 10.4 at 450MHZ AD9467 is a 16 bit 250 MSPS converter. SFDR = 100dB at 170MHz allowing very small signals to be detected in the presence of very large ones When you need to measure a signal with very high sample rate AD9286 toggles 2 ADCs to achieve 500MSPS. It is targeted at Oscilloscope applications and other time-domain measurements

Continuous time Sigma Delta is easy to drive CN-0062
Reduces system level component count, cost, size, and power consumption Automatic Gain Control ADL5382 Quadrature Demodulator AD9262 FPGA Digital Processing AAF AAF ADC Amp RF Front End 16-bit CT-ΣΔ ADC 90 Phase Shifter Main RX AAF AAF ADC Amp AD9520 Clock Generation and Distribution To TX/FPGA 61 61

Input Considerations Continuous Time Sigma Delta
4/20/2017 Input Considerations Continuous Time Sigma Delta Input is purely passive 1kohm differential input resistor for 85dB SNR (10MHz BW, 2Vpp) Driver amplifier may be removed Input impedance is real vs. complex Low NF allows reduced gain before ADC => more linear front-end Typical Pipeline ADC: NF=22 -78dBFS at 125MHz, +4dBm fullscale, 0.4W/ADC = -152dBm/Hz AD9262: NF=15 -86dBFS over 10MHz, -3dBm fullscale, 0.35W/ADC = -158dBm/Hz S/H Quantizer Switched Capacitor Input Discrete-Time ADC Vin Loop Filter Amp DAC Vin Continuous-Time ΣΔ ADC Quantizer 62

Digital to Analog Converters
Architectures Analog Devices Confidential – © 2008 – Version 1a

1-Bit DAC: Changeover Switch (SPDT)
VREF OUTPUT Perhaps the simplest DAC is the one bit DAC comprised of a single pole double throw switch, known as the changeover switch. On one input of the switch place the voltage reference, on the other place ground, and have the switch toggle between the two. This in fact is the heart of some DACs, like certain PCM DACs or DAC within some Sigma Delta A/D converters. But even this very simple architecture has some issues that we need to be aware of. < next>

Sampled Data System: Sampling and Quantization

Sampled Data System: Sampling and Quantization
The very act of sampling causes the signal to be parsed in two axes. We refer to sampling as the impact along the time domain. While quantization is the impact along the amplitude domain. that the very act of sampling does cause both to take place at the same time. This sampling can be continuous or to be discontinuous. And as we’ll see this very process has enormous impact on the quality of the signal captured. < next >

Sigma-Delta DAC Digital Interpolation Filter Digital ΣΔ Modulator
Analog Signal 2 Levels fs K fs K fs Analog Output Digital Interpolation Filter Digital ΣΔ Modulator 1-Bit DAC Analog Output Filter Single Bit Analog Signal 2M Levels fs K fs K fs Analog Output Digital Interpolation Filter Digital ΣΔ Modulator 1-Bit DAC Analog Output Filter Multi Bit

Simplest Voltage Output Thermometer DAC: The Kelvin Divider ( AKA - "String DAC")
REF R 3-TO-8 3-BIT DECODER DIGITAL R INPUT 8 R TO SWITCHES R ANALOG OUTPUT R Let’s start looking at some of the architectures which are used in today’s modern DACs. Perhaps one of the simplest ones for producing a voltage output is the Kelvin divider, which is also known more commonly as the string DAC. This type of DAC is a thermometer type approach, whereby an array of equally weighted resistors, between a voltage reference and ground, contribute voltage to the output by closing subsequent switches starting at the bottom and working up, produces larger voltages. The sampling and quantization takes place in this architecture at the switches, while the digitization takes place in the digital drivers of the switches. <Next> R R R

Digital Potentiometer
Terminal A 3-TO-8 3-BIT DECODER DIGITAL R INPUT 8 R TO SWITCHES R TAP R Let’s start looking at some of the architectures which are used in today’s modern DACs. Perhaps one of the simplest ones for producing a voltage output is the Kelvin divider, which is also known more commonly as the string DAC. This type of DAC is a thermometer type approach, whereby an array of equally weighted resistors, between a voltage reference and ground, contribute voltage to the output by closing subsequent switches starting at the bottom and working up, produces larger voltages. The sampling and quantization takes place in this architecture at the switches, while the digitization takes place in the digital drivers of the switches. <Next> R R R Terminal B

The Simplest Current Output Thermometer (Fully-Decoded) DAC
V REF R R R R R R R 3-TO-7 CURRENT DECODER OUTPUT INTO VIRTUAL GROUND 7 TO SWITCHES (USUALLY AN Another very simple architecture is known as the fully decoded DAC. The voltage reference be equally weighted resistors, and the switches in this case are acting to steer currents to the output. It’s important when using current output DACs that the output be directed into virtual ground. This is typically an op amp acting as a current to voltage converter, but other setups are possible. Here again, the sampling and quantization are taking place across the switch array in a parallel fashion. <Next> OP-AMP I-V CONVERTER) 3-BIT DIGITAL INPUT

Voltage-Mode Binary Weighted Resistor DAC
OUT R/8 R/4 R/2 R LSB MSB V REF An improvement over the thermometer architectures, like the fully decoded architecture, is shown here. This is a voltage mode, binary weighted resistor DAC. Starting at the far right, that resistor, R, produces the MSB. Then resistors are scaled with the binary weighting, until the LSB. In this case the DAC is a voltage mode device, since the switches are selecting between the voltage reference or ground to make the selection to pass through the resistor to the output. Because of the interaction of the voltage switching via the switch between widely different voltages of the reference and ground, voltage mode DACs tend to have a harder time achieving good distortion performance, when compared to their current mode siblings, were the switch is not making large voltage transitions. As a good rule of thumb to remember when you’re selecting DACs. While we generally like to deal with voltages, there can be benefits to dealing with currents. <Next>

Current-Mode R-2R Ladder Network Resistor-Based DAC
V REF * R R R << R 2R 2R 2R 2R 2R MSB LSB CURRENT OUTPUT Current mood case as shown here, it works the same way. A small trim resistor is sometimes added immediately following the voltage reference input to just gain error. As opposed to the voltage mode DACs, the current steered DACs need to operate with your outputs working into a virtual ground, and within the voltage output compliance rating. <Next> INTO VIRTUAL GROUND * GAIN TRIM IF REQUIRED

Segmented Voltage Output DACs
KELVIN-VARLEY DIVIDER ("STRING DAC") (B) KELVIN DIVIDER AND R-2R LADDER NETWORK V V REF REF A B A OUTPUT B A B OUTPUT A But increasingly DACs are built not by one architecture alone but often through the combination of several. In the first example we show a Kelvin-Varley divider, or segmented string DAC, which to gain higher resolution while minimizing the number of resistors, this architecture buffers one string DAC into another, producing a segmented architecture with high resolution, but low power and small size. In this case, the sampling of quantization is more distributed across two layers of switches and resistors. The second architecture is another segmented device, this time improving the resolution of the string DAC, with a voltage mode R-2R ladder DAC. Of interest here is that we’ve spread out the sampling and quantization more widely, care must be taken by the designer to make sure that the stages minimize parasitics, so that the transitions are clean and accurate. Also in the second architecture, note that if the R-2R ladder network is monotonic, the whole DAC is monotonic. <Next> B NOTE: MSB OF R-2R LADDER ON RIGHT A IF THE R-2R LADDER NETWORK IS MONOTONIC, THE B WHOLE DAC IS MONOTONIC A A B

Oversampling Interpolating Txdac™ Simplified Block Diagram
DIG IT AL N N N LA T CH INTER POLA TION LA T CH D A C FILTER f Here is a simplified block diagram of an interpolating DAC, which we call a TX DAC – for transmit DAC, since these types of DACs are often used in transmit architectures in communications systems. A relatively low speed digital interface to the outside world is provided, and the onboard PLL, and digital interpolation filter do all the heavy lifting. <Next> c K•f c PLL LPF f o TYPICAL APPLICATION: f c = 160MSPS f = 50MHz o K = 2 Image Frequency = 320 – 50 = 270MHz

Multiplying DAC MDAC Vref Analog Output Digital Input
Analog Output = Vref x Digital Input x K 2R R V REF MSB LSB CURRENT OUTPUT INTO VIRTUAL GROUND << R * * GAIN TRIM IF REQUIRED Current mood case as shown here, it works the same way. A small trim resistor is sometimes added immediately following the voltage reference input to just gain error. As opposed to the voltage mode DACs, the current steered DACs need to operate with your outputs working into a virtual ground, and within the voltage output compliance rating. <Next>

ADCs State of the Art SAR Converters

The Need For Speed 16-bit PulSAR ADCs
Technology Leadership: Meeting customer need for faster sampling rate No compromise on performance, keeping power to a minimum AD7626 0.25um 10 MSPS 10 9 8 7 AD7625 0.25um 6 MSPS 6 Speed MSPS 5 AD7621 0.25um 3 MSPS AD7622 0.25um 2 MSPS 4 AD7677 0.6um 1 MSPS 3 2 1 2002 2005 2008 2010 Year of Release 77

AD7626 and AD7625 16-Bit, 10MSPS and 6MSPS PulSAR® Differential ADCs
Features Fast Throughput, High Performance 10 MSPS (AD7626) 6 MSPS (AD7625) SAR architecture 16-bit resolution with no missing codes SNR: 92 dB Typ, 90dB 1MHz INL: ±1 LSB Typ, ±2 LSB Max DNL: ±0.3 LSB Typ, ±1 LSB Max Differential input range: ± 4.096V No latency/no pipeline delay Serial LVDS interface On-Board 4.096V Reference Power dissipation MSPS, MSPS 16-Bit Resolution 4.096 Input 1 Channels 2LSB INL, Max Serial-LVDS Interface 32-lead LFCSP Package 78

AD7980- 1MSPS, 7mW 16 Bit ADC in MSOP/QFN
EE Times China converter Winner The World Lowest Power 16-Bit ADC Lowest Power: 1MSPS Power scales linearly with sampling rate like 10kSPS The World Smallest Package in > 0.2MSPS 16-Bit ADC LFSCP/QFN (SOT23 size) or MSOP Pin-Pin compatible with AD768x The World fastest MSOP/QFN 16-Bit ADC Outstanding DC and AC Performance 16-Bit No Missing Code +/-1.5LSB INL Max 20bit effective 10kSPS Ease of use 2.5V main supply 0 to REF input (up to 5V) - lower cost opamp - 5V/3.3V/2.5V serial SPI Multiple ADC Daisy Chain, Busy Indicator 3mm For Data acquisition, ATE, Smart Sensors and Portable Medical equipments

AD7982 PulSAR ADC: 18-Bit, 1MSPS, 7mW
The World Lowest Power 18-Bit ADC 1MSPS (30x lower than competition) Power scales linearly with sampling rate: 10kSPS The World Smallest Package 18-Bit ADC LFSCP/QFN (SOT23 size) or MSOP (5x smaller than competition) Pin-pin compatible with AD769x Outstanding DC and AC Performance 18-bits NMC, +/-2LSB INL max 22.7 bit effective 1kSPS Ease of use Easy design for ANY input ranges 0 to REF input (up to 5V) - lower cost opamp - 5V/3.3V/2.5V serial SPI Multiple ADC daisy chain, busy indicator Released

AD7986 High Speed 2MSPS 18-bit ADC, Low Power 15mW, 4
AD7986 High Speed 2MSPS 18-bit ADC, Low Power 15mW, 4.096V Reference, 20L-LFCSP AD7986 18-bit, 2MSPS High Performance Maintains leadership position: Smallest, Fastest, Lowest Power Features Lowest power: 2MSPS w/o reference 2MSPS w/reference Throughput: 2MSPS Turbo= HIGH 1.5MSPS Turbo= LOW 1.8V/2.5V/2.7V serial SPI SNR 97dB w/external VREF Pin for pin with AD7985 (16b), AD7944 (14b) Resolution Input Channels INL, Max Interface Package 18-bits DIFF +/-VREF 1 1LSB typ 2.5LSB max SPI QFN-20

AD7609 : 18 Bit, 8-Channel Simultaneous Sampling ADC Multi-Market Building Block for High Dynamic Range Applications simultaneous sampling Energy Motor Control Process Control Instrumentation Features 8 channels simultaneous sampling 200KSPS for all 8 Channels Single 5V supply operation Differential Analog Inputs +/-20V & +/-10V  40V Differential Analog Input Range  Sensors with differential output can connect directly to the AD7609 Analog Inputs can withstand 7KV HBM ESD +/-16.5V Analog input clamp protection 1Meg Resistor input impedance 2nd Order Analog Anti-Alias Filter Backend Digital filter 2.5V reference and reference buffer SPI and Parallel interface. 64 lead LQFP Package Performance 18 Bits No Missing Codes INL +/- 2.5LSB (Typ) 91 dB 200k 105 dB (digital filter on, OSR = 64) 100mW Power (Typ) NFS/PFS Code 0.1% FSR over Temperature

ADCs State of the Art Precision Sigma-Delta (Σ-Δ)

Precision Σ-Δ ADCs – Most Recent
Released Highest Precision + PGA Low Power / Highly integrated with PGA 8.5 nV Noise; 4.8 kHz 2/4-Channel 11 nV Noise; 4.8 kHz 2/4-Channel 5.6 mA-7.35 mA max 4 Hz – 4.8 kHz PLC Weighscale 16-/24-bit 6-ch PGA + ref + exc currents AD7190 AD7192 16-/24-bit 3-ch PGA uA max 4 Hz – 470Hz Temp Pressure Weighscale AD7794/95 AD7798/99 16-bit 2.4kHz; G=128 4/8-Channel AD7193 16-/20-/24-bit 3-ch PGA + ref + exc currents Pin Programmable 15 nV Noise; 120 Hz 2/4-Channel AD7190 Performance With AC Excitation 25mm2 CSP pkg 16/24-bit single ch AD7792/85/93 AD7796/97 8/16-Channel AD7191 AD7194 AD7195 130 uA max 9.5 Hz to 120 Hz Gas Detectors Portable Ultralow Power / Small Package High Dynamic Range 24-Bit DAQ Vibration Medical (EEG) WideBandwidth DC & AC 16-/24-bit 1-ch PGA 16-/24-bit 1-ch PGA 16-/24-bit 2-ch PGA AD7788/89 AD7790/91 AD7787 AD7764 AD7767/67-1/67-2 312kHz, 115dB, Diff Amp& Ref Buffer AD7760/2/3 128/64/32kHz 8mW, 115dB, 18-Bit INL Ease-of-Use AD7765 2.5MHz/625kHz 100dB, Diff Amp & Ref Buffer Programmable filter AD7766/66-1/66-2 AD7780/81 500 uA max 10 Hz/ 16.7 Hz Weighscales Pressure Portable Bridge Sensor ADCs 24/20-bit; 380 µA 156kHz, 115dB, Diff Amp& Ref Buffer Flexible Decimation 128/64/32kHz 8mW, 115dB, 16-Bit INL AD7170/71 Tiny Pkg 12/16-bit ADCs

AD7785/92/93/94/95 – Product Description Low Power, Highly Integrated Σ-Δ ADC for Temperature Sensing Low Power – 400 μA typical Low Noise – 40 nV rms Programmable Integrated Features for Temperature Sensing (RTDs, Thermocouples, Thermistors) Instrumentation Amplifier (binary gains 1 to 128) Excitation Current Sources (10 / 210 / 1000 µA) Voltage Reference, Clock Input Buffer, Temp Sensor Superior offset & gain drift specs Offset = 10 nV/°C; Gain = 1 ppm/°C Simultaneous 50 & 60 Hz Rejection 4 Hz to 470 Hz Output Data Rate Supply: 2.7 V to 5.25 V Temp: -40°C to +105°C +125°C option for AD7794 AD7792/85/93 16-/20-/24-bit Σ-Δ ADC 3 Differential Channels 16-TSSOP Package AD7795/94 16-/24-bit Σ-Δ ADC 6 Differential Channels 24-TSSOP Package

Temperature Measurement RTD Sensor
KEY APPLICATION BENEFITS 3-wire RTD 2 matched excitation currents 40 nV Gain = 64 Ratiometric Configuration 50 & 60 Hz Rejection (-70 dB)

Temperature Measurement Thermocouple Sensor
KEY APPLICATION BENEFITS Thermocouple Internal Reference 40 nV Gain = 64, 4 Hz Update Rate Differential Analog Input On-chip VBIAS Centers the Sensor Range 50 & 60 Hz Rejection KEY APPLICATION BENEFITS Cold Junction Second Channel In-Amp (Gain 1-64) Excitation Currents Ratiometric Measurement

Flow Measurement Flow Sensor
KEY APPLICATION BENEFITS Flow Sensor Several channels required 40 nV RMS Noise (In-Amp Gain = 64) REFIN up to AVDD Ratiometric Configuration 50 & 60 Hz Rejection (-70 dB)

Pressure Measurement Weigh Scale (Bridge Sensor / Loadcell)
KEY APPLICATION BENEFITS 27 nV noise (In-Amp Gain = 128, 4 Hz Update Rate) REFIN up to AVDD Ratiometric Configuration Medium/High Range Weigh Scales (1 count in 112, 000 (±10 mV Input Range)) 50 & 60Hz Rejection (-70 dB)

AD7190 – Product Description 2/4 Channel 4
AD7190 – Product Description 2/4 Channel 4.8 kHz Ultralow Noise 24-Bit Σ-Δ ADC with PGA 8.5 nV rms Noise 20.5 bits noise free resolution Gain = 128, Output Data Rate = 4.7 Hz 22.5 bits noise free resolution Gain = 1, Output Data Rate = 4.7 Hz 16 bits noise free resolution Gain = 128, Output Data Rate = 2.4 kHz Output Data Rates up to 4.8 kHz PGA: Gains from 1 to 128 INL 15ppm max (1ppm typ G=1) Offset Drift 5 nV/°C Gain Drift 1 ppm/°C Specified Drift Over Time AVdd = 5V; DVdd = 3V / 5V Resolution Current Channels Output Data Rate Interface Package Temperature 24-Bit 6 mA 2 / 4 4.7 Hz – 4.8 kHz SPI 24-TSSOP -40°C to +105°C 90

AD7190 – Applications 4.8 kHz Ultralow Noise 24-Bit Σ-Δ ADC with PGA
Scientific, Test & Commercial Instruments Weigh Scales (Retail, Laboratory, Industrial Hopper & Conveyer Scales) Chromatography for Chemical Analysis Data Acquisition / Analyzers Dataloggers Industrial Automation PLC/DCS Analog Input Module Front-Ends Temperature Controllers Pressure Measurement Medical Instrumentation Patient Monitoring Blood Pressure Measurement, Temperature Measurement, Blood Analysis 91

AD719x – Application Example Weigh Scale Loadcell or Pressure Sensor Measurement
+5V 2 mV/V Sensitivity IN+ OUT- OUT+ IN- Exceptional precision for low speed & high speed Weigh Scale applications 8.5 nV rms noise (Gain = 128, 4.7 Hz Output Update Rate) 16 bits of noise free resolution (Gain =128, 2.4 kHz Output Update Rate) Lowest Offset 5 nV/°C Power Save Mode via programmable Bridge Power Down Switch (BPDSW) 92 92

AD7760 24 Bit, 2.5MSPS Sigma Delta ADC
4/20/2017 AD Bit, 2.5MSPS Sigma Delta ADC KEY BENEFITS High SNR allows accurate digitization 112dB at 78kHz, 100dB at 2.5 MHz Reduced anti aliasing filtering (Sigma/Delta) Flexibility Filter Programmability allows application customization Comprehensive Solution On Chip Buffer/Amplifiers simplify design - no need for user to select expensive external components AD7760 Filter Response Resolution Speed Interface Power Supply Package 24-Bit 2.5 MHz Parallel 5V , 2.5V 64-TQFP_EP AD7762 AD7763 625 kSPS Version Parallel Interface 625 kSPS Throughput Serial Interface 93 93

ADCs State of the Art Pipelined Converters

ADI : New High Speed ADC Products
DPD Observation Receiver 250MHz BW AD9434 12 bits 500MSPS, low power (AD6641 w FIFO) DPD />100MHz AD9250 Dual 14 bit 250MSPS w/ JES204B ad9643 Dual 14 bit 250MSPS family AD6649 IF Diversity Receiver 250MSPS AD9642 Single 14 bit 250MSPS 5x5 CSP AD9467 16 bit 250MSPS Highest Ain Performance AD6657A Quad 14 bit 205MSPS 65MHz BW option; improved SFDR; pin comp with AD6657 AD6643 Dual 11 bit 250MSPS w/NSR AD6672 Single 11 bit 250MSPS w/NSR; 5x5 CSP 75MHz AD6657 Quad 14 bit 185MSPS Yellow shade means these are in development. The clear circles are products in definition stage. Input from customers is welcome!. AD9650 Dual 16 bit 105MSPS Highest SNR (375mW/Ch) AD9648 fam. Dual 14b 125MSPS 100mW/ch – Par LVDS AD9253 fam. Quad/Octal 14b 125MSPS 100mW/ch – Par LVDS 20-60MHz Newly released Sampling 95 95

AD9434 12-Bit, 370/500 MSPS, 1.8 V ADC KEY SPECIFICATIONS
A/C Performance at 500Msps SNR = 65.2 Ain up to 250 MHz ENOB of fIN up to 250 MHz SFDR = 75 fIN up to 250 MHz LVDS SDR at 500 MSPS (ANSI-644 levels) 1.2 GHz full power analog bandwidth On-chip reference, no external decoupling required Programmable via SPI Integrated input buffer and S/H Programmable input voltage range: 1.18 V to 1.6 V, 1.5 V nominal Low power dissipation MSP—LVDS SDR mode Single 1.8 V supply operation SPI Port for configuration and control Selectable output data format (offset binary, twos complement, Gray code) Power down Output Test patterns Output timing adjustments Key Benefit Lower Power and High Sample Rate Pin Compatible with AD9230: 12-bit 250Msps AD9434 Package 1k 56-lead LFCSP AD : $125 AD : $90 Sampling Final Release Now March2011

AD9484 8-Bit, 500 MSPS, 1.8 V ADC KEY SPECIFICATIONS
A/C Performance at 500Msps SNR = 47 Ain up to 250 MHz ENOB of fIN up to 250 MHz SFDR = 83 fIN up to 250 MHz LVDS SDR at 500 MSPS (ANSI-644 levels) 1.2 GHz full power analog bandwidth On-chip reference, no external decoupling required Programmable via SPI Integrated input buffer and S/H Programmable input voltage range: 1.18 V to 1.6 V, 1.5 V nominal Low power dissipation MSP—LVDS SDR mode Single 1.8 V supply operation SPI Port for configuration and control Selectable output data format (offset binary, twos complement, Gray code) Power down Output Test patterns Output timing adjustments Key Benefit Lower Power and High Sample Rate Pin Compatible with AD9230: 12-bit 250Msps Package 1k 56-lead LFCSP AD : $36 Sampling Final Release Now March2011

AD9467 – 16-Bit, 250 MSPS ADC KEY BENEFITS Outstanding Performance
High effective resolution at high sampling rate. KEY BENEFITS Outstanding Performance SNR = 75.5 Fin = MSPS SFDR = 90 Fin = MSPS SFDR = 92 Fin = MSPS SFDR = Fin = 160MSPS Excellent Linearity DNL = ±0.5 LSB (16-bit Typical) INL = ±3.5 LSB (16-bit Typical) LVDS DDR at 250 MSPS (ANSI-644 levels) 900 MHz Full Power Analog Bandwidth Power Dissipation = 1.32W 2.0V p-p to 2.5 Vp-p (default) Input Voltage Range Integrated input buffer External Reference supported Data Clock Output Provided 1.8V and 3.3V supply operation User Controls via Serial port interface Output Data Format Option Clock Duty Cycle Stabilizer Output Test patterns Power down modes HSC Overview Slide NOTE: 75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS 92 dBFS at −1 dBFS 100 dBFS at −2 dBFS 100 dBFS SFDR at 100 MHz at 160 MSPS 60 fs rms jitter Excellent linearity at 250 MSPS DNL = ±0.5 LSB typical INL = ±3.5 LSB typical 2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable) Integrated input buffer External reference support option Clock duty cycle stabilizer Output clock available Serial port control Built-in selectable digital test pattern generation Selectable output data format LVDS outputs (ANSI-644 compatible) 1.8 V and 3.3 V supply operation Temp Package -40°C – +85°C 72 pin 9x9mm Pb-Free LF-CSP Sampling Final Release Now Oct 2010

Product-Market Focus Core Markets Core Products ADI Confidential
Industrial Control Instrumentation Communications Portable Consumer Medical ATE Core Markets Core Products Industrial Solutions Bipolar DACs Precision DACs Dense DACs Nano DACs POTs Digital Multiplying DACs High Voltage DACs DDS ADI Confidential

AD5791 – Product Description 1uS Update, 1ppm DAC in 0.29cm2
1ppm Linearity 20bit Resolution 1ppm DNL & INL <1ppm Noise 0.025ppm Low freq Noise 9nV√Hz Wide Band Noise 1µs Settling Time ¼ to ¾ scale settling <1ppm Drift Offset Drift 0.05ppm/°C Low Glitch 0.4nV·s (5v); 1nV·s (10v) Output Spans +5V to ±10V ± 7.5 V to ±15 V Power Supply Resolution DNL INL Refresh Rate Interface Package Temperature 20-Bit 1PPM 1PPM 1µs SPI 20-TSSOP -40°C to +125°C 101

AD5791 Functional Block Diagram
±10V ±5V +10V +5V Feedback & “Matched Resistors” – Eases Drive Amp Selection + - A1 Input Shift Register and Control Logic DAC Reg 20-Bit DAC ±10V ±5V +10V +5V Power-On-Reset & Clear Logic ±10V ±5V +10V +5V

AD5791 Ideal for MR Imaging Applications Exceeds All Digital-to-Analog Converter Requirements for MRI MRI DAC Requirements: High Resolution/Accuracy 18-20 bits minimum for ≥3.0Tesla Systems Low Noise Lessens unwanted image artifacts thereby reducing the need for multiple MRI scans Low Drift Eliminates system calibrations Fast Settling Time Reduces scan time HV Gradient Coil Supply Control 20-Bits Magnet AD5791 1ppm DAC Digital Control If you move to Slide 14 you can see how the performance features of the AD5791 satisfies and exceeds All D-A Converter Requirements for MRI. Firstly, the High Resolution and Accuracy enables fine control of the magnetic gradient in high-field-strength applications (greater than or equal to 3.0T which is very common today),…..this results in superior image clarity, resolution and contrast. The ultra low Noise performance lessens unwanted image artifacts and lowers image-error rates thereby reducing the need for multiple scans. This speeds up the overall exam time and ensure that healthcare facilities can effectively treat more patients within a shorter time period. The Low Drift performance eliminates system calibrations and reduces the need to take the system off-line. Additionally, the Fast Settling Time reduces system response time and enables more scans to be performed in a shorter time period, shortening waiting times, and improving patient access. Finally, the small 29cm square footprint reduces overall cost and board Space and enables smaller cabinets – and thus smaller and more portable MR systems. So in summary – for MRI Systems PRACTITIONERS & PATIENTS - The AD5791’s 1 ppm system performance level gives radiologists the superior image clarity, resolution and contrast they need, allowing them to see smaller anatomical structures than ever before, which in turn leads to better and faster diagnostic outcomes. FOR the SYSTEM ENGINEER- THE AD5791 greatly simplifies system design. The DAC's performance level makes a single DAC architecture possible and does away with the design effort needed to combine multiple DACs and to develop the calibration circuitry needed to keep the system up and running. HV Gradient Coil Amp -HV RF Coil AD5791 Exceeds All MRI DAC Requirements Amp ADC Patient

AD5422 Current Source & Voltage Out DAC – 16 Bit, 4-20mA , ±10V
4/20/2017 AD5422 Current Source & Voltage Out DAC – 16 Bit, 4-20mA , ±10V Single Channel Configuration for Isolated PLC Systems 16-Bit Resolution IOUT 4mA-20mA, 0mA-20mA or 0mA-24mA ±0.01% FSR TUE 4ppm/oC Output Drift VOUT 0-5V, 0-10V, ±5V, ±10V 10% over-range 0.01% FSR TUE 3ppm/oC Output Drift Force & Sense capability Functionality Internal 5V 10ppm/oC Reference Diagnostics/Fault detection Output Loop compliant AVDD-2.5V Related Products AD5412 12 Bit Version Similar Functionality Resolution Features Temp Range Interface Power Supply Package 16-Bit Fault Detection -40oC to +85oC Serial 12V to 48V or ±12V to ±24V 24 – TSSOP 40 - LFCSP

AD5422 – Sample Application
4/20/2017 AD5422 – Sample Application - Distributed Control System Sensor i/ps : Thermocouple, RTD, Loadcell, Pt100, Gas, Flow etc Measures climate, gas, light intensity, Flow rate, temp etc. XTAL Sensor Sensor Sensor Sensor Mux LCD Display Standard 4 to 20mA Communication or bipolar Voltage Output ADuM DSP AD779x AD719x ADC ADuM Vout to 4-20mA Circuitry DAC Reference AD5422

AD5755 – Quad 16 bit V/I DAC with Dynamic Power Control
16-Bit Quad Industrial V/I Output DAC with Thermal Control IOUT Range: 4-20mA, 0-20mA or 0-24mA 0.06% TUE Accuracy 5ppm/oC Output Drift VOUT Range: 0-5V, 0-10V, ±5V, ±10V 20% Over-range. 0.04% TUE Vsense + & Vsens - Functionality Flexible Digital Interface On-chip Diagnostics Integrated per channel DC-DC for Dynamic Power Control Internal 5ppm/oC Reference Housed in 64 – LFCSP (9 x 9mm) Related Products AD5735 AD5755-1 12 Bit Version Similar Functionality 16bit version HART Compliant Vsense + Sampling , Release Spring 2011

AD5755 Block Diagram Leverages ADI Core Technologies
Smart and High- Efficiency Dynamic Power Control (DPC) Precision 16-bit DAC Precision Linear Signal Processing 4 X Output (V/4-20mA) Channels Diagnostics I/P O/P No Calibration Required (Full Channel Spec)

AD5764 – ±15V 16-Bit Accurate Quad DAC - Bipolar Cores
4/20/2017 AD5764 – ±15V 16-Bit Accurate Quad DAC - Bipolar Cores KEY BENEFITS Small: 32 lead TQFP Full 16 Bit Accuracy 1 LSB DNL 1 LSB INL(C-Grade) 2/4 LSB INL (B/A-Grade) Ease of Application On chip reference buffers Bipolar output generated from single 5V Ref Output control during power on/off Output clamped to 0V during power on/off Resolution Output Channels INL, Max Interface Package 16 Bits ± 10.5V 4 1 LSB SPI 32-TQFP Released Status Related Products AD5764R AD5744/44R AD5762R Same Functionality 16 bit, Quad Internal 10ppm Reference. 14 Bit, Quad 44 R – Int 10ppm Ref 16 bit, Dual Internal 10ppm Reference

AD5541A/2A –16-Bit ±1LSB, 1ɥs, DAC Upgrade to AD5541/42
KEY FEATURES 16-Bit ±1LSB INL & DNL Low Noise 12nV/rtHz 3V and 5V Operation VDD = 2.7V to 5.5V Fast 1µs Low Glitch: 1.1nV-sec VLOGIC Pin with 1.8V operation Gain Error TC: ±0.1ppm/ºC Zero-Code Error TC: ± 0.05ppm/ºC Bipolar Zero TC: ±0.2ppm/ºC (AD5542) 50MHz SPI compatible Interface Increased Interface Flexibility Related Products AD5512A AD5551/52 12 – bit Similar Functionality Feedback resistors for bipolar outputs 14 bit version 8 & 14 ld SOIC Resolution Feature Temp range Interface Power Supply Package 16-Bit 1µs Settling -40oC to +125oC Serial 2.7V to 5.5V 8 & 10 – LFCSP (41) 10 – MSSOP (41) 10 &16 – LFCSP (42) 16 – TSSOP (42) ADI Confidential

AD5664R –16-Bit Quad nanoDACTM in 3x3 LFCSP package
KEY BENEFITS High Performance 16-Bit Resolution, 12LSB INL 10-MSOP / 3x3 10-LFCSP ….and also includes an on-chip 5ppm/°C Reference 70% Space saving over competition Ideal for base-stations, optical transceivers Reference and non reference options Dual Configuration also available A Member of the nanoDAC family Resolution Output Channels INL, Max Interface Package 16-Bits 0-5 V 4 ± 12 LSB SPI 10-LFCSP/MSOP AD5644R/24R AD5663R/43R/23R AD5664/24 & AD5663 Same as AD5664R except 14/12-Bits Resolution Same as AD5664 except 16/14/12 Bits Dual Configuration No on-chip reference Quad and Dual configuration ADI Confidential

AD5291/2 – 256/1024 Tap, 30V or ±15V, 1% R-Tol, 20-TP Wiper Memory digiPOT+
KEY FEATURES Single-Channel, 256/1024 Tap resolution 20 kΩ, 50 kΩ and 100 kΩ Nominal Resistance Calibrated 1% Nominal Resistor Tolerance +4.5V to +30V Single-Supply Operation ±4.5V to ±15V Dual-Supply Operation 20-TP – 20-Time Programmable Memory Applications Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage to current conversion Programmable filters, delays, time constants Programmable power supply Sensor calibration Temp 1K -40°C to 105°C AD5291: $2.29 AD5292: $2.62

High Speed DAC Category Overview
Signal Image Sample Rate, Integration, Performance Frequency (GHz) FDAC MixMode RF DAC Up to 2.5GSPS w/ Interpolation & NCO + MixModeTM Frequency (GHz) FDAC Frequency (GHz) IF FDAC TxDAC+ ® : IF Class Signal Processing DACs Up to 1.25GSPS w/ Interpolation & NCO The High Speed DACs are divided in three categories to represent the differences of use and performance of the products. The first category is TxDAC which are also called Base-band DAC. This category of DAC have a maximum update rate of 500Msps with resolution between 8 and 16 bits. These DACs do not have interpolation. When representing the DAC output signal in the frequency domain with the signal of interest in blue while the images are in green, you can see that these DACs can generate signals between DC and Fdac/2 with a maximum signal bandwidth of Fdac/2. The line in red represent the expected image rejection required with this DAC. The second category of DAC is TxDAC+ or IF class DAC. This category of DAC have a maximum update rate of 1.25Gsps with resolution between 8 and 16 bits. In majority, these DACs have interpolation and come in dual or quads. When representing the DAC output signal in the frequency domain, these DACs can generate signals between DC and Fdac/2 with a maximum signal bandwidth limited by the data interface. Today our fastest interface is an LVDS interface which can achieve 500Msps or 400MHz of bandwidth. As you can see from the frequency domain plot, the interpolation allows to relax the DAC image rejection filter specification by pushing the images further away. These DACs therefore allow to generate signals at IF but also allow easier filtering. Finally, the last category of DAC is RFDAC. These DACs have an update rate up to 2.5Gsps and depending on the product might have interpolation and NCO. Due to the high update rate, these DACs allow to generate wide bandwidth signals which is useful in designing multi-band transmitter. Another feature of these DACs is the mix-mode. In mix-mode, these DACs can generate signals in the 2nd Nyquist zone, as shown in the top figure or even in the 3rd Nyquist zone up to 3GHz. This feature allows RFDAC to output signals directly into RF. Frequency (GHz) 0.5 1.0 1.5 2.0 2.5 3.0 FDAC TxDAC® Low Power Base Band DAC 8-16b ; Up to 500MSPS

Baseband-Class TxDAC® High Performance / Low Power Transmit DACs
Released Baseband-Class TxDAC® High Performance / Low Power Transmit DACs AD9747/46/45/43/41 16-8b, 250 MSPS CMOS Inputs 72p QFN (10x10) Dual AD9783/81/80 16-12b, 500 MSPS LVDS Inputs 72p QFN (10x10) Dual Higher Bandwidth AD9117/16/15/14 14-8b, 125 MSPS CMOS Inputs 40p QFN (6x6) Dual AD9707/06/05/04 14-8b, 175 MSPS CMOS Inputs 32p QFN (5x5) 2mA output current Single Small Footprint Low Power AD9717/16/15/14 14-8b, 125 MSPS CMOS Inputs 40p QFN (6x6) 2mA output current Dual

IF-Class Signal Processing TxDAC+®
Not Preferred Preferred IF-Class Signal Processing TxDAC+® CMOS Interface LVDS Interface AD9788/87/85 16-12b, 800MSPS Interpolation + Fine NCO 100p QFP (16x16) AD9122 16b, 1.25 GSPS Interpolation + Fine NCO 72p QFN (10x10) AD9125 16b, 1.0 GSPS Interpolation + Fine NCO 72p QFN (10x10) AD9146 16b, 1.25 GSPS Interpolation + No NCO 48p QFN (7x7) Dual DAC AD9148 16b, 1.0 GSPS Interpolation + Fine NCO 196b BGA (12x12) Quad DAC 114

RF-Class TxDAC® & TxDAC+® High Performance MixMode™ DACs
Not Preferred Preferred RF-Class TxDAC® & TxDAC+® High Performance MixMode™ DACs 1st Generation 2nd Generation AD9739 14b, 2.5 GSPS Single AD9736/35/34 14-10b, 1.2 GSPS 2x Interpolation Single AD9789 14b, 2.4 GSPS Highly Integrated Single All LVDS Inputs

MxFE® Roadmap Integrated Mixed-Signal Front-End
Not Preferred Preferred MxFE® Roadmap Integrated Mixed-Signal Front-End Part Tx Rx Package Resolution Fs AD9860 10b 128 MSPS 64 MSPS 128p LQFP (16 x 22) AD9861 200 MSPS 50 / 80 MSPS 64p LFCSP (9 x 9) AD9862 14b 12b AD9863 50 MSPS AD9963/61 12b/10b 130 MSPS 100 MSPS 72p LFCSP (10 x 10) 1st Generation 2nd Generation AD9863/2/1/0 AD9963/61 Low Power

Senior Field Applications Engineer
Cosimo Carriero Senior Field Applications Engineer Mobile:

Cosimo Carriero Analog Dialogue Seminar November 2011

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Cosimo Carriero Analog Dialogue Seminar November 2011

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