1. Understanding and Protecting Against Electrical Overstress (EOS) of Operational-Amplifiers
By Thomas Kuehl – Senior Applications Engineer
Precision Analog – Linear Applications Engineering
The presentation today will examine the issue of input electrical overstress. Simply, this implies a condition where potentials applied to the amplifier exceeds those of the normal specified operating range. Most circuit applications will never experience an input or supply overstress, but in those few cases where there is the potential for an overstress condition it is important to understand the performance or reliability implications.

2. This is your IC

3. This could be your IC after an electrical overstress event!

4. Presentation Subjects
ESD and EOS definitions
Amplifier input range
ESD models
Internal ESD and consequently EOS protection circuits
Amplifier EOS operating situations
External EOS protection

5. ESD and EOS: What’s the difference?
Electrostatic Discharge (ESD) – The transfer of electrostatic charge between bodies or surfaces at different electrostatic potential.
Electrical Over Stress (EOS) – The exposure of an item to current or voltage beyond its maximum ratings.
ESD
High voltage (kV’s)
Short duration event (1-100ns)
Fast edges
Low power
Out of circuit event
EOS
Low voltage >Vs
Longer duration event
Low power
In-circuit event
One of the most intuitively evident sources of electrical overstress is Electrostatic Discharge, ESD. An ESD event can take place when two bodies are at 2 different electrostatic potentials; often thousands of volts apart. If a conductive path is provided between the two bodies, a transfer of electrostatic charge can take place until charge neutrality is achieved.
The event usually takes place in a fraction of second; less than 100ns. An electrostatic EMF on the order of kilovolts can be reduced to zero during the brief charge transfer period. Current on the order of amperes may flow through the path if there is little opposition to current low. Remember:
i(t) = C∙ dV / dt
Decades ago semiconductor circuits fell victim to ESD events resulting in complete circuit failure, or even more hideous parametric degradation. However, since that time ESD has been well characterized, better understood and protection solutions implemented.
Input Electrical Overstress, EOS, is likely an unintentional application of an over-voltage typically outside the normal operating range and much longer in duration than an ESD event. An important point to keep in mind is that this is an in-circuit event, while ESD is usually an out-of-circuit event.
Unknowingly we may be relying on a device’s internal ESD circuits to provide protection during an EOS event as well.

6. Two very different environments
ESD
EOS
10V 0V
Internal ESD protection circuits are primarily intended for pre-assembly handling and assembly operations. Low impedance ground paths abound which can serve as discharge paths. But once the IC is installed in the PC board and interconnected to other components the likelihood that an ESD path exists is greatly diminished. There is every possibility that with proper ESD control and prevention that the internal ESD circuitry will never be exercised. That is a good thing!
However, there is the other possibility that a device input may be subjected to an EOS event while installed in the operating environment. And although the ESD circuitry may not be specifically designed for a particular EOS condition, there is a probability that it will come into play during the event.
This circuitry could provide a protective path for the input devices where no damage to the circuit ever occurs. Or, at the other extreme, it could be damaged and become a liability to the otherwise normally operating circuit.

7. The TI data sheet Absolute Maximum Ratings is a good place to check and assure EOS problems are avoided
When there is a concern whether a circuit operating condition may bring about an electrical overstress (EOS) condition the first place to check is the product data sheet Absolute Maximum Ratings table. This table provides information about the maximum voltage levels that may be applied to pins and may also include maximum currents as well.

8. Input voltage range of an op-amp+
+2kV–
+100V
ESD protect region
In-circuit max
positive ≈
Safe with Rs
OPA735 low
Drift CMOS
Op-amp
+5.5V
+5.0V
Pos Safe
Non-linear input
Pos rail
+3.5V
CMV input range *
Input
voltage 0V
-0.1V
-0.5V
Neg rail
Neg safe
Safe with Rs
The scale on the left side of the slide depicts the input range for the OPA735 CMOS op-amp. The linear response CMV region is stated as -0.1V to +3.5V. Exceeding these values by any appreciable amount will result in signal distortion.
Moving in the positive direction, from +3.5V to +5.5V, the input is still within a safe region, but signal linearity will suffer becoming increasingly worse. Note that the positive supply rail is +5.0V, so an input signal more than about 0.5V beyond this results in the positive ESD diode turning on. A hard turn on begins around +5.5V and a series input resistor must be added to limit the current. The input current is usually restricted to a value of 5 or 10mA. Failure to include the resistor will almost assuredly result in damage to the internal ESD diode if the current becomes too high.
The series resistor can be used to protect the input up to reasonable limits, tens of volts. But be aware the resistor will add noise to the overall circuit performance which may be objectionable from a performance stand point. Note in many applications this resistor is not included.
The series resistor is determined from the maximum applied input voltage, maximum input voltage rating and maximum current:
RSERIES = ( VAPPLIED (MAX) - VINPUT (MAX) ) / IINPUT (MAX)
Be sure to check both the positive and negative input regions. For the above circuit the negative input region will result in a larger value resistor.
In the realm of 100V or more the ESD circuitry is really in place to protect the device during an ESD event. It is not realistic to expect EOS protection at such high voltage levels.
Moving the input about 0.5V beyond the negative rail results in the negative ESD diode turning on. The same precautions as the positive case must then be observed. The remaining negative input conditions mirror those of the positive conditions.
-5.0V ≈
In-circuit max
negative
-100V–
-2kV
ESD protect region _
* Selected to limit input current to 10mA max.

9. ESD Stress Models
There are 3 different ESD generator models commonly applied when testing semiconductor ESD protection circuitry. They are the Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). All 3 boil down to a series RLC circuit, but the circuit values and pulse generator characteristics are much different for the 3 models. All 3 produce a short, but well defined ESD pulse that results in current levels comparable to those experienced during an actual ESD event.
ESD model R L C V
Human Body Model
HBM
1.5 kΩ
7500 nH
100 pF
≥ 2kV
Machine Model MM
20 Ω
750 nH
200 pF V
Charged Device Model
CDM
5 nH
2-10pF
200V - 1kV

10. Human Body model Rdut is the “on” resistance of an ESD
protection circuit
The first model, the Human Body Model (HBM) is intended to simulate an statically charged human touching an IC pin that has a current path to ground.
C1, L1 and R1 represent the charged human electrical properties. C1 holds the high voltage charge which in this case is established at 2kV. When contact is made, the equivalent of SW1 being closed, C1 discharges through L1, R1 and parallel combination of C2 and Rdut – of which the latter 2 components represent the path internal to the IC. The current is defined by the 2nd order differential equation for this circuit. Note that the current peak - Ipk, occurs quickly; under 25ns with a maximum value of 1.2 to 1.3 amperes. However, significant current continues to flow for hundreds of nanoseconds. The integrated power can be surprisingly high during this period and the protection circuitry must be capable of not only withstanding the high voltage associated with the ESD pulse, but also dissipating the power.
Although Rdut is represented by a 10Ω resistor, it is sometimes replaced with a 10V zener diode which exhibits a hard “turn on” characteristic at 10V. The dynamic resistance may be much less 10Ω’s.
When a device is characterized using the HBM ESD environment the test is conducted using multiple, increasingly large charge voltage levels. Usually the lowest test level used is 500V, which is then increased 500V until 2kV is reached. Testing may continue to the 3 or 4kV input level.
There are times when the semiconductor process may dictate that a lower starting voltage level be used, in which case it may be as low as 100V. On the other end, semiconductors that have I/O pins routinely exposed to manual, make and break connections may be tested with charge voltages as high as 15kV. HPA products are designed to withstand an HBM ESD voltage of 2kV.

11. Machine Model Rdut is the “on” resistance of an ESD protection circuit
The second model, the Machine Model (MM), was introduced by the Japanese semiconductor industry and was intended to be a more severe test than the HBM. The charge capacitor was made intentionally larger – 200pF, and the charge source resistance reduced to a very low value, 0 to 10Ω. This allows the ESD source to supply even greater currents than the HBM model.
Although this model was intended to represent machines associated with the end user electronic assembly, it is not intended to represent the handlers used in semiconductor final testing and handling. It may simulate the electrical stress from low impedance sources that are not necessarily ESD.
Notice that the charge voltage is 200V, instead of 2kV as with the HBM model. This is dictated by the fact that the current is only limited by the finite source resistance and the “on” resistance of the ESD protection circuit path. Higher voltage would result in dangerously high currents that would almost certainly damage even the most robust ESD circuits. For the example shown the peak current exceeds 2 amperes on the positive peak and then follows a damped pulse response from there. The entire event concludes in about 200ns, which is substantially less than the HBM event’s duration. That noted, it is important to recognize that the integrated power dissipation is higher and occurs in a shorter time period. Passing the MM test is usually a more difficult feat than than passing the HBM test. The MM test is conducted with a starting voltage of 100V, which is advanced 50V at time to 200V.
As was mentioned, the MM may actually be a better model of a low impedance, HV source, than an actual ESD source. Therefore, the MM qualification has been dropped by the US and Europe as a requirement. Only Japan continues to require MM qualification of products.

12. CDM - ESD by induction Rdut is the “on” resistance of an ESD
The third commonly employed ESD model is the Charge Device Model (CDM). It has come to replace the one-time popularly employed MM. This model is specifically slated to simulate the charge accumulated by an IC package, or piece of manufacturing equipment, as a device is processed through the final production operations.
The CDM charge voltage is set to 250V. The pulse width is very short; less than 400ps with extremely fast edges. Like the MM the series resistance is low. The device under test (DUT) model consists of the ESD protection “on resistance” and a small value series capacitor. The CDM model is a charged package model where the small capacitor is the die/package to the surrounding manufacturing environment capacitance. Therefore, the capacitance value depends on factors such as the die size, package size, dielectric characteristics and surrounding environment characteristics.
Once the ESD pulse is initiated the current rapidly rises to a value dependent on the said characteristics. The plot shows the resulting current waveform for different package capacitances; 2, 4 and 6pF. The capacitance value somewhat alters the peak current and settling time. For the example shown the peak current approaches 5 amperes, but note that the entire event is over very quickly - in less than 2ns.
Rdut is the “on”
resistance of an ESD
protection circuit

13. Common input/output ESD protection circuits
Input steering diodes
CMOS input/output protection
A commonly applied practice for protecting both bipolar and CMOS input and output pads involves steering diodes and an absorption circuit. Depending on the ESD pulse polarity one or the other diode will turn on and the current will be directed through the absorption circuit. This circuit is “off” when the IC is in operation, but momentarily turns “on” during an ESD event. It is intended to absorb the ESD event energy and then dissipate it as heat.
The Vcer clamp circuit relies on the breakdown of the NPN transistor for a positive going ESD pulse and diode conduction for a negative going pulse.
The third circuit is typical of one used to protect CMOS IC inputs and outputs. Although the schematic shows a simple series connected MOSFET-diode clamp at across the input to the ground bus, the physical layout of the IC has parasitic structures that form a true 4-layer, SCR device. SCRs have faster turn-on times than the simple breakdown connected MOSFET. The circuit has a secondary protection path consisting of some series absorption resistors and a clamp MOSFET for the input circuit.
Vcer input clamp
IC level SCR model is more complex

14. Supply clamp circuits ≈ NPN bipolar on high-speed process
The power supply clamp circuit is satisfied using a bipolar transistor or by a parasitic bipolar transistor inherent to an MOS device. The clamp transistor’s base-emitter junction is not forward biased (IB =0uA) rendering the device in a normally “OFF” state.
As the collector-emitter voltage is increased, the breakdown voltage (BVcer) is approached. The internal electric field intensities increasing to a level where electron-hole pairs are generated and current begins to flow between the collector and emitter. If the collector-emitter voltage is further increased the collector current rapidly increases until the point is reached where a “snap back” takes place. This is due to impact ionization and the resulting regenerative feedback. Beyond the snap region current again begins to rapidly increase.
If there isn’t another source of resistance in the transistor’s path to limit the current, it can increase to the point where the thermal regeneration results in excessively high temperatures and transistor melt down. Usually the emitter ends up spiking through the base and shorting to the collector forming a permanent short circuit. ≈
ON →
← OFF

15. NMOS parasitic bipolar transistor
Gate
Drain
(collector)
Source
(emitter) n
IDS n IC p
Isub
This is a cut away, side view of an NMOS clamp structure. The parasitic NPN transistor is revealed within the NMOS structure. In normal operation the parasitic bipolar does not function. However, under the previously described conditions, the device will latch in the on state.
Rsub
Sub (base)
P-sub/epi

16. A commonly applied ESD protection method for analog integrated circuits
Input protection
Output protection
ultra
low leakage
diodes
This is a typical ESD protection method for an analog circuit. Integrated diodes are connected from each input and the output pins back to each supply rail, V+ and V-. An internal series resistance may be placed in each input path to limit the current during an ESD event. This resistance may be a diffused element or simply the resistance of metal or poly interconnections.
The output protection devices may be larger area devices compared to an input protection device. Most op-amps have minimal resistance between the output devices and the output pin. Resistance in this path will limit output current and output voltage swing during heavier output current conditions.
The other protection element is an absorption device connect between the positive and negative supply pins. It is a large area transistor and if triggered on, it can handle the current directed to it by the input/output steering diodes and then dissipate the momentary energy release without damage. This transistor’s collector-emitter breakdown exceeds the maximum rated supply voltage for the device and should only turn “on” during an ESD event.
Power supply
absorption device

17. INA168 ESD cell layouts Input pin Supply clamp NPN transistor /
ESD2 N-sinker – BL
ESD1 NPN B-E
Supply clamp
NPN transistor /
resistor
Sections of the INA168 die layout are shown depicting the various ESD protection structures. The input diodes are structures ESD1 and ESD2. ESD1 is the input-to-positive supply diode consisting of NPN base-emitter. ESD2 is the input-to-negative supply diode comprised of an N-sinker and buried-layer to substrate structure. ESD7 and ESD8 are comparable to ESD1 and ESD2, respectively, but connected at the output pad.
The third section is that of supply clamp device consisting of a large NPN transistor. This device is slated to conduct during an ESD event, clamping the supply-to-supply voltage and absorbing and releasing the energy associated with the event.
Output pin
ESD7 NPN B-E
ESD8 N-sinker – BL

18. The ESD protection paths
V+ pin at GND
Vout at
GND
This example shows possible current paths to ground during an ESD discharge event. An ESD event most often takes place between 2 pins; one floating and the other at a much lower potential such as ground. Several paths exist here; from an input, through an ESD protection structure to ground.
ESD
pulse
source
V- pin at GND

19. Input overdrive may activate ESD protection circuits
This is an example of a simple follower circuit comprised of a low power, OPA364, CMOS op-amp. The intended, low frequency signal represented by VG1 is the desired transducer output.
If the transducer is located a distance from the amplifier and they are interconnected by cables, twisted pair wires or other lines, noise and/or transients can be induced from the surrounding environment. Transients may also be an artifact of the transducer connected to the amplifier.
VG2 illustrates an unintended transient source that is simply added, or rides upon the intended transducer output signal. The summed signal amplitude is sufficient to exceed the maximum specified input range for the amplifier. If sufficiently large, the ESD circuit may be activated by the input signal.
VG1 + VG2 sum may activate
ESD circuit on peaks

20. ESD cell paths may be activated during an EOS event*
T1 can become a near
short between supplies!
Intended
signal
Input
EOS
source
The current path created by an EOS event can be complex and somewhat unpredictable; more so at high frequencies where stray impedances become significant. The normally near-zero impedance power supply paths, which may be such at DC, may exhibit significant reactance at high frequencies.
A main consideration is that any of the paths through the device can safely withstand the current and voltages present during the event – while protecting the analog circuit. If they are incapable of doing so, they, or the analog circuit may be damaged due to the joule heating that takes place as the power is dissipated. *
*may no longer represent a near-zero impedance at high frequencies

21. A supply clamp transistor failure during resulting from an input EOS/ESD event
Vcer clamp
transistor
This is an actual application of a high-speed op-amp where the ESD clamp transistor was damaged by an EOS event. This problem was repeatable and devices could readily be damaged when a charged cable was connected to the BNC connector at the op-amp’s non-inverting input.
There were two conditions that would set the clamp transistor up for failure; 1) The circuit was powered by a “wall-wart” that didn’t have a on/off switch, 2) T1, the input termination switch, was not initially engaged, rendering the op-amp input in a floating state.
When a charged cable was connected to the input of the powered circuit, the EOS pulse would raise the supply rails to the point where the clamp transistor, T1, went into a BVcer condition and conducted. Because the supplies were continuously “on” T1 appeared as a near short between the supplies.
T1’s safe operating conditions were quickly exceeded resulting in extreme joule heating, melt down and destruction.

22. EOS-related CMOS operational-amplifier field failures
An example where EOS related failures were incurring in air conditioning units. The application of the CMOS operational amplifier was straightforward using a low voltage +5 V supply, but high voltage and high current is present in the application. The failed devices upon receiving failure analysis indicated a direct short between the supply pins. The devices had over heated, carbonizing the plastic molding compound and melting the die silicon.
TI quad CMOS operational amplifier failing unexpectedly in air conditioner application
TI FA report indicated the operational amplifier die had carbonized material on die and pin 4 (V+) to pin 11 (V-) short
EOS analysis of the customer application input and output ESD circuits did not reveal any likely candidates

23. EOS-related CMOS operational-amplifier field failures
20 Vpk EOS
on V+ line
A request for the Field Applications Engineers to observe and monitor the amplifier pins during the various operational cycles was made and provided
They found that a 20 Vpk pulse was appearing on the V+ line during operation of the air conditioner. The nominal supply voltage was +5 V
The EOS was causing either the supply-to-supply ESD clamp to break down, or voltage breakdown of the amplifier transistor structures
A higher voltage operational amplifier and a transient voltage suppressor on the V+ line were recommended
The TI Field Applications Engineers were able to identify that the CMOS operational amplifier was being subjected to a +20 V EOS pulse during a portion of the air conditioning unit’s operating cycle. The amplifier has a absolute maximum supply voltage rating of 7 V. The EOS level easily exceeded the breakdown voltage of internal CMOS devices and the ESD supply clamp.

24. Input current limiting by external series-R
Where does the 10mA
IOVERLOAD maximum originate?
A review of the TI-Tucson CMOS op-amp data sheets will yield numerous models recommend adding an input protection resistor to circuits where an over voltage might occur. This resistor is added to the circuit to limit the input current to a safe level. This current is referred to as IOVERLOAD and is the maximum continuous value the input circuitry can withstand without sustaining damage. The limit is established at 10mA. But where does this value come from?

25. Parasitic circuit latch testing
Latch testing of analog integrated circuits is a normal qualification requirement. The purpose is to identify parasitic semiconductor structures that may latch “on” when the input, output and power supplies pins are subjected to voltage impulses. Latched parasitic devices may lead to abnormal circuit operation or even destructive current paths.
One requirement of the latch test series is the Current Injection Test. During this test a particular I/O pin is subjected to a voltage pulse that is equivalent to the full, supply-to-supply voltage; 7.5V for the OPA348 example. The supplies pins are set to the nominal supply voltage and all other I/O pins are connected together at one supply rail voltage, then at the other. The pulse duration is less than 10ms. The current is limited to 150mA and should this value be reached the pulse voltage ceases to increase any further.
This sequence is conducted with the I/O voltage swept from the lower power supply rail voltage (0V) to the maximum positive voltage (7.5V) and from the upper supply rail voltage (5V) to the maximum negative voltage (-2.5V).
Once latch testing is completed the device is electrically tested. This is to establish whether the device remained undamaged, was impaired or electrically damaged.
As mentioned the input current is limited to 150mA. The ESD clamp diodes nearly always conduct first and limit the pulse voltage when it exceeds the rail voltage by about 0.6V. High-Performance Analog engineering has established that if the device survives the 150mA pulse event that the internal devices can safely withstand a maximum continuous current of 1/15th this value - 10mA.
Current injection
latch test
The continuous input overload current is set to < 1/10th
the JEDEC maximum latch test current (t ≤ 10ms)

26. Watch Vin during power up!
Iin excessively high
while supply ramps
There are applications where the input signal is present before the power supply voltage is applied to the amplifier. Such a scenario has the potential to damage the input ESD protection circuit if the current is limited to a safe value.
For illustrative purposes the supply is slowly ramped from 0V to 5V in 50ms, while the 3.5V input signal is applied just 5ms after the supply begins its ramp.
The problem with this scenario is the inputs are initially higher than the positive rail voltage, which turns on the positive ESD diode. This continues until the voltage difference between the supply and input is somewhat less than 0.6V.
If the input source has a low impedance and can deliver the current and there isn’t a source limiting the current, then a potentially harmful current could flow through the ESD diode.
Again, including the series input resistor will protect the input circuit from such damage.

27. Instrumentation amplifier input protection
The INA116, INA118 and some of the other 3-opamp instrumentation amplifiers have a JFET current limiting circuit in series with the inputs. This circuit protects the input from voltages as high as +/-40V. When the instrumentation amplifier is operated within the normal linear input range the JFET circuit appears as a low resistance in which the base or gate current flows.
When a large voltage, outside the linear range is applied to the input, the current through the JFET will increase but to a safe limit dictated by the FET “ON” characteristics. The internal ESD input diodes route the current to the supply rails.

28. Excessive differential input over-voltage
Possible occurrences
When operating an operational amplifier as a comparator
During slewing
Bipolar input operational amplifier
90%
Input-output
voltage difference
SR = 2.3V/us
Some situation arise where an amplifier’s inputs are subjected to a large differential voltage. This can occur when the amplifier is employed as a comparator, or when a large signal output slew takes place. As an example of the slewing case, a fast, 10V peak rectangular pulse is applied to the non-inverting input. The amplifier responds to the pulse by producing a linearly ramping output voltage whose characteristics are dictated by the amplifier’s limited slewing-rate, in this case about 2V/us.
During the slewing time, the time required for the output to reach the input pulse’s peak value, a large input to output voltage differential exists. Initially that value is 10V for the above example, but decreases after slewing is complete. Meanwhile the op-amp internal circuitry and feedback elements must handle that the current that flows during this period.
Modern bipolar input operational amplifier have a clamp protection circuit added to the input circuitry to prevent damage to the op-amp’s input stage.
10%
Plot for illustrative purposes only!

29. OPA277 input-to-input differential over-voltage protection
modern bipolar op-amps have input clamps
Iin
20mA
max
This simplified OPA277 schematic shows differential over-voltage protection circuit employed at the amplifier’s input. Two series diodes are connected between the bases of the differential input devices, T28 and T23.
For the moment, imagine that the series diodes are removed from the circuit. Unless a sufficiently large voltage is applied only the input bias current will flow into the input. However, if the applied voltage is large enough it will overcome the emitter-base forward voltage drop of T23 and the base-emitter reverse breakdown voltage, V(BV)EBO, of T28. Current would then have a path to flow via the feedback path to the output.
Exceeding the reverse breakdown of a transistor’s emitter-base junction has irreversible, detrimental affects on the transistor’s electrical characteristics which in turn degrades the op-amp’s input characteristics.
Including the series diodes clamps the base-to-base voltage at roughly 1.4V, and prevents the transistors from ever going into the reverse breakdown condition.
VG1 = 2VD + (Iin R1) + Vo
If VO = 0V, then:
Iin = (VG1 – 2VD) ∕ R1

30. Input overdrive of CMOS rail-to-rail IO chopper amplifiers
Back-to-back clamp diodes are inherent and internal to the chopper switch structures
When Vin exceeds a Vcm maximum Vo is forced to an output rail level
The op-amp is forced outside of its linear operating range
The feedback loop collapses and an input differential voltage develops
One clamp diode or the other becomes forward biased and the input bias current can increase tremendously
This may limit the use of this type of operational amplifier as a comparator
Modern CMOS chopper operational amplifiers typically have low input bias current under normal operating conditions. The OPA330 used as an example in this slide has a typical input bias current of ±200 pA. However, under an input overdrive condition the current can increase by many decades depending on the overdrive voltage level.
The internal chopper switches shown at the input of the simplifier OPA330 circuit contains inherent diode structures. These diodes normally have a tiny differential offset voltage across them which is close to zero volts. Thus, they are essentially turned off and have little affect on the amplifier’s nominal input bias current.
However, should the amplifier input voltage be driven beyond one of the common mode rails its output will be driven to one output rail or the other which for the OPA330 is a few tens-of-millivolts from either supply rail. That causes the amplifier in a region of non-linear operation. When that happens the loop collapses and a non-trivial differential voltage develops between the amplifier inputs and the chopper switches and their inherent diodes.
The differential voltage will forward bias one diode or the other and the current flowing through the diode will add to the input bias current. The greater the differential voltage the larger the input bias current will become. It takes only a few hundred millivolts of diode forward bias to increase the input bias current to microampere levels and higher.

31. Operational-amplifiers
Overload Recovery
Auto-zero CMOS
Operational-amplifiers
Positive
input
+50mV
0mV
OPA335
Av = -50V/V 0V
Negative
output
≥ -2.5V
Negative
input
A-to-D converters have been tested for overload recovery for years to assure that the digital output does not change to an unusual code condition when the input is overdriven. This test also provides the time required by the converter to recover once the input overdrive condition is removed. Similar testing is being applied to auto-zero, CMOS op-amps to assure that they do not misbehave during an overdrive event or after it has ceased.
The overload recovery test is conducted with a small signal input and a high gain such as -50V/V. This is to avoid slew rate limiting in the input stage. Both positive and negative overload conditions are tested.
The input voltage is stepped such that the output moves off the rail to 0V. The time required for the output to achieve 0v (± offset) is the recovery time. For the OPA335 rail-to-rail amplifier shown this is about 20us. This measured result closely coincides with the plots shown in the data sheet.
One may be inclined to think that because this is an inverting circuit that the summing junction will always be very close to 0V. But that is only the case for an ideal op-amp. The summing junction of the non-ideal op-amp will momentarily follow the input source because of internal delays, finite response time, and a loss of loop control when the output is saturated.
0mV
-50mV
≤ 2.5V
Positive
output 0V
Vin ≥ Vs / Gain

32. Output inversion during input overdrive
VG1
-0.5V
+4.5V
VM1 0V
Some operational amplifier models exhibit an output inversion characteristic that accompanies an input overdrive. Most op-amps models do not exhibit this characteristic, but when one does precautions should be taken to prevent the input from being overdriven to the output inversion point.
For the example shown the input is being driven about 0.5V below the negative supply rail. The output level inverts momentarily from the negative rail to the positive rail. The duration of the output inversion worsens the more the input is overdriven. Obviously this is an undesirable condition that can have destructive consequences if the load is electromechanical in nature; a motor, actuator, etc.
This particular example circuit can be remedied by placing a reverse-biased Schottky diode between the non-inverting input and negative supply rail.
Output inversion was covered extensively in the 2005 AFA deep dive conference. For more information refer to the conference proceedings.
Output inversion

33. Supply pin over-voltage protection
Smoothing a transient
with an RLC filter
Transient amplitude effectively reduced
Ringing dependent on RLC values and load R
Amplifier PSRR becomes important
A switching power supply may be corrupted with high-frequency transient energy. This is especially true for switching power supplies that use high-frequency MOSFETs to perform the switching function. The voltage “spikes” provide the potential for an over voltage condition across the amplifier’s power supply pins. Should the supply voltage exceed the voltage breakdown of the internal circuits a direct current path can be created between the supply pins, leading the device failure.
Protecting the device from a power supply transient can be accomplished with an RC or RLC circuit. This may be done unknowingly by a common on-board EMI/RFI filter. However, the circuit’s response can vary tremendously depending on the RLC constants and the load characteristics.
The simple RLC circuit is connected to a load resistance in the accompanying slide. The +5V supply has a 5V, 1us transient imposed upon it, equivalent to a 10V spike. This well exceeds the maximum supply voltage for most low voltage CMOS processes. The 1K load resistance simulates an amplifier drawing a supply current of about 5mA.
It can be seen from the response that the RLC circuit integrates the spike into a sinusoidal response riding on the +5Vdc level. The slight over voltage should not pose a problem for the device.
Besides the unknowns associated with the RLC circuit combination in many cases, the supply voltage does undershoot. This will affect the op-amp output offset. The op-amp’s PSRR will help minimize the change in the output offset, but it is a notable error.

34. Supply pin over-voltage protection
Transient voltage suppression (TVS) diode
6.8V- 550V reverse standoff voltage
Unidirectional & bidirectional models
Ppk = 1.5kW (10 x 25C
Cj ≥ 20V
Littlefuse no. 1.5KE6.8, etc.
A better, more predictable transient suppression method is to use a Transient Voltage Suppressor (TVS) on the supply line. It is similar to a zener diode, but is specifically designed to withstand very large transient current and peak power.
The Littelfuse 1.5KE series of TVRs is available with a reverse standoff voltage from 6.8V to 550V, in both unidirectional and bidirectional polarities. The peak power PPK capability is 1500W, for ten 100us pulses.
An obvious advantage is the fast voltage clamping characteristic with no undershoot of the supply voltage.
The model and response shown in the slide are actually for a zener diode as no TVR models exist in the TINA simulation software. However, the response should be quite similar to that shown.

35. Supply pin over-voltage protection
Features
Multilayer ceramic construction
Operating voltage range VM(DC) = 5.5 to 120V
Non-repetitive surge current (8/ 20us)
Non-repetitive energy (10/ 1000us)
response time <1ns for zinc oxide
Inherent bidirectional clamping
Wider temperature range and flatter response
than solid-state TVS
An alternative to the zener type TVS is the varistor. It is similar to the conventional junction type varistors except it utilizes ceramic technology based semiconductor materials. One example is a zinc oxide varistor.
They have advantages compared to the conventional zener in that the TVS operates over a wider temperature range with a flatter voltage vs. temperature response and provides inherent bidirectional clamping. They are available in relatively low capacitance (<100pF) versions and with very fast response times (<1ns).

36. Externally connected input protection devices
Transient voltage suppressors
For CMOS, bipolar and SiGe
Features:
Available from 5.6 to 18V
DC working voltage ≤ 18V
AC working voltage ≤ 14V
Turn-on-time <1ns
Repetitive spike capability
watch
capacitance
Here is another type of Transient Voltage Suppressor that is intended for input protection. The device can be selected such that the breakdown voltage is just a few volts above the input operating voltage.
Any protection device attached to the input of an analog IC must be understood relative to the application. Such devices can degrade the overall circuit performance either from a DC, AC or both stand points. However, if the circuit can tolerate the leakage current, added capacitance or other parametric degradation then these added devices can offer an increased level of EOS protection.
uA J A pF

37. Externally connected input protection devices
A Transient Voltage Suppressor (TVS) may be employed as input protection when higher voltage transients occur. A problem with many types of TVS products is that they can exhibit tens or hundreds of picofarads, of capacitance. This might lead to a condition where the amplifier becomes unstable.
A pole in the frequency response is normally created by the feedback resistor (Rf) and the amplifier input capacitance (Cin). Normally the phase shift associated that pole is not enough to significantly degrade the phase margin. Adding the large TVS shunt capacitance (Ctvs) to the input summing node lowers the pole frequency and increases the phase shift around the loop. In some cases the phase margin is degraded to the point where the circuit becomes unstable.
A technique for reducing the capacitance added by Ctvs is to add a junction diode in series with the TVS. Small signal diodes such as the INA4448 silicon diode, or BAS40 Schottky diode, have low equivalent series capacitance. When the capacitance of the diode is placed in series with the capacitance of the TVS the overall capacitance is less than that of the smallest device capacitance. In the example circuit the TVS 15pF capacitance has been reduced effectively to 2.5pF by the addition of a diode having 3pF of junction capacitance.
The 1N4448 and BAS40 can handle forward current of a couple hundred milliamperes. Likely Ri will limit the current to safe levels.

38. Externally connected input protection devices
Schottky diodes provide
enhanced input protection
Features:
Forward voltage VF ≤ 380mV, IF = 1mA
Forward current IF = 200mA max (cont.)
Leakage current * IR ≤ 100nA, VR = 30V
Diode capacitance Ctot ≤ 5pF, VR = 0V
The Schottky diode has a lower forward voltage than a similarly rated silicon junction diode at a given current level. For instance, the small-signal Schottky diode will have a forward voltage closer to 250 to 300mV at 1mA, compared to something on the order of 550 to 650mV for the junction diode operating at the same forward current.
When Schottky diodes are placed from the amplifier input to the supply rails, they shunt the internal junction diodes. They turn on earlier than the internal diodes and will carry the majority of current during an overload condition.
The internal ESD diodes may only be rated 10mA continuous, whereas, the external Schottky diodes are rated at 200mA continuous current (TA = 25°C).
* A small-signal silicon diode (IN4148) will likely turn on at lower voltage than the internal
ESD silicon diode and may exhibit lower leakage current than a Schottky diode.

39. Externally connected input protection devices
It is good idea to include external EOS protection devices in a circuit that might be subject to EOS conditions. Doing so relieves the internal circuits of having to withstand voltage and/or current levels that they were not originally intended to handle.
The protection scheme shown in the slide covers just about any EOS scenario that the amplifier might be subject to. Adding resistance in series with the inputs, output and even the power supply lines helps limit the maximum current that can flow during an EOS event. However, that may not always be practical; especially, for the output and supply lines. The resistance will add undesirable voltage drops.
When forward biased external small-signal Schottky diodes will direct input EOS current around the internal ESD protection circuits, to the supply lines. If, for example, SD1 is turned on by a EOS voltage that exceeds the positive supply rail voltage, SD1 will direct the EOS current to the +V pin. What happens next depends on how the +V supply handles the EOS current. Usually that supply cannot sink current. That would cause V+ to rise. However, in this circuit a TVS or zener diode Zs1 is present at the V+ pin. Once its turn-on threshold voltage is reached it will conduct and clamp the voltage at a safe level directing the EOS current to ground.
Also Zs1 and Zs2 provide reverse supply protection and a supply current path if the opposite supply is disabled (floats). In this case Zs1 or Zs2 becomes forward biased and conducts the device supply current.
Circuit designs sometimes arise where an external voltage may be applied to the operational-amplifier output before the supplies come up to voltage. This can occur when the output has a pull-up connected to an external voltage. If protection isn’t provided this may be an instance where current will flow through the output ESD protection. Again, added Schottky diodes will direct the current to the supply pin protection paths.

40. An important point about added protection devices in the signal circuit
Protection components such as transient voltage suppressors (TVS), diodes and zener diodes all exhibit capacitance even when biased off
The capacitance will vary to some extent with the voltage applied across the protection device
Most often the capacitance does not have a linear capacitance to voltage relationship (voltage coefficient)
This non-linear capacitance to voltage relationship may increase distortion in the protected circuit
It will be most evident in a very low THD circuits, but may not degrade performance significantly

41. Power Line Communications (PLC) EOS environment – IEC61000-4-5
Open-circuit surge pulse test
4kV, 1.2us tfront, 50us thalf-value
Operational-amplifiers are finding widespread application in Power line Communication (PLC) circuits. The operational amplifiers used in both the receiver and transmitter functions must be interfaced with AC power lines commonly operating with voltage levels of 24V, 110V, or 220V, and sometimes higher. Although the operational-amplifiers can be readily interfaced with these voltage levels by employing step-down transformers and blocking capacitors they must also be able to withstand the high-voltage (HV) transients that may, at times, be present on the power lines. These transients are often classified as being equivalent to those of AC equipment switching on the line, or a result of a lightning strike down the line.
IEC describes both an open-circuit voltage test and closed-circuit current test. The open-circuit voltage test is commonly applied to PLC equipment. The 4kV voltage pulse is illustrated in the slide. Commonly HV clamping is applied before the isolation transformer that leads to the receive and transmit operational amplifier circuits. Despite this primary protection nearly always additional protection must be included on the secondary side to prevent damage to the operational-amplifiers.

42. PLC – EOS protection Actual protection scheme will vary with application and layout
High voltage MOV
and low-voltage TVS
clamping
Fast rectifier and
Schottky clamps
This circuit shows protection circuitry added at both the primary and secondary sides of a PLC transmitter output circuit. A metal oxide varistor (MOV) provides the first line of protection clamping the HV pulse peaks riding on the AC line. The clamped AC pulse is then coupled to a bidirectional transient voltage suppressor (TVS) which further clamps it and drops it to a lower voltage. The step-down transformer provides some further reduction of the transient voltage.
It would appear that successfully clamping the transient and keeping the peak voltage to something on the order of 6V, or 12V would keep the operational-amplifiers down stream safe, but that often isn’t the case. Circuit layout, non-ideal components and the speed of the transient suppressors may not be ideal and remnants of the transient may get through to the active components.
Additional components are added to the secondary side of the circuit to provide greater protection. The ESD cells of operational-amplifiers are never intended to be turned on by an EOS event. However, they are often sensitive to not only over voltage but may turn on in response to very fast pulses on the power line. If the ESD cell turns on it is likely to remain on and conduct high levels of current until either the source of current is removed, or the cell is damaged. Thus, it is best to prevent the ESD cells from ever being turned on.
The high-speed rectifier diodes and Schottky diodes are intended to turn on very quickly and prevent the ESD cells from ever turning on. The passive components plays a role as well limiting the current that can flow in the amplifier’s output circuit.
The internal output ESD
cell is unlikely to withstand
the open-circuit HV pulse
- latching is probable

43. In Summary
EOS and ESD events may activate ESD protection but result in different outcomes
Internal ESD circuits may sufficiently handle EOS
Be aware of unique EOS situations such as power up and input slewing
External EOS protection circuits will be required if device damage is likely to occur without it