1. Layout Considerations of Non-Isolated Switching Mode Power Supply
Presented by
Henry Zhang
Power Business Unit
Linear Technology Corp.
Oct. 2003
3863

2. 1. General Discussion
3863

3. Plan of the Power Supply Layout
In the system, power supply should be close to
its load devices.
Cooling fan should be close to the supply to limit
its component thermal stress.
Select the right number of layers and copper thickness
The large size passive components (inductors, bulk
capacitors) should not block air flow to power MOSFETs
Power supply designer should always works closely with
PCB designer on the critical layout design
3863

4. 4-Layer PCB – Layer Placement
Layer #1 – Power Component
Layer #2 – GND
Layer #3 – Small Signal
Layer #4 – Small signal / controller
Desired
Place ground or DC voltage layer between power layer and small signal layer
Undesired
Layer #1 – Power Component
Layer #2 – Small Signal
Layer #3 – GND
Layer #4 – Small signal / controller
Power
Signal
GND
PCB capacitance
High current loop
Pulsating current loop
3863

5. 6-Layer PCB - Layer Placement
Undesired
Desired
Layer #1 – Power Component
Layer #1 – Power Component
Layer #2 – Small signal
Layer #2 – GND plane
Layer #3 – GND plane
Layer #3 – Small Signal
Layer #4 – DC Voltage or GND plane
Layer #4 – Small Signal
Layer #5 – Small signal
Layer #5 – DC Voltage or GND plane
Layer #6 – Power Component / Controller
Layer #6 – Power Component / Controller
DC power and ground planes function as AC reference planes.
As a general rule, the reference planes of a multi-layer PCB design should not be segmented.
3863

6. Small Signal Traces on Reference Layer
If the small signal traces have to be routed on the reference layer, use short traces with proper direction:
Reference Layer
current
Desired
Undesired
PWM IC
MOSFET
Coupled AC
current return path
3863

7. Copper Thickness and PCB Resistance
Copper resistivity (/cm):
T – Copper temperature in oC
Resistance of copper:
Example: 1 Oz copper (1.4 mil thick), 0.5 inch wide (500mils), 2 inches long (2000mils), at 70 oC with 20A current:
Rcopper = 2.3 m, Vcopper=46mV, Ploss=0.92W
High current application - Recommend 2 oz or higher for external power layers
3863

8. 2. DC/DC Converter Power Stage Layout
3863

9. Buck Converter Current Paths
Continuous Current
VIN+
ESRin
Vin
Cin ST SB LF Co R Vo D
ESRo SW
PGND
Pulsating Current
CHF
High dv/dt node
Identify the continuous and pulsating current paths
Pay special attention to pulsating current paths and high
dv/dt switching node
3863

10. Parasitic Inductance in the Current Paths and Example Layout (Buck)ST SB D SW
VIN+
PGND
Trace Inductance
CHF
VIN+ SW LF
PGND D ST SB
Minimize this loop area
0.1uF – 10uF
Ceramic Capacitor
CHF
Minimize loop between HF capacitor and MOSFETs
It is desirable to keep CHF, top FET and bottom FET on the same layer
Use multiple vias for power connection
3863

11. Boost Converter Current Paths
Continue Current
High dv/dt node
Pulsating Current LF D SW
Vo+ Vo
VIN
CIN
CHF Co SB
Load
PGND
Minimize the critical pulsating current loop on the output side
3863

12. Output Noise Decoupling Capacitor (Boost)
PGND
Minimize this loop area
Vo+ SW
0.1uF – 10uF
Ceramic Capacitor SB D
CHF LF
(a)
(b)
Minimize the critical pulsating current loop on the output side
3863

13. 12V-to-2.5V/30A LTC3729 Supply Layout Example
VIN+ (12V)
VO+ (2.5V)
LF1 QT
CIN
SW1
LTC3729 Co QB
GND
GND Co
SW2
VIN+
VO+ (2.5V)
(a)
3863

14. Noise Problem @ Heavy Load
Io = 0A
Io >= 13.3 A
vSW1
iLF1
vSW2
(b)
(c)
3863

15. Input Ceramic Capacitors Make a Difference
Add
1uF/16V/X7R
(a)
Io = 0A
Io = 30 A
vSW1
iLF1
vSW2
(b)
(c)
3863

16. Land Patterns of Power Components
Use wide / short copper trace for power components
Use multiple vias for inter-layer connections
Avoid improper use of “thermal relief”
Minimize resistance and inductance
Desired C
R/C/D/L
FET + -
Connected Via
Undesired
Connected Via
3863

17. 3.3V/40A LTC3729 Layout Design Example
High Current Trace
3863

18. Examples of a 2-Phase DC/DC Power Stage
VIN Vo
SW1
SW2
GND
QT1
QB1
QB2
QT2
CHF1
CHF2 L1 L2
Rsen1
Rsen2
Cout D
Internal
GND Layer
CIN
Air Flow Vo
SW1
GND
QT1
QB1
CHF1 L2 L1
Rsen2
Rsen1
Cout D
CIN
Vin
Internal
GND Layer
3863

19. Separation of Input Paths Among Supplies
Undesired
Desired
RPCB1
RPCB
DC/DC #1
Cin
Cin
DC/DC #1
DC/DC #2
RPCB2
PGND
PGND
PGND
DC/DC #2
PGND
3863

20. 3. Layout of the Controller and MOSFET Drivers
3863

21. Decoupling Capacitor and Separated Grounds
LTC3729
RUN/SS R
SEN1+
TG1
RSENSE C R
SEN1-
SW1 C
EAIN
SGND Island
BG1
ITH
INTVCC C C
SGND
PGND
VDIFF
BG2
PGND
Plane
SW2 R
SEN2-
TG2
RSENSE C R
SEN2+
Shortest Distance
3863

22. Signal Ground and Power Ground
Components connected to following pins use SGND:
- EAIN, RUN/SS, ITH, UVADJ, PHAMD, PLLIN, PLLFTR, FCB, CLKOUT
Components connected to following pins use PGND:
- BOOST, +5V, PGND
The SGND and PGND can be tied together underneath the IC.
3863

23. QFN Package Controller Layout
SGND
PGND
INTVCC C
Vias
LTC3731
SGND
PGND
Example
Exposed SGND pad must be soldered to PCB
Use multiple vias to connect SGND pad to both SGND and PGND layers
PGND pin also connects to SGND pad underneath the IC
3863

24. Automatically coupled AC
Gate Driver Traces
LTC3729
Route together QT
BOOST1
TG1
SW1
INTVCC
BG1 QB C
PGND
Automatically coupled AC
ground return current
PGND
Plane
3863

25. IC Signal Trace Width
Following are the trace width values we use in Polyphase demo board:
20 mils – TG, BG, SW
25 mils - +5V, Vcc, PGND
15 mils – Current sensing, feedback, ITH, etc.
10 mils – Short traces that directly connected to IC pads
3863

26. Current Sensing Traces
RSENSE LF
Vo+
Direct trace connection.
Do NOT use via.
LTC3729
This via should NOT
touch any other internal Vo+
copper plane. R
SENSE- C R
SENSE+
Kevin sensing of the current signal
Keep current sensing traces away from noisy traces / copper area or use ground layer for shielding.
3863

27. Sensitive Traces and Noisy Traces
Most sensitive traces:
Current sensing (SENSE+/-), EAIN, ITH, SGND
Sense+ / - traces for each channel should be routed together
With minimum trace spacing. The filter capacitor should be as close to
IC pins as possible. The filter resistor should be close to filter capacitor.
Keep sensitive traces away from noisy traces.
Sensitive traces:
Vos+/-, DIFFOUT, PLLFTR, CLKOUT
CLKOUT is a sensitive trace but it is also a noisy trace. So keep it away from
other small signal sensitive traces.
Most noisy traces:
SW, TG, BOOST, BG
Keep them away from sensitive traces.
Avoid overlapping between large SW copper area and sensitive traces in two
neighborhood layers.
- For each channel, route the SW and TG trace together with minimum space.
3863

28. Summary - Layout Checklist
Plan of the layout:
Location of the supply / load / bulk capacitors
# of layers / layer placement / copper thickness
Power stage layout:
Power component placement
Power component land patterns
Identify pulsating current paths
Decouple capacitor close to MOSFET
Short / wide copper trace and multiple vias for high current
Controller circuit layout:
Decoupling capacitors close to pins
Separate signal / power grounds
Current sensing
De-couple sensitive and noisy traces
Gate driver traces
Select proper trace width
3863