1. 1 Oscillation Control in CMOS Phase-Locked Loops A Thesis Presented to The Academic Faculty by Bortecene Terlemez PhD Candidate in School of ECE 11/04/2004 Dr. Martin Brooke, Advisor Georgia Institute of Technology School of Electrical and Computer Engineering Microelectronics Research Center Atlanta, GA 30332-0269

2. 2 Outline  PLL history and fundamentals  PLL Architectures  Oscillation control in CMOS charge-pump PLLs  Single-ended control for multi-GHz charge-pump PLLs  Design of a low-noise 1.8 GHz charge-pump PLL  Design of a low-noise 5.8 GHz charge-pump PLL  Differential control for multi-GHz charge-pump PLLs  Performance comparison  Pulse-stream coded PLLs  Summary/Conclusions/Contributions

3. 3 Brief Phase-Locked Loop (PLL) History  1932: Invention of “coherent communication” (deBellescize)  1943: Horizontal and vertical sweep synchronization in television (Wendt and Faraday)  1954: Color television (Richman)  1965: PLL on integrated circuit  1970: Classical digital PLL  1972: All-digital PLL  PLLs today: in every cell phone, TV, radio, pager, computer, …  Clock and Data Recovery  Frequency Synthesis  Clock Generation  Clock-skew minimization  Duty-cycle enhancement

4. 4 Phase-Locked Loop  Phase Detector (PD): This is a nonlinear device whose output contains the phase difference between the two oscillating input signals.  Voltage Controlled Oscillator (VCO): This is another nonlinear device which produces an oscillation whose frequency is controlled by a lower frequency input voltage.  Loop Filter (LF or LPF): While this can be omitted, it is always conceptually there since PLLs depend on some sort of low pass filtering in order to function properly  A feedback interconnection: Namely the phase detector takes as its input the reference signal and the output of the VCO. The output of the PD, the phase error, is used as the control voltage for the VCO.

5. 5 PLL Architectures

6. 6 PLL Architectures – Linear PLL vs Digital PLL  No frequency tracking  Input amplitude dependency  Nonlinear phase detector gain  No frequency tracking  Duty-cycle sensitivity (can be solved by edge triggered phase detector

7. 7 PLL Architectures – All-digital PLL  Lower sensitivity to digital-switching noise  Easier to transfer a design between technologies  Faster lock-in times  Higher complexity  Bigger die size  No true frequency synthesis (in general)

8. 8 PLL Architectures - Charge Pump PLL  Zero phase error (ideally)  Unlimited capture range (ideally)  Stability: Two poles at the origin  Zero in LPF  Auxiliary charge pump

9. 9 Oscillation Control in Charge Pump PLLs  Charge Pump PLL: contemporary applications  PFD and charge pump nonidealitites: 45% of the output phase jitter 1  Phase-Frequency Detector  Possible dead zone  Possible duty-cycle dependency  Possible unbalanced output generation  Charge Pump  Possible current asymmetry  Possible current leakage 1 V. Kaenel, D. Aebicher, C. Piguet, and E. Dijkstra, “A 320 MHz 1.5mW @ 1.35 V CMOS PLL for microprocessor clock generation,” in Journal of Solid-State Circuits, Vol. 31, No.11, Nov. 1996.  Clock skew in Clock/Data Recovery  Reference spur in Frequency Synthesis

10. 10 Phase-Frequency Detector - Behavior  Three-state device  PLL capture range  Maximum operating frequency: orthogonal inputs  Reset pulse  Too short = dead zone  Too wide = VCO control perturbation

11. 11 Charge Pump - Behavior Effective charge pump requirements:  Equal charge/discharge current at any CP output voltage  Minimal charge-injection and feed-through (due to switching) at the output node  Minimal charge sharing between the output node and any floating node, i.e. MOS switches at off position  Iup: charging current  Idn: discharging current  S1, S2: switches

12. 12 Single-ended control for multi-GHz charge-pump PLLs Design of a low-noise 1.8 GHz charge-pump PLL

13. 13  0.18μ TSMC CMOS  Differential outputs  Reset pulse = 0.2ns Phase-Frequency Detector - Design  Maximum frequency ≈ 600 MHz  Significant power dissipation above 100 MHz VDD=1.8V

14. 14 Single-Ended Charge Pump – Design  No charge sharing  No charge injection Replica Biasing

15. 15 Differential VCO with Single-Ended Control Saturated Gain Stage with Regenerative Elements Delay Stage : C.H. Park, and B. Kim, “A Low-Noise, 900-MHz VCO in 0.6-  m CMOS,” IEEE J. Solid State Circuits, vol. 34, pp. 586-591, May 1999.  Delay control by varying latch strength  Two sets of inputs for multiple-pass architecture  Tuning range control by varying M3 and M4 sizing

16. 16 Differential VCO with Single-Ended Control 9-Stage Multiple-Pass Loop  Auxiliary loops nested inside main loop  Frequency Improvement  Effective stage delay reduced  Noise Improvement  Slew rate increased

17. 17  Current-mode logic dividers: 1/2 to 1/64 of actual frequency  Current-mode logic buffers  DTOS: Differential to single-ended conversion  Driver chain  Turn-off circuitry to reduce cross-talk Differential VCO with Single-Ended Control Testing Issues

18. 18 Differential VCO with Single-Ended Control Layout

19. 19 Differential VCO with Single-Ended Control Simulation vs Measurement  VCO Range  Simulation: 1.16 – 1.93 GHz  Measurement: 1.10 – 1.86 GHz

20. 20 PLL with 9-stage ring VCO VCO Range (MHz)1120 - 1860 Lock-in Range (MHz)124.4 – 128.5 Internal Freq. (MHz)1180 - 1840 Division Ratio16 VCO Gain (MHz/V)770 I CP (μA)100 Open-Loop Phase Margin 81 Closed-Loop BW (KHz)625.5 RMS jitter (ps)1.7 Phase Noise (-dBc/Hz)116 1.8 GHz Low-Noise PLL Measurement Summary  Off-chip LPF: flexibility in testing

21. 21 Single-ended control for multi-GHz charge-pump PLLs Design of a low-noise charge-pump PLL for maximum frequency

22. 22 Differential VCO with Single-Ended Control 3-Stage Multiple-Pass Loop  VCO Range  Simulation: 5.18 – 6.11 GHz  Measurement: 5.35 – 6.11 GHz

23. 23 Differential VCO with Single-Ended Control Phase Noise for the 3-Stage Multiple-Pass Loop Measurement Simulation: SpectreRF Power Spectrum at ¼ Output of the 3-Stage Ring Power Spectrum at 5.79 GHz center frequency  Simulation: -99.5 dBc/Hz @ 1 MHz offset from ~6 GHz central frequency  Measurement: -99.4 dBc/Hz @ 1 MHz offset from ~6 GHz central frequency

24. 24 5.8 GHz Low-Noise PLL Measurement Summary PLL with 3-stage ring VCO VCO Range (MHz)51620 - 5930 Lock-in Range (MHz)166 - 182.5 Internal Freq. (MHz)5310 – 5840 Division Ratio32 VCO Gain (MHz/V)793 I CP (μA)100 Open-Loop Phase Margin 73.4 Closed-Loop BW (KHz)248.4 RMS jitter (ps)2.6 Phase Noise (-dBc/Hz)110

25. 25 Differential control for multi-GHz charge-pump PLLs

26. 26 Differential Charge Pump – Design  Output linear range (0.315V, 1.390V)  Differential outputs: FST and SLW

27. 27 Charge Pump – Common-Mode Feedback (CMFB)  Sampled data CMFB  CMFB transconductance gain: 40µA/V  CMFB bandwidth: 3KHz  CMFB phase-margin: 76º 100µA  Capacitors  DC voltage stability  Diodes  No effect on operation  Discharging metal during the etching process

28. 28 Charge Pump - Layout 150 x 130 µm 2

29. 29 Charge Pump – Post Layout Simulation  High output resistance  No charge sharing  Decreased charge injection

30. 30 Differentially Controlled LC Oscillator - I  Differential fine tuning: Accumulation mode MOS varactors  Digital coarse tuning: MiM capacitors  Three-turn inductor  2.4 nH, 1.7mm, Q~9.5  Thick top metal  Frequency goal: 2.5GHz Accumulation mode MOS varactor

31. 31 1/16 output fo = 157.8 MHz PN @100KHz = -83.8 dBc/Hz Differentially Controlled LC Oscillator - II

32. 32 PLL – Test Setup  Stable nested loops  CMFB BW ≈3KHz << Loop BW ≈200KHz << Reference ≈150 MHz 2.5 GHz PLL with LC VCO Output lock-in range (MHz)2402-2518 Input lock-in range (MHz)150.1-157.4 Division ratio16 C 1 (nF)10 C 2 (pF)50 C 3 (pF)50 R 1 (Ω)680 R 2 (Ω)1500 Phase margin54.92 PLL bandwidth (kHz)194.36 Output RMS jitter (ps)3.5 Phase noise @ 1MHz offset (-dBc/Hz)123

33. 33 PLL - Measurement  Phase lock @ 2.5 GHz internal frequency  Phase Noise @ 1MHz offset from 2.5 GHz: as low as –123 dBc/Hz Reference ½ Output

34. 34 Prototype Chip in 0.18μm TSMC CMOS  Analog Layout Techniques  Common centroid topology  Stacked parts with dummy components  Guard rings  Routing  Matched and short busses  Decoupled parallel analog and digital lines  Complimentary digital signals crossing analog buses  Power  Analog and digital supplies merging as close to the pad as possible  Wide supply busses at the top metal  Pads  Electrostatic discharge protection within the custom designed analog I/O pads

35. 35 PLL Performance Comparison

36. 36 Single-Ended vs Differential Control  For a given frequency range V dd K VCO  Increased K VCO causes a higher sensitivity to the control line perturbation  For V ctrl = V m cosω m t  Differential Control Line  Doubles Dynamic Range to drop the spur level by 50%  Common mode rejection lowers the spur levels

37. 37 PLL Measurement Summary PLL at 1.8 GHzPLL at 5.8 GHzPLL at 2.5 GHz Control path single-ended differential VCO type9-stage multi-pass ring3-stage multi-pass ringLC VCO range (MHz) 1120-18605160-59302392-2525 Output lock-in range (MHz) 1180-18405310-58402402-2518 Input lock-in range (MHz) 74-115166-182.5150.1-157.4 VCO gain (MHz/V) 77079368 Division ratio 163216 Charge-pump gain (μA/rad) 11.14 C 1 (nF) 10 C 2 (pF) 50 C 3 (pF) 50 R 1 (Ω) 680 R 2 (Ω) 1500 Phase margin 68.6673.3854.92 PLL bandwidth (kHz) 529.58248.37194.36 Output RMS jitter (ps) 1.72.63.5 Phase noise @ 1MHz offset (-dBc/Hz) 116110123 Power (mW) 112505

38. 38 PLL Performance Comparison - I Maximum frequencies of published PLLsPhase noise versus maximum frequency

39. 39 PLL Performance Comparison - II Reported output jitter vs measured jitterReported normalized jitter vs measured jitter

40. 40 PLL TypeOscillation control path RMS phase jitter (ps) clean supply voltagenoisy supply voltage 1.8 GHzsingle-ended1.760 5.8 GHzsingle-ended2.650 2.5 GHzdifferential3.520 Clean vs Noisy Supply Voltage  Increase in jitter  Single-ended: 20-35 times  Differential: 6 times Periodic cycle-to-cycle jitter in noisy environment: significance of the control line noise

41. 41 Control Line Noise Reduction

42. 42 PLL Phase Noise Improvement - I  ↑ Temperature → ↑ Leakage ≡ Loss of lock at low frequencies  Solution: Multiple reset pulses in lock: up’, dn’  Solution: Adaptive multiple pulses in lock: up’’, dn’’

43. 43 PLL Phase Noise Improvement - II  Best case phase skew for  I CP = 70 µA  I LEAKAGE = 0.01 I CP  I CP modulation by CMFB: up to 30µA Static Phase Error Improvement

44. 44  M = 8  ~6dB improved output spur level  M = 32  ~20dB improved output spur level PLL Phase Noise Improvement - III

45. 45 Oscillation Control Summary in Charge Pump PLL  Periodical disturbance of the VCO control line  Process, voltage, and temperature (PVT) variations of the LPF components  Large area consumption by LPF components  Limited acquisition time  Analog control drawbacks determined by CMOS trends  Reduced linear range (decreasing supply voltage)  Significant leakage and weak-inversion currents (decreasing feature size)  Power supply and substrate noise (increasing integrity)

46. 46 Digital Control and Analog Oscillator  Immune to current leakage  Immune to supply/substrate noise  Tolerant to process variations  Semi-custom loop design  Monitoring of the internal loop states  Quantization noise introduced by the DAC Precision in oscillation control

47. 47 Pulse-Stream Coded Phase-Locked Loop

48. 48 Pulse-Stream Coded Phase-Locked Loop A novel method to render digital control: Phase/frequency comparison coded by pulse trains REF VCO DN UP VCO LeadsIn PhaseVCO Lags Dual Pulse-Stream PFD : Single Pulse-Stream PFD : REF VCO DIR MOD VCO LeadsIn PhaseVCO Lags

49. 49 A Simplified Pulse-Stream Coded PLL Prototype Single Pulse-Stream PFD :  0.18μ TSMC CMOS  Highly parameterized for testing basic characteristics  3-stage current-controlled oscillator  Active load differential pair stages  4-bit shift register

50. 50  Control 1: pulse width (1-1.6ns)  Control 2,3: delay (0.2-1.5ns)  Control 4: DAC step current  Control 5: CCO bias (100-200 MHz) A Simplified Pulse-Stream Coded PLL Prototype Control Signals :

51. 51  Control line characteristic  Frequency modulated reference  VCO lagging= current increase  VCO leading= current decrease A Simplified Pulse-Stream Coded PLL Prototype  Slow frequency tracking  Equally weighted control word  No phase lock due to very low resolution  Low number of bits  Equally weighted control word Simplified psc-PLL :

52. 52 Next Generation Pulse-Stream Coded PLL

53. 53  Monotonic binarily-weighted DAC and Counter  Faster capture  Higher resolution  Larger area Next Generation Pulse-Stream Coded PLL Quantization noise:  CCO gain= 100 KHz/μA  Tuning range= 100 MHz

54. 54 Single-Pulse Train PFD - Behavior MODIFY output Overall (MODIFY + DIRECTION) Response Discrete Characteristic

55. 55 Single-Pulse Train PFD - Implementation Gated oscillator  Pulldown strength  Low: big dead zone  High: noise sensitive operation  Low dead zone (80ps)  High power dissipation in lock (1.4mW)  Dead zone is a random variable t dead-zone,min < t dz < t dead-zone,min + T clk (1-duty cycle)  Low dead zone when output negative edge is utilized (70ps)  Low power dissipation in lock (20μW) sptPFD1sptPFD2sptPFD3

56. 56 Truncated UP/DOWN Counter - Implementation Counter Length (bits)Minimum T CLK (ps) 4570 5700 81200  Manchester-like carry look ahead adder Worst case propagation delay for 8-bit UP/DN counter

57. 57 DAC and CCO - Implementation  After continuous time VCO characterization, number of bits can be determined by:

58. 58 Pulse-Stream Coded PLL - Stability F(z): digital filter m: number of short pulses that would fit within a reference period T Root-locus plot for F(z) = 1/ (1 - z -1 )Root-locus plot for F(z) = (1 – 0.5z -1 )/ (1 - z -1 ) UNSTABLESTABLE FOR

59. 59 Pulse-Stream Coded PLL – Control Line at Lock

60. 60 PLL Design Procedure

61. 61 Conclusions  Basics of PLL operation were shown in a unique control centric flow  Single-ended CPPLLs with ring VCOs were designed and tested for low-noise multi-GHz applications that previously required CPPLLs with LC-VCOs  Design of a low-noise 1.8 GHz CPPLL  Design of a low-noise 5.8 GHz CPPLL  An exceptionally performing differential CPPLL was implemented with a unique charge pump and a unique CMFB scheme  Physical design considerations were summarized for low-jitter PLLs  The significance of the control line noise at lower frequencies was addressed along with possible solutions  A novel method for digitizing the control line was described: Pulse-Stream Coded PLL

62. 62 Future Research  Limits of a single-ended PLL design when used along with a voltage regulator  The differential control with the unique CMFB scheme can be utilized to drive higher-Q oscillators to note top-notch measurements  The control line noise reduction techniques can be further studied along with various test structures  Pulse-stream coded PLLs can be considered in dual-loop PLLs as coarse-tuning blocks

63. 63 Questions