1. Information Theory Based Parametric Network Consolidation Team Dark Knight Akhil Singhvi Anup Ganesh Avinash Varma Sushrith Hegde Vishaal Nagaraja

2. Motivation Electricity consumption of network links > Electricity consumption of the United Kingdom(2011) Fiber optics, copper cable Reduce power consumption of network links. Source: Opportunistically reduce link capacity to save energy Lingwen Gan, Anwar Walid, Steven Low Caltech, Bell Labs

3. Packet flow Vs Energy Capping the packet flow to 5 packets/sec will save 0.9 J or 64.28% of Energy [2] Source: International Journal of Computer Science & Information Technology (IJCSIT) Vol 3, No 4, August 2011 Packets/Sec Energy Consumption(J) 50.5 201.4

4. Packet Encrypting Decrypting Encoding Decoding Processor on NetFPGA Power Measuring Unit Power Mgmt. Unit System Overview Source: Information theoretic measures for power analysis – Diana Marculescu, Radu Marculescu and Massoud Pedram Node1 Node2 Node3 Node4

5. Processor Power Measuring Unit Power Management Unit Threshold Output Queues Packet > Threshold Packet < Threshold Controlling Pkt Flow Power Monitoring

6. OUPUT PORT LOOK UP INPUT ARBITER FIFO 1 FIFO 2 OUTPUT QUEUES OUTPUT ARBITER CORE #1CORE #2 P1 P2 T1 T2 T3 T4 T1 T2 T3 T4

7. PROCESSOR FEATURES 5 stage MIPS pipeline Custom ISA Custom Compiler 4 Threads: Fine grain Threading NO Hazard Detection Unit or Forwarding Unit Saved resources Achieved Parallelism

8. PC-0 MUX INST. MEM ALU ID/EX Register FIFO/SRAM Branch PC3_next=Branch Thread_sel DEMUX Thread_Sel_next Multi-thread Processor EX/MEM Register MEM/WB Register PC-1 PC-2 PC-3 PC2_next=Branch PC1_next=Branch PC0_next=Branch Control Unit Reg Bank 0 Reg Bank 1 Reg Bank 2 Reg Bank 3 IF/ID Register thread0 add $1,$2,$3 thread1 j 10 thread2 lw $2,10($0) thread3 sw $2,10($0) thread0 add $3,$2,$3 $2=1, $3=1 $2=1, $3=2 2 2 1 1 1 1

9. Future Work Use of sophisticated encryption/decryption techniques. Threads to be used for additional functionalities. Implementation as ASIC Scale frequency Scale Voltage

10. Evaluation Logic functionality Check and Bug Analysis Rectify Design Compare With The Software Results

11. PROJECT TIMELINE Phase Description Date Single Core Processor with Multi Threading 04/07/2014 Multi Core Processor with Multithreading Hardware Accelerators Design Simulation Hardware Accelerators Individual Implementation Integration of Hardware Accelerators with Multicore Processors Evaluation of the System ( Software ) 04/14/2014 05/05/2014 04/21/2014 04/28/2014 05/12/2014 Completed In Progress Completed In Progress Status

12. THANK YOU !

13. Appendix-1 Power Measurement Power is proportional to Activity factor Frequency Reference: Probabilistic Modeling of Frequent Value Bus Encoding Scheme for Low Power Computation by Mehta, K.K. ; Kowar, M. ; Sharma, H.R. Advance Computing Conference, 2009. IACC 2009. IEEE International

14. Appendix-2 Applications Disaster recovery in data center. Security applications like video surveillance. More applications

15. Appendix-3 Analysis Capping the packet flow to 5 packets/sec will save 0.9 J or 64.28% of Energy International Journal of Computer Science & Information Technology (IJCSIT) Vol 3, No 4, August 2011 PERFORMANCE EVALUATION AND IMPACT OF WEIGHTING FACTORS ON AN ENERGY AND DELAY AWARE DYNAMIC SOURCE ROUTING PROTOCOL Jihen Drira Rekik, Leïla Baccouche and Henda Ben Ghezala RIADI-GDL laboratory, ENSI National school of computer sciences Manouba University, 2010 Manouba, Tunisia ] Packets/Sec Energy Consumption(J) 50.5 201.4

16. APPENDIX -4 Power Saving Within A Processor Major power consuming blocks in a processor are Memory, Register File, and ALU. Techniques used to reduce: Loopback Mux to reduce the bus transitions.

17. Appendix -5 Packet Flow Encryption Bus Encoding Processor Power Measuring Unit Power Management Unit Output Queues Threshold Packet Application Packet Encrypted Encoded

18. REFERENCES [1] Opportunistically reduce link capacity to save energy Lingwen Gan, Anwar Walid, Steven Low Caltech, Bell Labs