# Switching Power Supply Design: EMI Reduction

## Presentation on theme: "Switching Power Supply Design: EMI Reduction"— Presentation transcript:

Switching Power Supply Design: EMI Reduction

© 2011 National Semiconductor Corporation.
AGENDA Introduction – EMI Overview Noise Sources Identification Minimize EMI Generation by Layout Protect Sensitive Circuits From Noise Conducted EMI and EMI Filters Transcript: So, the agenda for this presentation, I'll start with an introduction of EMI problems in switch mode power supply, and then, how to identify the source of the noise in such topologies, then how to reduce the noise generation by PCB layout. And at the same time, how to protect the sensitive circuits on the same board from the noise, and then, I will cover briefly conducted EMI and the EMI filter. After this section, there will be an isolated and a high-power density PowerPoint design prepared by Youhao Xi. Summary © 2011 National Semiconductor Corporation. 2

 AGENDA Introduction – EMI Overview EMI in SMPS Definition Standard 
Noise Sources Identification Minimize Noise Generation by Layout Protect Sensitive Circuits from Noise Conducted EMI and EMI Filters Summary Definition Standard EMI in SMPS So, the first part of my presentation is an introduction. I will talk about the definition of the EMI, the standards, and the EMI problems in switch mode power supplies.

What is EMI & EMC? (Electromagnetic Interference) EMI unwanted coupling of signals from one circuit to another, or to system coupling via conduction through parasitic impedances, power and ground connections Conducted EMI: Radiated EMI: unwanted coupling of signals via radio transmission EMC (Electromagnetic Compatibility) An electrical systems ability to perform its specified functions in the presence of EMI generated either internally or externally by other systems EMI stands for electromagnetic interference. They are unwanted coupling of signals from one circuit to another or to the whole system. It has two major parts. One is conducted EMI. One is radiated EMI. Conducted EMI is coupled via conductions through the parasitic impedance, the power, and ground connections. Radiated EMI are coupled through radio transmissions, and EMC stands for electromagnetic compatibility. It stands for electrical systems' ability to perform its specified functions in the presence of EMI generated by internally or externally by the other systems,

EMI/EMC Standards EMC Standards vary by… Region Application usage
US = FCC Europe = CISPR = EN Application usage Consumer Medical Automotive What standards do we use FCC part 15 B CISPR 22 = EN 55022 The standards can vary by the region, by the application, so even two customers who are trying to use the same IC, they can apply totally different standards. So pay attention to special region and applications of a particular customer. And the standards we usually apply for our power supply is FCC part 15, sub-part B, and CISPR 22, which is the same as EN 55022, 5

EMI/EMC Standards Organizations
United States Electrostatic Discharge Association (ESD) Federal Communication Commission (FCC) Institute of Electrical and Electronic Engineers (IEEE) Institute of Interconnecting and Packaging Electronic Circuits (IPC) National Institute of Standards and Technology (NIST) International Society for Measurement and Control (ISA) National Standards System Network (NSSN) Society of Automotive Engineers (SAE) International Telecommunication Industry Association (TIA) Underwriters Laboratories, Inc (UL) US Standard Developing Organizations (ANSI) International European Committee for Electrotechnical Standardization (CENELEC) European Telecommunications Standards (ETSI) Institute of Electrical and Electronic Engineers (IEEE) International Electrotechnical Commission (IEC) International Organization for Standardization (ISO) International Special Committee on Radio Interference (CISPR) International Telecommunication Union (ITU)

Links EU EMC Directives: EU EMC Standards List (24 Feb 2011): FCC Rules (Title 47 Telecommunications, Part 2): FCC Rules (Title 47 Telecommunications, Part 15) Information Technology Equipment (ITE): FCC Rules (Title 47 Telecommunications, Part 18) Industrial, Scientific, & Medical Equipment (ISM): FDA Inspection and Compliance (Medical devices are exempt from FCC regulations):

Conducted vs. Radiated Emission Limits
FCC/CISPR Conducted Emission Limits FCC/CISPR Radiated Emission Limits Measured at 10m We showed the two most commonly used standards in our power supply design for both conducted and radiated in this slide. So, the CISPR and FCC standards are pretty close to each other, and CISPR is stricter than the FCC in the radiated specs. Class B is even more restricted than Class A. So, we trying to design our power paths as Class B, so that it can be used by all the customers in different regions, Conducted limits ends at 30Mhz Radiated limits start at 30Mhz If you fail conducted you will probably fail radiated. FCC and CISPR standards the same FCC and CISPR standards somewhat different FCC B (consumer) much more stringent than FCC A (commercial, industrial, and business) 8 8

How Does Noise Show Up in the System?
NOISE SOURCE Emissions ENERGY COUPLING MECHANISM Conducted Electric Fields Magnetic Fields Radiated Low Frequency Low, Mid Frequency, LC Resonance High Frequency SUSCEPTIBLE SYSTEM Immunity

Engineering Approach To Mitigate EMI
NOISE SOURCE Unwanted Emissions ENERGY COUPLING MECHANISM Conducted Electric Fields Magnetic Fields Radiated Identify Significant EMI Sources Figure Out EMI Coupling Paths EMI Filters Shielding Add EMI Filter / Snubber / Shielding Engineer Circuit Layout To Mitigate EMI So, as power engineers, what should we do to reduce the problem? We shall start with identifying the source of the noise, and then, figure out the path of the noise transmission. Then, use the proper PCB layout to reduce the noise generation and the transmission. If these are not good enough, we can add some EMI filters, add some snubbers, and some additional shielding to add further protection to the susceptible systems. SUSCEPTIBLE SYSTEM

SMPSs Are Big Generators Of Radiated And Conducted Emissions
Switch Mode Power Supply Supply LOAD Due to High power High di/dt on the switches and diodes Fast transients (voltage and current) Not generally enclosed (not shielded) Parasitic inductance and capacitance in current paths Causing Noise Conducted to Supply and / or Load Interfere with circuits in the same system Interfere with other systems Switch mode power supplies are generally big generators of radiated and conducted emissions. Due to its high-power, high di/dt on the power switches, fast transitions, and the fact that they are not generally enclosed. This is exacerbated by the parasitic inductance and capacitance in the current paths. Switch mode power supplies can also generate large conducted emissions that might make it back to the supply or the load, and compromise their operation. 11

Electrically Small Loop Antennas
Electro Magnetic Field Energy is *: f: frequency of interest (Hz) A: loop area of the current path (meters squared) I : Current magnitude at the frequency of interest (A) r is measured distance between source and receiver (meters) This comes from Henry Ott's EMI reduction techniques. It claims that the electromagnetic field energy is proportional to the square of the frequency. And also, it's proportional to the loop area enclosed by the current paths and proportional to the current magnitude at the frequency of interest and the inverse proportional to the measured distance from the source of the noise. So, it comes to a conclusion from here that to reduce the noise generation, we could reduce the switching frequency. We could reduce the high-frequency component in the di/dt current transition or we can reduce the high-frequency current loop area. *Henry Ott’s classic Noise Reduction Techniques in Electronic Systems

Theory Behind EMI Mitigation by PCB Layout
Any Current must go from a source of energy and they must RETURN to the same source Self Inductance Voltage Spike Reduce loop area reduces L B fields cancel each other if current return path is close to current path First of all, a current. A current always has to come from a source of energy, and they must go back to the same source. So, there will always be a current loop, and the self-inductance of the current loop is proportional to the area enclosed by the current loop. If there is di/dt current transition exists in the current loop-- a voltage spikes is going to be generated, and the voltage spikes is proportional to its self-inductance and proportional to the di/dt. If we can reduce the loop area similar to the picture shown at the bottom, you can see that the loop area is largely reduced. So, the self-inductance can be smaller, and the voltage spikes can be reduced. Also, if the current return paths can be very close to the current paths, the B field generated by the two opposite direction current can be almost canceled. 13

Theory Behind EMI Mitigation by PCB Layout
Which PATH is the current going to take? Current Takes the Path of Least IMPEDANCE, NOT the Path of Least RESISTANCE! Z = R + jX High freq components contained by high di/dt current can go through different path than their low freq counterpart Thus, the loop area enclosed by high freq components can be completely different HF Current Path DC Current Path How can we identify the paths that the current is going to take? It comes from the characteristic of the current. It always takes the path of the least impedance, but not the path of the least resistance. And the impedance is a combination of the resistance, the inductance, and the capacitance on the path. So, the high current components contained by the high di/dt current can go through different paths than their low-frequency counterpart, and the loop area enclosed by the high-frequency component can be completely different as well. An example is shown on the right by a Simple Switcher Power Module board. So, the right arrow shows the DC current paths defined by the PCB layout design when you do the board. You have input current go in from Vin and go out to ground, and the output current go out to Vout and go back to ground. But the high current component in the input and output current is going to see the capacitors as smaller impedance paths at high frequency. So, the paths they are going to go is shown by the current loops on the picture, and is completely different than the DC current path.

Theory Behind EMI Mitigation by PCB Layout
ElectroMagnetic Field Energy is Proportional To*: f2: frequency of the harmonic of interest From switching frequency and di/dt A: loop area of the current path If: current magnitude at the frequency of interest 1/r: measured distance r Reduce Noise Generation Reduce fsw and high freq component in di/dt Reduce high freq loop area *Henry Ott’s classic Noise Reduction Techniques in Electronic Systems

Choice of Switching Frequency Spread-Spectrum Switching
EMI Mitigation Choice of Switching Frequency Not just for efficiency/space trade-offs Beware of EMI “keep out” zones Automotive = 500kHz < AM Band > 2MHz ADSL = >1.24MHz to avoid channel interference Harmonics Choose switching frequency that keeps beat frequency and harmonics out of the EMI range Spread-Spectrum Switching LM5088 dithers frequency and shows up to 20dB decrease in EMI We discussed briefly the choice of switching frequency in terms of meeting conducted emissions, but also it could be application specific. For example, there may be keep out zones that the customer's trying to meet. He has a range of frequency where it needs to be particularly quiet at because he's sampling at that rate, for example. For automotive applications, we know that it has an AM receiver; And typically in the old cars you'll put it on the AM band and you're twiddling with the knob, and you press on the accelerator, you can actually hear the engine, the revs per minute. You can hear the (inaudible) on the radio. That's typically an EMI problem. That band is between 500KHz and 2MHz, so automotive applications are particularly sensitive to noise in that range. Another technique, if you like, for minimizing EMI noise is spread-spectrum switching. As you can on the graph on the right hand side, you can see where you're not dithering the frequency, you can see a huge energy pulse at the switching frequency. However, for example, by using the LM5088, this dithers the frequency in a controlled fashion by plus or minus 5%, thereby spreading the energy that's seen in the frequency domain over a wider range, bringing its peak to a lower level. And thereby it could be the difference between passing and failing EMI certification. Fundamental switching frequency spike reduction and sidebands using spread spectrum switching in the LM5088 16 16 16

Steps To Mitigate EMI In PCB
Where is high di/dt? Where is the Critical PATH? How to reduce di/dt and LOOP area? Switching components generate high di/dt current  where is the return path? Loop Contains high di/dt current is CRITICAL PATH. And so, in switch mode power supply PCB design, we should first identify the location of the high di/dt noise, and then, identify the return paths of the high di/dt current, which we call the Critical Paths of the board design, and then, we can reduce the di/dt and reduce the loop area, to reduce the noise generation. Slow down switching action Reduce high freq path enclosed area

Noise Sources Identification 
AGENDA EMI Overview – definition and standards Noise Sources Identification Minimize EMI Generation by Layout Protect Sensitive Circuits from Noise Conducted EMI and EMI Filters Summary Isolated and High Power Density Power Supply Board Buck Boost Buck Boost So, the first step is to identify the source of the noises in switch mode power supplies. So, in my section of the presentation, I'm going to cover the non-isolated DC-DC converter topologies, which is Buck converter, Boost converter, and Buck-Boost converter, and in the coming session, we'll cover the isolated converter topologies.

Identify Critical Path
Buck Converter Switching Current exist in the input side Critical path Boost Converter Buck-Boost Converter In a Buck converter, it is obvious that the power switches is going to be part of the high di/dt loop, but which ground connection is more critical than the others? How we find out is by identifying the current path of the two sub-sections in switching period of this converter. When the high-set FET is on, the current is going to go through the blue trace, and when the low-set FET is on, the current is going to through the pink trace, shown in this slide. And if a branch contains both of the two colored lines, that means 100% of the time of the switching period, there is current going through this branch, and we consider that a DC current path. If a branch only contains one of the colored lines, that means only a part of the switching period has a current going through this branch, and the current is going to be discontinuous. So, we consider those to be high di/dt paths and the critical paths of the PCB layout. So, in Buck converter, this is shown as the shaded loop, which contains the high-side switch, the low-side switch, and the input capacitor. 19 19 19

Identify Critical Path
Buck Converter Critical path Boost Converter Buck-Boost Converter We can do the same thing in the Boost converter, and the critical path is contained by the two switching components and the output capacitor. 20 20 20

Identify Critical Path
Non-Inverting Buck Converter Critical path Boost Converter Inverting Buck-Boost Converter Now, inverting Buck boost is shown here, and the Buck boost. In both the input and output current are discontinuous. 21 21 21

What Can We Do In PCB Layout? --Buck example
Buck Converter Boost Converter Minimize critical path area Separate noisy ground path from quiet ground Buck-Boost Converter Layout the pcb with the small loops. Sometimes extra capacitors are Needed to bypass the noise. 22 22 22

What Can We Do In PCB Layout? --Buck-Boost example
Non-Inverting Buck Converter Boost Converter Buck-Boost Converter 23 23 23

AGENDA  Minimize EMI Generation by Layout
EMI Overview – definition and standards Noise Sources Identification Minimize EMI Generation by Layout Protect Sensitive Circuits from Noise EMI Filters Summary Isolated and High Power Density Power Supply Board Critical Path Area Reduction Grounding So, now, we are going to talk about PCB layout. How do we minimize the EMI generation, and we are going to talk about it in two-folds. One is, how to reduce the path's loop area. The other is, how proper grounding can help in EMI reduction?

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding BUCK Example Bypass Caps in High di/dt loop should be placed as close as possible to the switching components Low side FET SOURCE should be connected as close as possible to the input capacitor Apply to critical paths in other SMPS topologies High di/dt Caps SW Node FETs & Driver So, we go back to the Buck example. As we said before, the goal is to put the Bypass Caps in the high di/dt loops as close as possible to the switching components. And the low-set FET source should be connected as close as possible to the Bypass Caps ground, and the same thing applied to all the other topologies.

Lower EMI can be achieved by…
Place capacitors on same side of board as component being decoupled Locate as close to pin as possible Keep trace width thick and minimized Connecting to decoupling capacitors Connecting to output capacitors 26 26 26

BUCK controller Input Cap GND connection
Customer Layout Example BUCK controller Input Cap GND connection Input Cap GND LS FET GND Bad Layout Good Layout Input Cap GND LS FET GND LS FET GND Input Cap GND

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding Buck Regulator Comparison with Cin location (single Cin, smaller loop area) High di/dt Caps SW Node FETs & Driver SW 14.5V max VOUT 47mVpp 41dBµV/m Also, to show the effect of the high di/dt paths, bypass capacitors, we did an experiment here. We have only one -- this board is a Buck regulator switch amp load, and we only use one input capacitor for this comparison. And in the first case, the capacitor is put as close as possible to the IC pins, which contains the switching components inside. So, we measure the switch node at the peak current, the Vout peak-to-peak ripple, and the radiated EMI data. VOUT VIN 28

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding Buck Regulator comparison with Cin location (single Cin, 2.5 times larger area) High di/dt Caps SW Node FETs & Driver SW 18.1V max 44dBµV/m And as a comparison, the input capacitor is moved to be a little bit further away from the pins, and the loop area is about 2.5 times bigger comparing to the first case. And the measurement we did, we see that the switch node maximum voltage is about 3.6 volts more, and the Vout peak-to-peak ripple is about 50% more, and the EMI peak also shows 3 dB micro volt per meter more. And all the other parts of the board -- all the other part of the BOM are identical in this comparison. VOUT 75mVpp Comparison SW max (V) Vout p2p (mV) EMI peak (dBµV/m) Smaller Area 14.5 47 41 Larger Area 18.1 75 44 29

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding SW Swings from VIN or VOUT to ground at Fsw. Very high dv/dt node! Electrostatic radiator Requires a contradiction: As large as possible for current handling, yet as small as possible for electrical noise reasons Solutions: Switch node short and wide Minimum Copper Width Requirement: Roughly 30mils/Amp for 1 Oz Cu and 60 mils/Amp for ½ Oz Cu, or Where T = Trace width in mils, A is current in Amps, and CuWt is copper weight in Ounces. Formula approximates IPC recommendation for a 10 degree rise for currents from 1A to 20A. High di/dt Caps SW Node FETs & Driver After talking about the bypass capacitors, there is a node in this high di/dt loop we normally call the switch node because the voltage swings from Vin or Vout to ground at the switching frequency, and it is a very high dv/dt node. It can be a radiator of EMI, but the layout of this node has a contradiction. It should be as big as possible for the current handling and thermal handling, and yet, as small as possible to reduce the noise radiation. So, the solution should be that we should keep the inductor as close as possible to the FETs and keep the switch node trace to be short and only as wide as necessary to carry the current. To make matters worse the SW is also often a heat-sink for the low side switch.

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding Minimize loop area enclosed by high-side FETs, low- side FETs, and bypass caps Connect the low-side FET’s source to the input- cap ground directly on the same layer, then connect to the ground plane Use copper pours for drain and source connections to power FETs Minimize stray inductance in the power path High di/dt Caps SW Node FETs & Driver

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding Gate drives are also high di/dt paths, lower current level Place drivers close to MOSFETs Keep CBOOT and VDD bypass caps very close to driver and FETs Minimize loop area between gate drive and its return path: from source of FET to bypass cap ground Minimize stray inductance in the power path Avoid vias in di/dt path Short trace and width > 20mil for CBOOT, CVDD-bypass, and Gate drive High di/dt Caps SW Node FETs & Driver Gate drive signals are also high di/dt signals. They just have smaller power level comparing to the power track current. So, the drivers should also be placed as close as possible to the MOSFETs, and the Boot capacitors and the VDD bypass capacitors should be placed as close as possible to the drivers and the FETs. And the loop area between the gate drive and its return paths should be as small as possible, the paths being from the source of the FET to the bypass caps ground. To minimize the stray inductance in the gate drive paths, vias should be avoided in the gate drive signal, and also the traces for the Boot cap, the Bypass caps, and the gate drive would be best to be short and wide.

EMI Mitigation by PCB Layout
Critical Path Loop Reduction Grounding Contradiction on SW node transition rate: Faster Rising and Falling Times = Less Losses =Higher EMI Resistor Value: Start with 1-10 ohms and adjust from there High di/dt Caps SW Node FETs & Driver Here is another contradiction in the switch node transition rate design. If you have a faster rising and falling time on the switching current, which is controlled by the gate drive of the MOSFET, then you will have smaller switch losses, but at the same time, the EMI generated by the di/dt is going to be higher. So, here, I showed two options of how to slow down the rise and fall time of the power MOSFET if it is needed. The idea is to add gate resistors to slow down the Pin and Pout time. The resistor should be kept to about 1 to 10 ohms, and if in a controller case, you have access to the gate, then a schottky diode can be added in parallel to the gate resistors to increase the falling time, and also to pull on the gate harder to reduce the likelihood of shoot-through problems.

EMI Mitigation by PCB Layout
Critical Path Loop Reduction Grounding Ground Plane Return Current Takes The Least IMPEDANCE Path Unbroken Ground Plane Provides Shortest Return Path – Image current return path Trace or Cut on the ground plane Ground Plane Return current path enclose much larger area if the direct path is blocked Current flow in top layer trace So, after talking about the critical paths loop reduction, I want to also cover how to design the ground plane and shielding and how that is going to help with the EMI problem. So, an unbroken ground plane could provide the best -- the least impedance paths for a counter trace on the top or on the bottom to return to the current source. And if the current is right on top of each other, the loop area is minimized, and the EMI generated by the loop is small as possible, and the B-field can be canceled as well. The case shown on the right that if you have a cut in the ground plane, then, the return current has to find a longer path to go around the cut, to return to the current source. Then, the area enclosed by the current is much bigger and the EMI problem is going to be worse. Ground Plane Return current path in unbroken ground plane directly under path Area minimized B field minimized

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding Ground Shielding Example – Two Layer Board VOUT 30mVpp SW 15.7V max 32.5dBμV/m In the first case, we have a two-layer board, which is also a Buck regulator 3 amp load level, and we also married the Vout peak-to-peak ripple, the switch node maximum voltage spike, and also, the radiated EMI number.

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding Ground Shielding Example – Four Layer Board w/ Identical Layout / BOM – Two GND Planes in between VOUT 23mVpp SW 13V max It's the same board. It's the same layout and it's the same BOM and it's the same part as built up in a four-layer board with two ground planes in the middle, and to compare the things we care about. We can see that at the switch node, peak ripple is reduced by 2.7 volts. The peak-to-peak on the Vout is 7 millivolt smaller, and also, the peak of the radiated EMI is 5 dB microvolt per meter smaller. 27.5dBμV/m Comparison SW max (V) Vout p2p (mV) EMI peak (dBµV/m) Two Layer 15.7 30 32.5 Four Layer 13.0 23 27.5

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding Ground Shielding Example – Four Layer Board w/ Identical Layout / BOM – w/ CUT under SW node VOUT 26mVpp SW 15.7V max 32.5dBμV/m A third case we did is, all the same thing as before, but we have a cut on the ground plane right underneath the switch node. And then, from the table here, we can see that shielding is not as good as a solid ground plane. The switch node ripple, the Vout peak2peak and the EMI are all higher than the second case, which has two solid ground planes in between. Comparison SW max (V) Vout p2p (mV) EMI peak (dBµV/m) Two Layer 15.7 30 32.5 Four Layer 13.0 23 27.5 Four Layer w/ GND cut 26

EMI Mitigation by PCB Layout
Critical Path Area Reduction Grounding Ground Plane Unbroken Ground Plane provides shortest return path to EMI and Best Shielding Don’t cut ground plane Keep high power, high di/dt current away from ground plane, run separate paths on the top layer to contain it Ground plane is for DC distribution and signal reference only, ideally, there should be no current flow on ground plane Bypass to ground PINs, not the plane General rules for the ground plane. An unbroken ground plane provides the shortest return path to EMI and best shielding. So, don't cut the ground plane, and we should keep the high power high di/dt current away from the ground plane. Run separate paths on the top layer to contain the high di/dt current. The ground plane is only for the DC distribution and signal reference. Ideally, there should be no current flow through the ground plane.

Switcher Power Modules (LMZ23610)
4/19/2017 Switcher Power Modules (LMZ23610) 2.8 mm 15 mm 5.9 mm Ease of Use Webench, Ease to mount & rework Internal Comp Dual Lead frame Built in Vin Capacitors to solve EMI issue, & shielded inductor 10 Amp Current Sharing Eval board CISPR 22 Measurements EMI Configuration 39 39

Nano Module – LMZ10501/0 (1A/650mA)
Extremely Small Solution Size 2.5 mm 1.2 mm 3 mm Place on front-side or back- side of PCB LLP-8 Footprint Mounted on PCB Expanded View Excellent Performance Low output voltage ripple High efficiency Fast transient response COUT = 10uF Vout = 1.8V Low EMI Complies with CISPR22 Class B Standard 40

Innovative Packaging Top View Side View Solder Reflow Profile
Key Features: LLP Footprint Micro SMD is a standard National package running in high volume Moisture sensitivity level 3 Standard soldering process Reliability testing on complete module according to NSC standards RoHS compliance to IPC 1752 1.2 mm 3 mm 2.5 mm Here is a closer look at the Nano Module packaging. At 2.5 x 3 x 1.2mm, the Nano Module is the smallest 1A DC/DC solution in the market today. It has a standard LLP-like 8 pin footprint with the silicon die as a uSMD mounted on top of the inductor. This uSMD silicon is a standard package that currently runs in high volume in our manufacturing facilities. This package has passed the moisture sensitivity level 3 test, the standard soldering process up to 260 degrees Celsius, and all reliability tests that come standard to any product from SIMPLE SWITCHER. Top View Side View Solder Reflow Profile 41

Passing CISPR22 Class B Radiated EMI
The evaluation board with the default components complies with the CISPR 22 Class B radiated emissions standard. 5Vin, 1.8Vout, 1A load 10uF input capacitor 10uF output capacitor 1nF VCON capacitor See AN-2168 42

Nano Module - Cispr 25 Class 5 EMI (Radiated)
43

Passing CISPR 25 Class 5 Radiated EMI
Adding two small 0.1μF 0805 input capacitors results in CISPR 25 Class 5 radiated emissions standard compliance 44

AGENDA    Protect Sensitive Circuits from Noise Summary
EMI Overview – definition and standards Noise Sources Identification Minimize EMI Generation by Layout Protect Sensitive Circuits from Noise Conducted EMI and EMI Filters Summary

Protect EMI Sensitive Nodes from Noise
Shielded by Ground / Power Planes Vout sensing path and feedback node Compensation network Current sensing path Frequency setting Monitoring and Protecting Circuits … … Sensitive Nodes: Control and Sensing Circuits SW node Inductor High di/dt bypass caps MOSFETs Power Diodes … … Noisy Nodes: Any Nodes in High di/dt Loop On a switch mode power supply, we have all these noisy nodes in the high di/dt loop, and we also have some sensitive nodes including the control and sensing circuits, including the Vout sensing paths and the feedback node, the compensation network, the current-sensing paths, the frequency setting network, and the monitoring or protecting circuits, and more if you have more functions. Well, I think there are two ways to protect these sensitive nodes. One is to shield them by the ground or power planes, put them on the other side of the shielding. The other way, if you cannot -- if it is not possible to put them on the other side, then put them further away from the source of noise. Away from EMI source

Good Practice to Protect EMI Sensitive Nodes
Use Layers – four layer board stack-up plan Top: All high power parts and high di/dt paths, signals that can be routed away from high di/dt paths Mid1: Ground Plane Mid2: Ground Plane / Power Plane / Signal & low power traces Bottom: low power and signal traces Flood unused area with copper for improved thermal performance and shielding Place and Route Keep all bypass caps close to pins The higher the impedance and/or gain, the smaller the node should be, especially inputs to op-amps: FB pin, comp pin, etc Low impedance nodes can be wide, such as VIN and VOUT It is good practice to protect the sensitive nodes. One is to use the layers, and here, I have a commonly used four-layer board stack-up plan. We have the majority of the power components on the top layer. So, we keep the high-power high di/dt paths also on the top layer. And also, we can have some signals that can be routed away from the high di/dt paths on the top layer. And the middle layer one should be a solid, unbroken ground plane. The middle layer 2 can be a ground plane, can be a power plane, and can be a low-power and signal trace plane based on the complexity of the board you are designing. And the bottom is purely for the more sensitive nodes and traces and the components, so that we can put it on the other side of the shielding. And also, we should flood the unused areas with copper to improve the thermal performance and to have better shielding. For place and route, general rule is to put all bypass capacitors as close as possible to the pins. The higher the impedance or gain of a node, the smaller the size of the node should be, especially the input to the op-amps. For example, the feedback node and the compensation, and the low impedance node can be wide, such as the Vin and Vout traces.

Protect EMI Sensitive Nodes – Cont.
Make long runs to low impedance nodes, short runs to high impedance nodes. Apply to Place output voltage divider close to the FB node (high impedance), farther from Vout (low impedance), if have to choose × Route Sense+/Sense- traces parallel to one another – minimize differential-mode noise pickup. Apply to Current sensing traces Voltage remote sense lines Another thing we need to pay attention to is that, if you choose to run a long trace for the Vout feedback, you should run it from the Vout to the top of the resistor divider. We know that the feedback node is a high impedance node. If any noise is coupled in it, voltage spikes are going to be generated, and in the contrary, the Vout is low impedance node. Any noises coupled can be conducted out. So, the best way is to put the resistor divider closer to the feedback node, and to run a longer trace to Vout if you have to choose. For sensing traces, if you have differential sensing, for example, for the current sensing or Vout remote sensing, the two traces should be run in parallel to each other to minimize the differential mode noise pickup. Keep sensitive small signal traces thin and further away from surrounding signals – lower capacitance coupling

Customer Layout Example
LM20k 5A Buck regulator FB trace SW L Identified layout problems Vout sensing point is right under the inductor – noise pick up FB trace route very close to SW node and di/dt loop – noise coupling Res Divider 49

Customer Layout Example
More problems in this layout COMP RC GND CIN AVIN PGND pins CIN GND to LS source path (high di/dt) undefined, through gnd plane AVIN bypass cap gnd return path very long Comp network close to high di/dt loop

Check List If your board can not pass Radiated EMI
Check high di/dt loop layout, especially CIN gnd to LS FET source connection Check GND shielding Suggest Shielded L Use twisted pair at input / output (where switching current exists) Suggest to reduce fsw or switch transition rate Consider adding conducted EMI filter (also alleviate Radiated EMI) If your board is not working properly (no schematic reason) or too much volt spikes, check High di/dt loop layout GND shielding Sensitive nodes layout, especially FB divider and routing Sensitive node grounding Bypass caps Add small bypass caps (e.g. 47nF) to Vin and Vout as close as possible Add snubber to SW node If a board cannot pass radiated EMI, what can you check?

AGENDA    Conducted EMI and EMI Filters Summary
EMI Overview – definition and standards Noise Sources Identification Minimize Noise Generation by Layout Protect Sensitive Circuits from Noise Conducted EMI and EMI Filters Summary

Switch Mode Power Supply
DM Conducted EMI I Switch Mode Power Supply Supply LOAD Differential Mode Conducted EMI In DC-DC converter topology, only Hot and Neutral lines, no CM EMI involved Involves the Normal Operation of the Circuit Does not involve Parasitics, except input / output CAP ESR and ESL Only Related to CURRENT, not voltage For example, with the same power level Buck converter, lower input voltage means higher input current, thus worse conducted EMI Why we care? Excessive Input and/or Output Voltage Ripples can compromise operation of Supply and/or Load Conducted EMI in the switch mode power supplies -- the switch mode power supplies always have two wires to connect it to the supply and to the load. So, any current goes in has to go out through the other wire, so the sum of the two currents is always zero. There is no common mode conducted EMI involved in the non-isolated switch mode power supply design. So, we only consider differential mode conducted EMI here. For a differential mode, conducted EMI in switch mode power supplies, it involves the normal operation of the circuit. PCB layout cannot quite help to reduce the problem. It does not involve other parasitic except the ESR and ESL of the capacitor in the part with discontinuous current, and it is only related to the current of the discontinuous port, but not the voltage. So, for example, in fixed power level Buck converter, if the input voltage is reduced, then the input current is going to be higher, and the differential mode conducted EMI problem is going to be worse. So, why do we care? The conducted EMI can go back to the power supply or go to the load, and could compromise their operation.

DM Conducted EMI Mitigation
EMI filter design Add filter to prevent noise conducted to Supply or Load Must be designed so it does not affect SMPS stability See Application Note for practical EMI filter design (AN-2162) Switch Mode Power Supply Supply LOAD That’s why we should reduce them, and the effective way to do it is to add an EMI filter to prevent the high-frequency noise from going back to the supply or the load, but the filter added could affect the switch mode power supply stability. (Buck) 54

Input Filter Design for Conducted EMI
There are two basic requirements for the conducted EMI filter: Must meet noise attenuation requirement to meet regulations (i.e. CISPR 22) Must not interfere with the normal operation of the SMPS converter If filter impedance exceeds the negative impedance of the input supply, it will cause interaction and stability issues. Example of a Buck regulator No input filter Fails CISPR 22 regulation limits This regulator needs an input filter to meet regulations. But how do we estimate how much filter attenuation to add? Moving onto the next slide, we're going to discuss input filters for, let's just say, a DC to DC buck converter. Let's say you just have an input in your buck converter, you want to minimize the amount of noise seen on the input for another switching supply. Now one of the careful things we need to adhere to is the input filter will interact with our control loop of our buck converter. We're going to make sure that the output impedance of our input filter is much lower than the input resistance of our buck converter. The input resistance of our buck converter is negative. Now why do we say that? Input resistance is negative because as the voltage goes up on a buck converter, its current comes down. So we call it negative resistance. As I mentioned, the output impedance of our input filter needs to be much lower than the Rin. 55

Necessary Input Filter Attenuation
Methods of estimating the filter attenuation without LISN and Spectrum Analyzer Method 1 – estimation using oscilloscope measurement Measure the input ripple voltage using a wide bandwidth scope and calculate the attenuation. VMAX is the allowed dBμV noise level for the particular EMI standard. Method 2 – Estimation using the first harmonic of input current Assume the input current is a square wave (small ripple approximation) CIN is the existing input capacitor of the Buck converter. D is the duty cycle , I is the output current, Fs is the switching frequency

Typical Conducted EMI Filter
Follow the design steps described in AN-2162. Calculate the required attenuation using Method 1 or Method 2. Capacitor CIN represents the existing capacitor at the input of the switching converter. Inductor Lf is usually between 1μH and 10μH, but can be smaller to reduce losses if this is a high current design. Calculate capacitor Cf. Use the larger of the two values (Cfa and Cfb) below: Capacitor Cd and its ESR provides damping so that the Lf Cf filter does not affect the stability of the switching converter.

Conducted EMI Filter Design Tool
Excel based tool is available to help design the conducted EMI filter. The tool is based on the steps described in AN-2162. The filter design can be printed on one page. double click to open calculator

Conducted EMI Before and After Filter
VIN = 30V, VOUT=3.3V, IOUT = 1.6A, CIN = 10μF + 1μF, Fs = 370kHz Results before installing filter: Results with the following filter: Lf = 3.9 μH, Cf = 10 μF, Cd = 100 μF This picture just shows a before and after of the conducted EMI environment before and after EMI filter. So, on the left is before the filter, and the first highest spike happens at the switching frequency of this converter, and the following spikes are sub-harmonics, and some frequency components could come from the di/dt of the switching action. On the right is after the filter, and we can see that the sub-harmonic spikes are pretty much all filtered out, and the switching frequency is also greatly reduced, and the data we captured is peak noise values. So, it should be compared to the pink lines on the top. So, after the filter, this converter actually passes the EMI limits. 59

AGENDA   Summary EMI Overview – definition and standards
Noise Sources Identification Minimize EMI Generation by Layout Protect Sensitive Circuits from Noise Conducted EMI and EMI Filters Summary

SUMMARY EMI is Electromagnetic Interference. There are many EMC standards, based on regions and applications SMPSs are big source of radiated and conducted EMI EMI comes from high power switching action EMI problems can be mitigated by identifying high di/dt loop and reducing loop area by careful board layout Sensitive circuits should be protected with careful layout and shielding Filters can be designed to attenuate conducted EMI to protect supply / Load Filters also help reduce radiated EMI

AGENDA   Questions EMI Overview – definition and standards
Noise Sources Identification Minimize EMI Generation by Layout Protect Sensitive Circuits from Noise Conducted EMI and EMI Filters Summary Questions

Isolated and High Power Density Power Supply Board
Youhao Xi Phoenix Design Center April 2011 63 63

Outline Identify critical paths in isolated power circuits
Considerations for high power density board layout: copper layer thickness, trace width, and trace spacing and width The isolation boundary PCB Heat-sink An isolated power supply example Summary 64

Identify Critical Paths In Isolated Converters
Flyback Converter Forward Converter Push-Pull Converter Half Bridge Converter Critical paths Full Bridge Converter 65 65 65 65 65 65

Identify Critical Paths In Isolated Converters
Flyback Converter Forward Converter Push-Pull Converter Half Bridge Converter Critical paths Full Bridge Converter 66 66 66 66 66 66

Identify Critical Paths In Isolated Converters
Flyback Converter Forward Converter Push-Pull Converter Half Bridge Converter Full Bridge Converter Critical paths 67 67 67 67 67 67

Identify Critical Paths In Isolated Converters
Flyback Converter Forward Converter Push-Pull Converter Half Bridge Converter Full Bridge Converter Critical paths 68 68 68 68 68 68

Identify Critical Paths In Isolated Converters
Flyback Converter Forward Converter Push-Pull Converter Half Bridge Converter Critical paths Full Bridge Converter 69 69 69 69 69 69

Isolated and High Power Density Board
The good practices and generic rules covered previously all apply to the isolated power board layout. There are some additional considerations for isolated and high power density power boards: Spacing requirement to sustain the potential difference between adjacent traces; PC Board copper layer thickness and trace widths; PC Board heatsink; Isolation boundary. 70 70

High Power Density Board
What does it mean by high power density? Power density is measured by the ratio of power capacity to the physical volume of the unit, usually expresses in the unit of W/in3, or W/cm3 . Regarding PC Board design, power density normally means the ration of power capacity to the board size, expressed as W/in2, or W/cm2. High power density implies the board involves high current, and/or high voltage, traces. For typical communication applications, on the power board the current can be >30A, and the voltage can be >150V (mainly switching node voltage). High current traces requires large copper usage to reduce conduction losses High voltage traces requires certain minimal spacing between each other. Components are small, and placed densely. 71

High Power Density Board: Components
Use Small Sized Components, and Place Densely, as long as it does not violate the minimum spacing defined in the next slide. To achieve high power density, select small components, place densely. Note that the ratings must meet the application requirements. Resistors: voltage and power ratings. For example: R0201 size: 30V max, 0.05W R0402 size: 50V max, 0.063W R0603 size: 75V max, 0.10W R0805 size: 150V max, 0.125W R1206 size: 200V max, 0.250W Capacitors: voltage rating; ripple current rating. Inductor: current rating; power dissipation. MOSFET: voltage rating; power dissipation. Diode: voltage rating; power dissipation. A 200W 8th Brick Board 72

High Power Density Board Trace Spacing
PC Board Trace Spacing Guidelines IPC-2221: A widely accepted standard in Industry In power circuit board that you commonly see: There are other standards which are applicable case by case. IPC-2152 IPC-9592 UL-60950 etc. For signal traces For high voltage traces 73

High Power Density Board Copper Layers
PC Board Copper Thickness Typical power converter PC Board can be done with copper layer thickness of 1 Oz and 2 Oz. 1 Oz = in, or 35 m. 1 Oz copper layer is normally for signals traces. 2 Oz copper layer is for power circuit traces that conduct high current. For high power density board dealing with high current, heavy copper Oz or thicker copper layers --- can be used. 74

High Power Density Board Trace Width
PC Board Trace Width It is NOT ALWAYS TRUE that a wider trace is better. It depends on the function of the trace. If it conducts power current, a wider traces means lower resistance and hence lower conduction losses. If it conducts a low current signal, a wider trace may (or may not) increase the susceptibility to noise interference via capacitive coupling. Switch node pads, though conducting high current, should be kept as small as possible to minimize the radiated EMI. For traces conducting small signals, like feedback and control signals, typically use 0.010~0.015 inch. 75

High Power Density Circuit Trace Width
PC Board Trace Width (ref: IPC-2125) For trace current >0.25A, refer to the following for minimum width. Try to make it wider if board room permits. An example: 10A trace, 10C rise, 2 Oz copper Figure A indicates to 420 mil2, leading to 160 mil wide trace according to Figure B. For inner layers, double the width (2x160 = 320 mil). 76

PC Board Heatsink PC Board Heatsink
For surface mount (SMT) power components, like power MOSFETs, power rectifier diodes, etc, PC Board copper pads can help heatsinking these components in addition to additional heatsink devices. Typical PCB heatsink: Heatsink is realized by enlarging footprint of power component. For instance, the drain pad of a DPAK power MOSFET. Heatsink also extends to all other layers through the PC board, connected thermally and electrically with an array of thermal via holes. 77 77

Isolation Boundary Isolation boundary
Depending on application, the requirement of isolation strength is different. For telecom, it is usually 1.5kVac rms, or 2.2kV dc. For medical, it is 2.5kVac rms up to 5kVac rms. Some applications may require 10.1kVdc. Isolation boundary needs to be clear of conductors, or clear of copper traces. The clearance should confirm the spacing per applicable safety regulations and standards. In power supply, there are four types of devices that are usually placed across the isolation boundary. Power transformers fulfilling isolated power transfer Opto-couplers, or solid state isolators Pulse transformers for isolated gate drive A common mode capacitor (always reserve a position on PCB, even if not intended to use initially). 78 78

An Example A Flyback Converter: LM5072 POE Eval Board Schematic 79

An Example Example circuit board Top Side Isolation boundary Primary
Seondary Rectifier Heatsink MOSFET Heaksink 80 80

An Example Example circuit board Bottom Side Isolation boundary
Primary Seondary Rectifier Heatsink MOSFET Heaksink Opto-Coupler Cross Boundary Cap 81 81

Summary Switching current paths are critical, and need to follow the rules previously discussed for high di/dt circuit loops. Identify the high di/dt circuit loops on both the primary and secondary sides. Good practices for non-isolated circuit board layout also apply to isolated circuit. Considerations for high power density circuit boards: Use components as small as possible; Follow industry standards for layer thickness, trace width and trace spacing; Minimize the trace width for low current signal traces. Enlarge PC board pads of power components to enhance heat-sinking; Pay attention to isolation boundary. Remember to reserve a position for a common mode capacitor. 82

Thank You 83

Appendix A) Snubbers David Baba Power Design Group 84

Lower EMI can be achieved by…
Use snubbers and clamps to minimize both dv/dt and di/dt of switching waveforms We can also achieve lower EMI by using snubbers. As I mentioned, you always are going to have a certain amount of inductance. And you're always going to have a certain amount of capacitance that's going to ring out at the frequency of 1/2pvLparasitic x Cparasitic. What we want to do is dampen out that ring or clamp that ring. Firstly I would suggest we dampen out the ring as a first choice. Typically we do that on buck converters for the FET, and also we typically use the diode snubber on, let's say, isolated supplies where we're rectifying on the secondary. What the main component of is this is the R. It's the R that's dampening out the ring because, as you know, if you have a change in current and you have no R and you just have an L and C, or you have a change in voltage that's seen across an L and C, what you're typically going to see, if it has no resistance in that circuit, it's going to ring out for ever more. But obviously we do see the ring settle to a DC value again. However, it's because there's not enough resistance. So we place an extra resistance in the circuit. But we don't just want to put that resistor -- let's say we throw into figure (a) on this slide -- we don't just want to put resistor across the Q. That would be highly dissipative, and it certainly wouldn't give you a good switch if you've got a resistance across it. So we typically use a capacitor in series with that so that we don't allow DC or lower frequencies to flow. We just want the higher frequency ring, typically at 10s of MHz, 100MHz to flow through that circuit where the C becomes a short at them higher frequencies, and the R provides a dampening at the frequencies of interest. Same thing with the diode. Referring to (c), really on a flyback convertor, you have a voltage reflected, let's say, from the secondary to the primary. Let's say you have a 2:1 turns ratio from primary to secondary. Let's say you had 5V on the secondary, that's going to be 10V reflected to the primary. With that 10V, that's going to sit on top of your input voltage, that's what it's going to see on the flyback convertor. That's why when you look at the square wave on a flyback convertor that's down the drain of the MOSFET, you typically see it higher than Vin because you have sitting on top of that the reflected output voltage determined by the turns ratio from primary to secondary. You by no means want to clamp any of that. But you certainly want to perhaps clamp the ring or overshoot that goes above and beyond the input voltage plus the reflected voltage. That's where the sizing of that clamp voltage, the clamp or the transorb is comes in. Also you have a RCD snubber in (d), which again provides you with the same sort of clamp as the one in (c), but it's less dissipative than the (c) version. We're going to talk more about that in the following slides. Typical snubbers in switching power supplies 85 85 85

Designing RC Snubbers RC to damp out ringing Make Rsnub = Rchar
Determine R Measure the Ring at the switch node Determine Cswitch If it is a Diode Look at Junction capacitance. If FET Make Rsnub = Rchar Determine Power Dissp Rsnub Determine Characteristic Impedance In terms of the RC snubber, we need to determine what the R is, as I mentioned, in order to damp that ring out. One way we can do this is measure the ring frequency. So we put a probe, a low impedance path between the ground -- in other words, put the probe right across the source and the drain of your MOSFET, for example. We want to measure the ring frequency. Okay, so then we need to determine what the R characteristic or the snubber value is. Once we know what the ring frequency is, we need to determine what the C is. I've provided a rough estimate of C switch estimate. If you're using a MOSFET, look in the MOSFET datasheet. It has a gate charge between the gate and the source. It gives you a typical value. Multiply that by four and divide it by the voltage at the gate. The voltage at gate, typically if it's a 5V gate signal, it's divided by 5. We get an estimate of the switch node capacitance. Multiply it by the ring frequency that you measured, times two, times p, divided into one gives you the R characteristic or the characteristic resistance, which is basically equivalent to the snub resistance. You want to use as high a snubber capacitance as you can, but you don't want to select something too high, that causes you dissipate too much power. Now remember, whatever dissipation you're going to have, that's going to be dissipated in the snub resistor.

Guidelines to designing RCD Snubber
SetC snub to 10nF to 100nF For a set leakage inductance the Resistor value will determine the Clamp voltage and the losses in the snubber circuit. Typical clamp voltages to be set at ~2 x VRO. Select Rsnub based on power dissipation Transcript: The next one, guidelines for designing RCD Snubbers, we set the C for the RCD snubber, which was in figure (d) of the slide where we showed the different configurations. For a set leakage inductance, the resistor value will determine the clamp voltage. That is to say the higher the resistor value, the higher the clamp voltage will be. So it's just like using a higher transorb, a higher voltage transorb. It's not going to start clamping until a higher voltage. That's what happens if you use a higher resistor value. Again, we typically want to use twice the reflected output voltage. We need to know what the Rsnub value is. And really we typically find out what the Rsnub value is by following the power dissipation followed by the leakage inductors, which is typically given to you by the transformer manufacturer. The peak current, which you'd have to calculate, the switching frequency multiplied by 0.5 gives you the power in the snubber. So obviously the higher the resistor value, the less power dissipation there's going to be but it's lower clamping value. Hope that makes sense.

Designing Clamps for Flybacks
Determine reflected voltage to Primary Add a transorb whose value is GREATER than I have 10V on the input and 10V reflected, the clamp is sitting at 10V already. So we know that it's going to ring out to double the reflected voltage, which is 20V. We want a transorb value of around 20V Use Schottky for clamp

Appendix B) Component Selection
David Baba Power Design Group 89

Well-Chosen Components/Packages Reduce Amplitude of Ringing Waveforms
Resistors/Capacitors Inductors/Transformers Power MOSFETs Rectifier Diodes Concerns with components dealing with high di/dt and dv/dt stresses Cin, Cout, FET decoupling, snubbers, sense resistors Biggest concern is stray inductance Surface mount parts have less inductance than through-hole Use Low inductance resistors for current sense applications to preserve waveform shape Avoid Using Wirewound Resistors Moving onto the next slide where we're talking about well chosen components/packages, which could reduce the amplitude of the ringing waveform. This is because we really have concerns, obviously, by the changing current over time and its inductance. If you have a greater inductance and a very fast or large changing current over a very short period of time, that's going to give rise to a very big ring of voltage that's seen across that parasitic inductance. One way to minimize the parasitic inductance and capacitances can be seen by the placement and selection of components of the input capacitor, could be seen by the output capacitor in terms of measuring the output ripple, the FET decoupling, again, about how you're going to wire the switch node for the top FET, how you're going to wire between the Cin and the drain of the FET. Also there's obviously going to be certain amount of parasitic inductance and capacitances, particularly with the capacitor inductances we use snubber circuits and we're going to talk about that. Also we need to be careful of current sense resistors because that has a big effect on the loop control for current mode control, for example. A big concern, as I said, was stray inductance. In terms of current sense resistors, we need to use low inductance resistors. By no means do we use wire wound. We use specific current sense resistors to minimize the inductance and thereby minimize the amount of noise that we see as we're measuring or we're sensing the current across that resistor. 90

Well-Chosen Components/Packages Reduce Amplitude of Ringing Waveforms
Resistors/Capacitors Inductors/Transformers Power MOSFETs Rectifier Diodes Use shielded inductors for all power inductor paths If cannot find shielded coupled inductor, specify two shielded inductors Transformers major problem in EMI Flyback voltages can be very high Reflected voltages must be snubbed Different cores have different leakage flux Work with a reputable transformer manufacturer such as Pulse or Coilcraft to ensure quiet transformer design Moving onto the next slide, we can see that in terms of the inductor and if we're using a transformer, our first choice would be to use shielded inductors. If we can't find shielded inductors, we want to make sure the inductor's well-placed on the board so as not to upset any noise-sensitive circuitry because we're going to see some magnetic fringing coming off of that inductor. We're going to make sure that we don't wire a, let's say, sensitive feedback paths underneath that or near that inductor. In terms of transformers, for example, a flyback convertor, the voltage or you have what's called leakage inductance. The higher the leakage inductance, obviously the worse the amount of ring that there's going to be across that inductor. We'd have to use obviously snubbers. You also have reflected voltages to the secondary that need to be snubbed. Different cores have different leakage flux, and also with a flyback we store energy mainly in the gap. And also that gap we typically would put on the center limb and not on the outer limb so we could actually get some shielding of the fringing that comes off of that center limb. Typically we'd obviously want to use a shielded transformer. What we recommend is to work with a reputable transformer manufacturer so as to use good course material selection, good gap lengths. Also we want to make sure we have low leakages between the primary and secondary. Last but not least, we want to make sure that if we have a bobbin that has a nice manufactured shield around it, then we want to implement that to minimize the noise. 91

Well-Chosen Components/Packages Reduce Amplitude of Ringing Waveforms
Resistors/Capacitors Inductors/Transformers Power MOSFETs Rectifier Diodes Come in many packages (TO-220, SO-8, DPAK, etc) Surface mount devices have EMI advantages Lower lead inductance Use copper traces to cool part and reduce EMI Through-hole cooled via insulator which creates parasitic capacitance and radiates during switching cycles Method to reduce this noise shown using faraday shield Power MOSFETs, we're looking here at if we were to use through-hole MOSFETs. You obviously have a heat sink and obviously the tab that's found on TO-220 is light, and we obviously want to put a piece of insulator in-between that to the chassis. What we have, as you can see, is a parasitic capacitance between the tab of the MOSFET to the actual chassis, which has its own local ground. Now generally with noise what we want to do is we want to return the current back to its local source. We do not want to supply paths of electric fields and thereby injecting currents into grounds that are far away because then that makes big loops. It doesn't help your conducted emissions because that's really what conducted emissions are. It's currents flowing not into its local source, but it's flowing into an external or far away ground. We want to minimize that in order to minimize common mode noise and also to minimize the radiated noise. What we do here is on the right hand side diagram, we use a faraday screen that is not basically connected to the chassis. But it's connected to its local ground, returning its current back to the local source. Drain-heatsink (chassis) capacitance of thru-hole components and its neutralization with a Faraday screen. 92

Well-Chosen Components/Packages Reduce Amplitude of Ringing Waveforms
Resistors/Capacitors Inductors/Transformers Power MOSFETs Rectifier Diodes Used as freewheeling diodes in asynchronous bucks, secondary side rectifiers for transformer-based topologies, voltage doublers, valley fill circuits, etc. Same package concerns as FETs Budget space for RC snubber across diodes Several different types General purpose – High reverse voltage but too slow for SMPS Schottky – Low Vf, very fast but limited to <100V apps Ultra and super fast – High Vr, fast recovery, low leakage, but high Vf Also rectifier diodes, there's one thing to consider with rectifier diodes is that we know we want to use ultrafast or superfast diodes in order to limit the current, the reverse current. But we also know that by using slower general purpose diodes, it's too slow for the switch mode power supply, which increases our losses and decreases efficiency. On one hand, the slower switching of a rectifier diode really helps us with the EMI but doesn't help us with losses. Whereby the Schottky diode and the ultrafast and superfast diodes certainly help us with losses. But because of its ability to switch fast, it doesn't help us with EMI. They occupy different ends of where we need to be. That's the same with MOSFETs, I didn't make mention of that, but switching MOSFETs as well. You certainly want to make sure that you have a happy medium between transitional losses and switching too fast, which will cause higher noise levels at the switching frequency. 93

Reverse recovery effects EMI
Resistors/Capacitors Inductors/Transformers Power MOSFETs Rectifier Diodes Main trade-off Faster recovery = higher efficiency but higher EMI Use Schottky diodes for best performance (low capacitive types like MBR series even better) Reverse recovery effects and EMI, you can see here that if it is the TRR, or Reverse Recovery Time, if that's longer, obviously the reverse currents are going to be higher. And thereby the losses are going to be higher too. We want to the keep the TRR as small as possible to keep reverse currents, or the di by dt, that's going to be higher, the dt's going to be higher, but the reverse currents are going to be lower. 94 94 94

Thank You Questions? 95

Download ppt "Switching Power Supply Design: EMI Reduction"

Similar presentations