1. FPGA PID DC Motor Controller Galt Design, Inc.

2. Short Description PID control of DC Motor through PWM pulsing of H_Bridge PID control of DC Motor through PWM pulsing of H_Bridge Takes input from Quadrature decoder for position information Takes input from Quadrature decoder for position information PID, deadband, integrator_limit,ramping, timeout settings available PID, deadband, integrator_limit, ramping, timeout settings available Available in both Verilog and VHDL HDL code Available in both Verilog and VHDL HDL code Can be used in both FPGA and ASIC designs Can be used in both FPGA and ASIC designs DC Motor Timeout detector. Shuts down drive if motor jams.

3. PID Thermal controller FPGA DC_motor H-Bridge Quadrature CPU interface 2 1 PID DC Motor Controller PID motor controller FPGA Example Quadrature counter Requested position, parameters 32 Done Interrupt

4. PID Motor Control Diagram -  Accumulator Positive or Negative PWM pulses to DC Motor H- bridge Error ** I term P term * D term Derivative Gain Register Integral Gain Register Proportional Gain Register Temperature Setpoint Register Quadrature Encoder Input

5. Example FPGA Code Organization Quadrature_decoder.v Pid_controller.v Dc_motor_timeout.v dc_motor_control.v

6. Contact information Contact us with questions or for a quote: pid@galtdesign.com