1. P.Considine/P.Carbou Nov 2006 1 Switched Capacitor Filters

2. P.Considine/P.Carbou Nov 2006 2 Plan Lecture1: Integration Techniques Switched capacitor theory Parasitic effects in switched capacitor integrators Lecture2: Switched capacitor noise Continuous time domain to sampled domain mapping Synthesis methods

3. P.Considine/P.Carbou Nov 2006 3 Pole Requirements for stable systems S-Plane jw  jb a Z-Plane For a stable continuous-time system All poles, s i must be in LHP (  i <= 0) Transfer Function cannot have poles with positive real parts For a stable sampled system All poles, Z i must obey | Z i | < 1  Laplace Transform: F(s) =  f(t) e st dt 0 From Inverse Laplace Transform all poles, s i =  i + jw i of form 1/(s-  i ), 1/((s –  i ) 2 +b i 2 ),etc contain factor: e  iT   for  i >=0  Z-Transform: F(z) =  f(nT) z -n where z = e sT n=0 From Inverse Z-Transform all poles, Z i = a i + jb i of form 1/(Z-aT), 1/(Z – aT) 2, contain factor: a nT = | Z i | n in the transient response   for | Z i |>1 Objective: Map a Continuous-Time (C.T.) domain (analog) filter transfer function(T.F.), Ha(Sa) to a Discrete-Time (D.T) domain transfer function, H(z) by replacing Sa by some function Sa = f(z) Ha(Sa)  H(z) with Sa = f(z) Question: What are requirements of f(z) to be a “good” mapping?

4. P.Considine/P.Carbou Nov 2006 4 Requirements for “good” mapping function f(z) Ha(Sa)  H(z) with Sa = f(z) e.g., Continuous Time Integrator Ha(sa) = 1/sRC Requirements for f(z): 1)f(z) is a rational function of z, i.e.,a division of two polynomial functions 2)For s = jw, |Z|=1 must be true 3)For Re(s) < 0, |Z|<1 must be true

5. P.Considine/P.Carbou Nov 2006 5 Integration Techniques1 (Forward Euler Example) For a C.T.filter with T.F. =Ha(Sa), it’s response can be determined from it’s state equations, a system of 1 st order equations which describe it. nT-T nT Forward Euler g i (t) …Eq.1 …Eq.2 Now Eq.1 has been transformed into difference form. Numerical Integration can be used to evaluate this integral: e.g., for the Forward Euler approximation Now derive the state equations for sampled data systems: Integrating Eq.1 over the nth sampling period: Where: x i are the state variables of the filter g i (t) are linear functions of x i (t) and the input signal And we assume x i (t) = 0 for t <= 0

6. P.Considine/P.Carbou Nov 2006 6 Integration Techniques2 nT-T nT a) Forward Euler x i (nT) - x i (nT-T) = X i (z) – z –1 X i (z)=  Solve for f(z)= G i (z)/X i (z) Tg i (nT-T) T. z –1. G i (z) Tg i (nT) T. G i (z) (T/2)(g i (nT-T) + g i (nT)) (T/2)( z –1. G i (z)+ G i (z) ) (Not used because unstable in Z-domain) nT  g i (t)dt =  dx i (t)/dt.dt = x i (nT) - x i (nT-T) nT-T  f(z). X i (z) = G i (z) for some function f(z) g i (t) b) Backward Euler nT-T nT nT-T nT c) Trapezoidal/ Bilinear nT-TnT d) Mid-point In the same way, different numerical Integration techniques will give different approximations of  g i (t)dt and each will yield a different function f(Z) for transforming from Continuous-time to Discrete-Time domains. Integration Technique:

7. P.Considine/P.Carbou Nov 2006 7 Integration Techniques3 H (j  a ) H (e jwT ) Continuous-Time Filter Sampled-Time Filter (Forward Euler) Sampled-Time Filter (Backward Euler) Dominant poles (I.e., closest to j  axis in s-plane) move towards |Z|=1. (To see this let  a  0) => Results in peaking in passband In Forward Euler Zero’s on jw axis are not mapped onto |Z|=1. So no zero’s in Discrete-Time T.F. => Deteriorated stopband response In Backward Euler, dominant poles move away from |Z|=1 => Results in rounding in passband In Backward Euler, Zero’s on jw axis not mapped to |Z|=1 => Deteriorated stopband response Check Mapping properties of f(z) vs Requirements e.g., For Forward Euler Mapping: 1)F(Z) is a Rational Function of Z? Yes. 2)Let s a = j  a => j  a = (Z-1)/T => z = j  a T + 1 But |z| = 1 only at  a = 0 |z| ~= 1 at  a T >  a jb a Z-Plane Image of j  axis 1 From how F(Z) functions map poles and zeros from C.T. to D.T. domains we can see:

8. P.Considine/P.Carbou Nov 2006 8 Switched Capacitor Theory Resistor & equivalent switched capacitor. Interest of switched capacitors in IC. Basic structures of switched capacitor integrators. Comparison with continuous time integrator.

9. P.Considine/P.Carbou Nov 2006 9 Principle(Parallel mode) R VAVA VBVB C 11 22 VBVB VAVA 11 22 Tc

10. P.Considine/P.Carbou Nov 2006 10 Principle(Serial mode) R VAVA VBVB 11 22 VBVB VAVA 11 22 Tc C

11. P.Considine/P.Carbou Nov 2006 11 Interest of switched capacitors Pole accuracy: –Tolerance on integrated resistor ( σ R ) 20% to 30% –Tolerance on integrated capacitor ( σ C ) 10% to 20%  Accuracy on RC poles around 50% (Or more likely σ RC = (σ R 2 +σ C 2 ) 0.5 = 0.36 ) –Tolerance on integrated capacitor matching 0.1% –Tolerance on clock frequency few ppm –Accuracy on SC poles better than 1% Components size –High resistance value : PREVIOUSLY BIG RESISTOR  SMALL (Switched) CAPACITOR

12. P.Considine/P.Carbou Nov 2006 12 Continuous Time Integrator 4/Continuous Time Integrator V IN - + CICI V OUT +- R Transfer function:

13. P.Considine/P.Carbou Nov 2006 13 Switched Capacitor Integration Techniques Correspondance Table Summary Parallel Switched-Capacitor Integrator  Forward Euler Mapping Serial Switched-Capacitor Integrator  Backward Euler Mapping Serial/Parallel Switched-Capacitor Integrator  Bilinear Mapping We will establish on the following pages:

14. P.Considine/P.Carbou Nov 2006 14 Switched Capacitor Integrator 1/ Parallel Integrator - + CUCU 11 22 CICI V OUT V IN + + - - 11 22 Sampling Instant a) Calculate Transfer Function: b) Relate S.D. T.F. to Integration model: This is equivalent to Forward Euler integration X Final-Initial For  (  Q)=0 at node X At +Node of Capacitors

15. P.Considine/P.Carbou Nov 2006 15 Switched Capacitor Integrator 2/ Serial Integrator - + 11 22 CICI V OUT V IN + + - - 11 22 CUCU Sampling Instant a) Calculate Transfer Function: b) Relate C.T. T.F. to Integration model: Equivalent to Backward Euler Integration Final-Initial For  (  Q)=0 at node X At +Node of Capacitors X

16. P.Considine/P.Carbou Nov 2006 16 Switched Capacitor Integrator 3/ Parallel/Serial Integrator V IN - + 11 22 CICI V OUT + + - - C U1 C U2 - + 11 22 V IN Sampling Instant Equivalent to Bilinear Integration a) Calculate Transfer Function: b) Relate C.T. T.F. to Integration model: Final-Initial For  (  Q)=0 at node X At +Node of Capacitors X 2 + - Notice: For same RC pole Cu1=Cu2=Cu/2 of previous serial or parallel integrators

17. P.Considine/P.Carbou Nov 2006 17 Comparison of parallel and C.T. Integrators Sample Domain Frequency,w (normalised to w0)

18. P.Considine/P.Carbou Nov 2006 18 Comparison of serial and C.T. Integrators

19. P.Considine/P.Carbou Nov 2006 19 Comparison with parallel/serial integrator i.e.,BILINEAR TRANSFORM

20. P.Considine/P.Carbou Nov 2006 20 Parasitic effects in SC integrators Clock overlap Parasitic capacitors Switch resistance Clock feed through Charge injection Mismatch

21. P.Considine/P.Carbou Nov 2006 21 Need of non overlapping clocks V OUT V IN - + CUCU 22 CICI + + - - 11 CICI CICI V OUT - + CUCU 11 + + - - 22 V IN - + CUCU + + - - 22 11 11 22 Sampling Instant

22. P.Considine/P.Carbou Nov 2006 22 Non overlapping clocks generator D1 D2 D1 D2 D1 CK CK1N CK1P CK2N CK2P CK1P CK1N CK2N CK2P CK

23. P.Considine/P.Carbou Nov 2006 23 Parasitic Capacitors (Parallel Integrator) 11 22 V IN Sampling Instant - + CUCU 11 22 CICI V OUT V IN + + - - Cp2 Cp1 THIS TYPE OF INTEGRATOR IS SENSITIVE TO PARASITIC CAPACITORS ( INTERCONNECT, JUNCTIONS) POLE ACCURACY IS NO LONGER TRUE X

24. P.Considine/P.Carbou Nov 2006 24 Structure insensitive to parasitic capacitor (Equivalent Parallel Integrator) 11 22 V IN Sampling Instant V OUT V IN NON-INVERTING INTEGRATOR SAME TRANSFER FUNCTION AS PARALLEL INTEGRATOR EXCEPT THE SIGN POLE ACCURACY IS RECOVERED - + 11 22 CICI +- Cp2 Cp1 Cu 11 22 + + + X

25. P.Considine/P.Carbou Nov 2006 25 Structure insensitive to parasitic capacitor (Equivalent Serial Integrator) 11 22 V IN Sampling Instant V OUT V IN INVERTING INTEGRATOR SAME TRANSFER FUNCTION AS SERIAL INTEGRATOR POLE ACCURACY IS RECOVERED - + 22 22 CICI +- Cp2 Cp1 Cu 11 11 + + + X

26. P.Considine/P.Carbou Nov 2006 26 Switch resistance C RON VIN 11 22 Ts After charging C for one (non-overlap) clock phase: i.e., RON.C pole frequency must be more than twice the sampling frequency for capacitor charging error of <0.1%:

27. P.Considine/P.Carbou Nov 2006 27 Clock Feed-Through VIN C CgsCgd VG VC SWITCH ON VG ICgs TRANSITION ON ->OFF SWITCH OFF  CLOCK FEED-THROUGH INDUCES DC OFFSET BUT NO NON-LINEARITY because no dependency on V IN

28. P.Considine/P.Carbou Nov 2006 28 Clock Feed-Through compensation methods (1) VG1 ICgs1 VIN C Cgs1Cgd1 VG1 VC Cgs2Cgd2 VG2 WW/2 VG2 ICgd2 ICgs2 SINGLE TYPE OF SWITCH NMOS OR PMOS DUMMY SWITCH TRUE IFAND

29. P.Considine/P.Carbou Nov 2006 29 Clock Feed-Through compensation methods (2) VGn VIN C VC CgsnCgdn VGn CgspCgdp VGp ICgsn ICgsp COMPLEMENTARY SWITCHES NMOS AND PMOS TRUE IFAND

30. P.Considine/P.Carbou Nov 2006 30 Charge Injection - ------- C - - - - - -- - C SWITCH ON SWITCH OFF Pwell N+N+ N+N+ Vg=+V Vg=0 When Vg=+V is applied, P-type acceptor Holes are repelled from surface Negative acceptor atom space charge left in depletion layer As Vg increases, an inversion layer of electrons forms at surface This negative charge is redistributed when Vg  0 Pwell N+N+

31. P.Considine/P.Carbou Nov 2006 31 Charge Injection VIN C VG VC SWITCH ON TRANSITION ON ->OFF SWITCH OFF  CHARGE INJECTION INDUCES NON-LINEARITY because charge injection has a dependency on V IN D  1-   DEPENDS ON THE IMPEDANCES SEEN AT VIN AND VC TERMINALS

32. P.Considine/P.Carbou Nov 2006 32 Charge Injection compensation method 22 Cu  2D  1D 11 22 Cu  2D  1D 11 22 Cu  2D  1D 11 22 Cu  2D  1D 11 Cu 11  1D  2D 22 Cu 11  1D  2D 22 SAMPLING CHARGE INJECTION HIZ AT Cu SIDE CLOCK NON- OVERLAP RE-DISTRIBUTION CHARGE INJECTION SAMPLING Towards low- impedance input Don’t care

33. P.Considine/P.Carbou Nov 2006 33 Mismatch 5  55 55 55 55 25  C1 C2 C1 C2

34. P.Considine/P.Carbou Nov 2006 34 Noise in SC integrators Low pass filtering Sampling Aliasing Holding

35. P.Considine/P.Carbou Nov 2006 35 SAMPLING & HOLD LOW-PASS FILTERED WHITE NOISE PSD WHITE NOISE PSD AFTER HOLD PSD AFTER LPF LPFSAMPLEHOLD WHITE NOISE fc PSD AFTER SAMPLING C RON -20 -15 -10 -5 0 5 10 -4-2024 Gain(dB) Frequency -20 -15 -10 -5 0 5 10 -4-2024 Gain(dB) Frequency 10*log10(s(x)*sinc(x)**2) -20 -15 -10 -5 0 5 10 -4-2024 Gain(dB) Frequency -3dB frequency Fp=2 -20 -15 -10 -5 0 5 10 -4-2024 Gain(dB) Frequency Sampling frequency Fs=1 PSD = Power Spectral Density

36. P.Considine/P.Carbou Nov 2006 36 LOW-PASS FILTERED WHITE NOISE C RON 4kTRdf RON C Switch model: Resistor in series with Johnson Noise source  Total noise power is independent of R ON

37. P.Considine/P.Carbou Nov 2006 37 SAMPLING LOW-PASS FILTERED WHITE NOISE PSD AFTER LPF PSD AFTER SAMPLING SAMPLING Under- sampling factor Ondulation function  1when .fp.Ts>>1 -6 -5 -4 -3 -2 0 -3-20123 Gain(dB) Frequency 10*log(g(f)**2) -6 -5 -4 -3 -2 0 -3-20123 Gain(dB) Frequency -14 -12 -10 -8 -6 -4 -2 0 -3-20123 Gain(dB) Frequency   As R ON decreases, PSD SAMPLED increases

38. P.Considine/P.Carbou Nov 2006 38 EFFECT OF UNDERSAMPLING ALIASING Fp=2 Fs=10 Fp=2 Fs=5 Fp=2 Fs=2 Fp=2 Fs=1 22 0

39. P.Considine/P.Carbou Nov 2006 39 HOLDING SAMPLED LOW-PASS FILTERED WHITE NOISE PSD AFTER SAMPLING Under- sampling factor Double sided PSD PSD AFTER HOLD Hold function -15 -10 -5 0 5 10 -3-20123 Gain(dB) Frequency 10*log10(usf(x)) -20 -15 -10 -5 0 5 10 -3-20123 Gain(dB) Frequency -20 -15 -10 -5 0 5 10 -3-2.5-2-1.5-0.500.511.522.53 Gain(dB) Frequency EQUIVALENT BANDWIDTH …calculated in Mathematica

40. P.Considine/P.Carbou Nov 2006 40 Switching Noise Conclusions  The total noise in the baseband (-f c /2 < f < f c /2 ) due to replicas is kT/C  Aliasing due to sampling concentrates the full noise- power of R ON into the baseband  It is futile to reduce R ON below T settling requirements since, while direct thermal-noise PSD decreases, aliasing increases, and the two effects cancel  Increasing C and f c reduces both direct and aliased thermal-noise PSD’s C since reduces total noise power kT/C fc since baseband is wider while total noise kT/C is constant

41. P.Considine/P.Carbou Nov 2006 41 Idea: Pre-Distortion Each of these integration techniques distorts the frequency axis, w, in the sampled-domain Pre-distortion of the continuous-time function frequency variable, w a to w ap with a suitable pre-distortion function, and then mapping the resulting pre-distorted filter function Ha(Sap) to the Z-domain will avoid distortion of the original poles and zeros in the Z-domain filter.  This will be illustrated in the next example

42. P.Considine/P.Carbou Nov 2006 42 VIN 11 22 CICI - + Cu 11 22 VOUT1 - + 11 22 CICI Cu 11 22 VOUT2 Overall phase error =  Tc Predistortion of single-type (Forward Euler) integrator

43. P.Considine/P.Carbou Nov 2006 43 Predistortion of single-type (Forward Euler) integrator

44. P.Considine/P.Carbou Nov 2006 44 Poles pre-distortion CONTINOUS TIME FILTER HAS TO BE SYNTHESIZED USING POLE PRE- DISTORTION METHOD TO OBTAIN THE DESIRED FREQUENCY RESPONSE WITH SAMPLED FILTER Predistortion of single-type (Forward Euler) integrator

45. P.Considine/P.Carbou Nov 2006 45 Method1: Poles pre-distortion Distorted Pole Pre-Distorted Pole Desired Pole {-1,1} 0.01<Fs<10 Predistortion of single-type (Forward Euler) integrator

46. P.Considine/P.Carbou Nov 2006 46 Predistortion of single-type (Backward Euler) integrator

47. P.Considine/P.Carbou Nov 2006 47 Predistortion of single-type (Backward Euler) integrator

48. P.Considine/P.Carbou Nov 2006 48 VIN 11 22 CICI - + Cu 11 22 VOUT1 - + 11 11 CICI Cu 22 22 VOUT2 Overall phase error =0 Predistortion of both-type (Bilinear) integrator

49. P.Considine/P.Carbou Nov 2006 49 Predistortion of both-type (Bilinear) integrator

50. P.Considine/P.Carbou Nov 2006 50 Ha(Sa)  H(z) with Sa = f(z) Instead pre-warp (or “pre-distort”) w a  w ap and use w ap instead in f(z) i.e., w does not map onto w a and so w-axis in z- domain is warped (i.e., bent or compressed) i.e., Pre-warping now maps w  w a So poles, zero’s will now be mapped correctly Example: Bilinear Transform Notation: w a = continuous-time frequency variable w ap = pre-distorted continuous-time frequency variable w = discrete-time domain frequency variable Predistortion of both-type (Bilinear) integrator

51. P.Considine/P.Carbou Nov 2006 51 SC Filters synthesis methods Synthesis from LC ladder network –Mapping method1 –Mapping Method2 Ladder Filter Design Example Synthesis from active RC filters –Bi-quadratic switched capacitor example Use of bilinear transform Exact transfer function

52. P.Considine/P.Carbou Nov 2006 52 SC Filters synthesis methods Synthesis from LC ladder network –Mapping method1 –Mapping Method2 Ladder Filter Design Example Synthesis from active RC filters –Bi-quadratic switched capacitor example Use of bilinear transform Exact transfer function

53. P.Considine/P.Carbou Nov 2006 53 Synthesis from RLC ladder(1) C1 R1 C3C5 R2 L2L4 V0 V1V3V5V6 V2V4 I0I2I4 I1I3I5I6 Get nodal equations using Kirchoff’s Laws: 1)  I=0 at node x 2)  V=0 around loop y and solve…

54. P.Considine/P.Carbou Nov 2006 54 Synthesis from RLC ladder(2) I2 V0 V1 V2 V3V4 V5 V6V OUT V IN I0 I1I3I4 I5 I6 V0 V1 V2 V3V4 V5 V6V OUT V IN Vp0 =I0.R Vp1 =I1.R Vp2 =I2.R Vp3 =I3.R Vp4 =I4.R Vp5 =I5.R Vp6 =I6.R

55. P.Considine/P.Carbou Nov 2006 55 Synthesis from RLC ladder(3) V0 V1 V2 V3V4 V5 V6V OUT V IN Vp0 =I0.R Vp1 =I1.R Vp2 =I2.R Vp3 =I3.R Vp4 =I4.R Vp5 =I5.R Vp6 =I6.R

56. P.Considine/P.Carbou Nov 2006 56 SC Filters synthesis methods Synthesis from LC ladder network –Mapping method1 –Mapping Method2 Ladder Filter Design Example Synthesis from active RC filters –Bi-quadratic switched capacitor example Use of bilinear transform Exact transfer function

57. P.Considine/P.Carbou Nov 2006 57 Ladder Filter Design Example (1) V1 V3 L2Rs C1 C3 RLRL Vin Vout I2 Starting point: LCR prototype “Ladder” filter configuration Get nodal equations using Kirchoff’s Laws: 1)  I=0 at node x 2)  V=0 around loop y Subsequent equations alternate from V to I

58. P.Considine/P.Carbou Nov 2006 58 Ladder Filter Design Example (2) Arrange equations schematically. Each -1/s gain stage will become an integrator

59. P.Considine/P.Carbou Nov 2006 59 Ladder Filter Design Example (3) Replace each -1/s gain stage by it’s continuous time equivalent circuit

60. P.Considine/P.Carbou Nov 2006 60 Ladder Filter Design Example (4) Replace R’s by switched capacitors

61. P.Considine/P.Carbou Nov 2006 61 SC Filters synthesis methods Synthesis from LC ladder network –Mapping method1 –Mapping Method2 Ladder Filter Design Example Synthesis from active RC filters –Bi-quadratic switched capacitor example Use of bilinear transform Exact transfer function

62. P.Considine/P.Carbou Nov 2006 62 SC Building Blocks Φ2Φ2 Φ1Φ1 Φ1Φ1 Φ2Φ2 V IN C Φ1Φ1 Φ1Φ1 Φ2Φ2 Φ2Φ2 C C Non-Inverting S/C (*) Inverting S/C Unswitched C ΔQΔQ Φ2Φ2 Φ1Φ1 V IN V OUT Φ2Φ2 Φ1Φ1 V IN VNVN V N-1 VNVN VNVN V N-2 C V IN ΔQΔQ -CZ -1 V IN ΔQΔQ C(1-Z -1 ) V IN ΔQΔQ (-1/C)/(1-Z -1 ) V IN ΔQΔQ Requiv = T/C = 1/(f.C) For positive R’s |Requiv| = T/C = 1/(f.C) For negative R’s Z-domain Transfer Function V OUT - + CICI + - Φ1Φ1 Φ1Φ1 Φ2Φ2 Φ2Φ2 V IN C (*) Note: Is an inverting integrator V OUT

63. P.Considine/P.Carbou Nov 2006 63 Cascade Filter Design: Biquad Example (1) Second-order S/C Biquad: Lnx exex y=x Where: (definition)  0 = pole frequency of pole s p =  p +  p Q = Quality factor of H(s) jw  jw p pp spsp As Q increases, sp becomes closer to the jw-axis => Get peaking of H(jw) near w o

64. P.Considine/P.Carbou Nov 2006 64 Biquad Design Example (2) Create a simple block diagram of gain elements and integrators from the rearranged transfer function equation Create an active-RC realization from above block diagram by: - Assuming each integrator has a current input (or a sum of current inputs), a voltage output, and a feedback capacitor, C Then it’s transfer function is: Vout/Iin=-1/sC=-1/s if C=1 - Replace constant gains with resistors with equivalent current, e.g., for w 0 in block diagram above Iint1(in)=Vout*w 0, becomes R=1/ w 0 - Replace complex gains with equivalent C or R,C circuit, e.g., K1+K2s is equivalent to a resistor 1/K1 in parallel with a capacitor K2: I = Vin.(K1+K2s)=Vin.(Y1+Y2) Y1=1/Z1=K1, Y2=1/Z2=K2s

65. P.Considine/P.Carbou Nov 2006 65 Biquad Design Example (3) Use switch-cap building blocks to replace resistors: - Non-inverting for R>0, C=T/R - Inverting for R<0, C=T/|R| - Remove all redundant switches C1=T.K0/w 0 C2=C3= T.w 0 C4= T.w 0 /Q C1’=T.K1 C2’= K2

66. P.Considine/P.Carbou Nov 2006 66 Note that in the Biquad example above we assumed |wT|<< 1  It is fairly easy to get the exact transfer function (T.F.) of the final circuit above by replacing each integrator and branch by it’s z-domain T.F. Refer to Z-domain equivalents on Building Blocks slide Then compare required H(Z) polynomial with calculated T.F. and choose suitable values for components. This will result in a more accurate filter realization.  See the following 4 slides Limitation: For filters with High-Q poles, I.e., close to jw-axis (or to unit circle in Z-domain) response becomes sensitive to process variations. May become impractical, non-economical Biquad Realisation Footnote

67. P.Considine/P.Carbou Nov 2006 67 SC Filters synthesis methods Synthesis from LC ladder network –Mapping method1 –Mapping Method2 Ladder Filter Design Example Synthesis from active RC filters –Bi-quadratic switched capacitor example Use of bilinear transform Exact transfer function

68. P.Considine/P.Carbou Nov 2006 68 - + - + 11 G 22 11 22 22 11 H D E B C 22 A 11 11 22 22 11 11 22 I 22 11 J F - + + - +-+- Getting exact transfer function of synthesized Biquad Switched Capacitor Equivalent

69. P.Considine/P.Carbou Nov 2006 69 Synthesis from RC active filters (3) CHARGE RE-DISTRIBUTION TABLE Getting exact transfer function of synthesized Biquad Switched Capacitor Equivalent

70. P.Considine/P.Carbou Nov 2006 70 Use of bilinear transform Getting exact transfer function of synthesized Biquad Switched Capacitor Equivalent

71. P.Considine/P.Carbou Nov 2006 71 Use of bilinear transform Getting exact transfer function of synthesized Biquad Switched Capacitor Equivalent

72. P.Considine/P.Carbou Nov 2006 72 Use of bilinear transform pre-distortion Getting exact transfer function of synthesized Biquad Switched Capacitor Equivalent

73. P.Considine/P.Carbou Nov 2006 73 Use of bilinear transform Coefficients identification Getting exact transfer function of synthesized Biquad Switched Capacitor Equivalent

74. P.Considine/P.Carbou Nov 2006 74 References “Analog MOS Integrated Circuits for Signal Processing” by Roubik.Gregorian, Gabor C.Temes “CMOS Analog Circuit Design” by Phillip E.Allen, Douglas R.Holberg “Analysis and Design of Analog Integrated Circuits” by Paul R.Gray, Robert G.Meyer P.Considine Oct, 2001