1. A CMOS circuit for Silicon Drift Detectors readout
in exotic atom research
L. Bombelli, C. Fiorini, T. Frizzi, A. Longoni
Politecnico di Milano and INFN, Milano, Italy
Work supported by Italian INFN and EC (SIDDHARTA project)

2. What it as ‘exotic’ atom?
Hydrogen atom
Kaonic Hydrogen
n=1 p p
n=2
n=1 K-
n=25 e- K-
2p->1s (Ka)
X ray of interest

3. Shift ε = ≈ 300eV
Width Г= ≈ 450eV
(DEAR experiment)
Main measurement
issues:
- peak stability (< 1‰)
- E resolution (< 150eV FWHM)
- background suppression by triggering with Kaon monitor

5. The Siddharta collaboration: LNF-INFN Frascati, Italy
Frascati-LNF-INFN
DAFNE collider
The Siddharta collaboration:
LNF-INFN Frascati, Italy
MPI, PNSensor Munich, Germany
Politecnico–INFN Milano, Italy
IMEP Wien, Austria
IFIN-HH Bucarest, Romania
...

6. on-chip JFET and feedback cap
SDD board
detector
+readout
module
readout board
3 SDD (1cm2 each) with
on-chip JFET and feedback cap

7. Chip architecture

8. Features 8 analog channels Charge amplifier
Shaper (3us, 1.5us, 750ns, 680ns)
Fast Shaper & PileUp Rejector
BLH
Peak Stretcher
LT and HT triggers
Digital section
Address
LT (real time)
Differential Analog MUX
Acknowledge input
33mm2, AMS 0.35mm

9. “Drain feedback” Charge Preamplifier configuration
Rg: dynamic resistance
of the ‘weak’ avalanche
reset mechanism -A I0
Isignal CF Rg
Pre
out C1 R1 A1
Cgd
Detector chip
high-freq.
loop
low-freq.

10. -A I0
Isignal CF Rg
Pre
out C1 R1 A1
Cgd
high-freq.
loop
low-freq.
Preamplifier response well approximated by a single pole:
tdecay = K A1
R1C1
K = Cf
Cgd
tdecay independent from Rg, therefore from leakage+signal current
Pole/Zero compensation possible by means of A1 (exploited in the chip)

11. The CMOS implementation
15 V compatible devices in the 3.3V-0.35mm -A I0
Shaper
Isignal CF Rg
Pre
out C1
Detector
chip Gm RA R1 RZ CZ
gain adjustable
transconductance
amplifier
Ibuf
CMOS chip
Cgd
voltage gain A1 = GmR1
t = K
C1 R1
GmR1
K = Cf
Cgd
adjustment of the
decay time

12. The main amplifier VOUT = Iin·R·l  RA = R·l Isignal RA CF gmVin
Pre
out RA
Ibuf
gmVin
voltage gain = gmJFET·RA > 5000
 RA ~ 10MW
VOUT = Iin·R·l
 RA = R·l
low-noise
current
de-multiplier
C. Fiorini, M. Porro, IEEE TNS, 2004
R.L. Chase, et al., NIM A409,1998

13. The adjustable pole-zero network
not precisely
known a priori
RZCZ = tpreamplifier
fixed
adjustable
Isignal RA CZ
Ibuf CF -A
Shaper I0
Pre
out RZ IS
the role of RZ is to provide
a current
IS=VOUT/RZ
which is already available
in the transimpedance
stage and need just to
be duplicated and sent
to the shaper

14. Implemented baseline holder (BLH)
Vbaseline CB RB C1 R1
Vdrain
Ireset Rg Gm
Isignal RA CZ
Ibuf CF -A
Shaper I0
Pre
out RZ
The JFET Drain voltage drifts due to changes of the reset current
Drain, preamplifier output, shaper output are all DC coupled
Required Drain DC shifts are provided by the BLH whose extended
action back to the preamplifier stabilize also this last one
Low-pass filter guarantees unchanged signal processing

15. The shaping amplifier shaper preamplifier 4 selectable peaking timesRz C
Req Cz
6th order unipolar shaping
shaper
preamplifier
4 selectable peaking times
( ms)

16. Experimental results Cstray Cload = Cstray +33pF
SDD detectors
Siddharta CHIP
Analog output
Digital output
8 channel input
Cstray
Pre
out
Cload = Cstray +33pF
Cload = Cstray (~10pF)

17. external continuous control of the decay time of the preamplifier…
1.8V
… and of the pole-zero
adjustment of the
shaper waveform

18. Spectroscopy measurements
Temperature: -20°C
5mm2 SDD

19. Linearity
Integral non- linearity error at the Multiplexer output within ±0.1% in the 2-20keV range

20. Multiplexer logic

21. OUT SHAPER
BUFFER OUT +
BUFFER OUT - LT
ACK HT

22. 1° event amplitude (on channel 0)1
1° event amplitude (on channel 0)
2° event (on Channel 4)

23. 1° event amplitude (on channel 0)
2° event (on Channel 4)
amplitude out of
range:
amplitude discarded
event occurrence and address both recorded 1 1

24. Pile-up rejection this events are directly rejected inside the chip
two photons detected by 2° fast shaper
this events are directly rejected inside the chip

25. Different events close occurring on different channels
20ns
OUT+ LT
ACK
lost events occurring on
different channels at a rate
of 100kcounts/s/channel:
~ 3% (foreseen)
(to be compared with about
>5% pile-up rejection on
each single channel)

26. Conclusions
A 8 channels prototype of CMOS readout chip for the
Siddharta experiment with pre-shaper, fast MUX readout,
channel address and timing signals has been developed and
tested
Functionalities and noise performances are satisfactory
Deeper tests are on the way at LNL-INFN and installation
in the experiment is foreseen in early 2007