1. CS 140L Lecture 4 Professor CK Cheng 10/22/02

2. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

3. Flip flop FDCE D CE C CLR Q CLR CE D C Q 1 X X X 0 0 0 X X No change 0 1 1 1 0 1 0 0 Asynchronous Clear Inputs Output Clock Enable CLK = 0 CLK = 1

4. D Q CLK t t t t setup t hold D Q tcqtcq

5. 2) 3 bit shift register D Q CLK D Q D Q 0 0 X X X 11 0 X X 2 0 1 0 X 31 0 1 0 41 1 0 1 50 1 1 0 60 0 1 1 71 0 0 0 Time Steps A B C D A B C D

6. 3 bit counter (asynchronous) T Q CLK T Q T Q t A C B t t 1 010 110 B C t 1 1 7 6 5 4 A 1 1 1 Assume A(0) = B(0) = C(0) = 0 0 0 0 0 0 11 1 1 7 2 1 1 0 6 31 0 1 5 41 0 0 4 50 1 1 3 60 1 0 2 70 0 1 1 Time C B A