1. VHDL Synthesis of a MIPS-32 Processor Bryan Allen Dave Chandler Nate Ransom

2. Completed Project 5-stage Pipelined MIPS-32 Processor Hazard Detection Data Forwarding Project Goal: Efficient VHDL Coding for Small- Area Synthesis

3. Subset of Instructions (the full MIPS-32 instruction set will not be implemented) add, addU, addI, addIU and, andI div, divU mult, multU nor, or, ori, xor, xori sll, sra, srl sub, subu lui slt, sltU, sltI, sltIU beq, bgez, bgtz, blez, bltz, bne j, jr lb, lw, lbu sb, sw mfhi, mflo, mthi, mtlo

4. Dataflow – Pipelining w/o Forwarding

5. Dataflow - Pipelining with Forwarding

6. Architecture - Control

7. Architecture – Pipeline with Forwarding

8. Architecture - Hazard Detection

9. Main Components Control Unit Registers and Memory Hazard Detection Unit Forwarding Unit ALU

10. Simulation Results - 1

11. Simulation Results - 2

12. Simulation Results - 3

13. Synthesis Results

14. 2.32176022.13 Data Memory 2.3811011.88 Forwarding Unit 2.04196370.38 ALU 2.3677.43 Hazard Detection Unit 2.25150129.42 Register Bank 0.51976.03 Sign Extender 2.31869.31 Control 2.17147963.09 Instruction Memory 1.383760.84 Program Counter 1.65835.48 WriteBack Stage 3.23183921.88 Memory Stage 2.55217061.63 Execute Stage 2.1188066.97 Instruction Decode Stage 3.7158685.64 Instruction Fetch Stage 4.69896546.44 CPU (Top Level) Speed (ns)Area(nm 2 )Module

15. Final Results Violations: None Speed: 200 MHz Area: 896,546 gates Critical Path: Program Counter to Instruction Memory Register - 4.69 ns Max Input Delay: 1 ns Max Output Delay: 0.1 ns Max Input Capacitance: 0.012 pF Max Output Capacitance: 0.036 pF

16. Questions?