1. Research Potential We should develop a set of unified standardized CAD tools for synthesizing, verifying, testing and simulating of quantum computers. These methods and tools will be counterparts of what exists now in binary CMOS, like MVSIS. –Re-use spectral approaches, DDs, XOR logic, etc. –Use MVSIS as a part. –Use existing formats when possible –Link all tools that U Victoria and PSU already have –This is long term goal Development of these tools will require understanding of real quantum circuit technology.

2. New Frontiers Quantum Computer My statements below may be provocative and I may be wrong. But I am curious what you think.

3. Open Problems in Quantum Circuits Synthesis of binary quantum cascades with no garbage or small garbage –(Maslov, Dueck, Miller, Kerntopf, Perkowski, Khlopotine, Mishchenko, Curtis, Khan, Jha and Agrawal, Hayes, Markov) Synthesis of multiple-valued quantum cascades –(Muthukrishnan and Stroud, Miller et al, Khan, Perkowski, Curtis, Lee, Denler) –Universal gates, what are the counterparts of Toffoli and Fredkin gates? Fredkin Toffoli Multiple-valued logic for CMOS makes no sense. MV for quantum is reasonable and has in long term better potential than binary

4. Open Problems in Quantum Circuits What is the Fault Model for quantum circuits? –Technology dependent? People disagree Formal Verification of quantum circuits Test Generation for quantum circuits Fault Localization of quantum circuits Synthesis of testable quantum circuits Synthesis of fault-tolerant, error correcting quantum circuits. Classification and matching

5. Open Problems in Quantum Circuits What are universal gates? What are best components of universal gates (CV?) How to calculate costs of elementary gates for each quantum technology such as NMR or ion trap? What are the gates that can be truly realized in a quantum technology? Unlike n-input Toffoli What are the synthesis, analysis and test methods for sequential quantum circuits?

6. Open Problems in Quantum Circuits Invent new quantum algorithms. What are the principles to create quantum algorithms The nature of entanglement. Quantum computer architectures. Quantum formalisms. (Clifford algebras). Quantum Logic.

7. Nuclear Magnetic Resonance technology for quantum computing

8. What size of (binary) Quantum Computers can be build in year 2002? 7 bits

9. Is logic synthesis for quantum computers a practical research subject? CAD for physicists Yes, it is a useful technique for physicists who are mapping logic operations to NMR computers. CAD for physicists. Isaac Chuang, IBM

11. Quantum Circuit Synthesis is not the same as reversible logic synthesis

12. Problem We would like to assume that any two quantum wires can interact, but we are limited by the realization constraints Structure of atomic bonds in the molecule determines neighborhoods in the circuit. This is similar to restricted routing in FPGA layout - link between logic and layout synthesis known from CMOS design now appears in quantum. Below we are interested only in the so-called “permutation circuits” - their unitary quantum matrices are permutation matrices

13. A schematics with two binary Toffoli gates A B C DA B C D * * * * This is a result of our ESOP minimizer program, but this is not realizable in NMR for the above molecule, because there is no connection between A and C, for instance, in the molecule. A B C D Quantum wires A and C are not neighbors

14. So we have to modify the schematics as follows A B C D A B C D * * * * But this costs me two swap gates May be expensive

15. Design Issues 1. Local mirroring 2. Variable ordering versus gate ordering 3. Return to zero and folding 4. Realization of complex multiple-valued reversible gates (permutation gates) using directly 1-qubit and 2-qubit quantum primitives

16. “Return to Zero” and Folding Technique of local mirror can improve your ternary circuits, reduce the number of zeros in inputs. Here is the explanation for ternary logic

17. Molecule - Driven Layout and Logic Synthesis A B C D A B C D Allowed gate neighborhood for 2 qubit gates

18. Using Local Mirrors and Return-to-zero factorization

21. A better design of a large Toffoli Gate We can eliminate the last gate if we don’t mind flipping value of the scratch bit The purpose of the last Q (3) gate is to reset the scratch bit back to its original value 0. With one more gate we can obtain an implementation of Q (4) that works irrespective of the initial value of the scratch bit:

22. Solution One solution to connection problem in quantum NMR computers is to take into account these gate realization layout constraints in the logic synthesis phase – do not synthesize from non-realizable gates. Basic gate in quantum logic is a 2*2 (2-qubit gate). We have to build from such gates.

23. Complex Binary and MV Quantum Gates

24. Figure 4: Conceptual ternary multiplexer op = Logical Operations: +0, +1, +2 represent Galois Addition of constants 0, 1, and 2, respectively 01, 02, 12 represent logical replacement i.e. a 01 operation will replace 0->1, 1->0, and 2->2 Also, an arbitrary two-qubit quantum gate (described by a unitary matrix) can be constructed from such gates. These methods can be used to hierarchically synthesize larger circuits [55,59] and can be generalized to ternary (or in general multi-valued) logic (see Figure 4) for the realization of universal ternary permutative controlled gate. Universal quantum gate is created when operations are single-qubit ternary rotations

25. Figure 3. Smolin/DiVincenzo realization of Toffoli gate as a prototype of a regular controlled quantum structure: (a) standard notation, (b) notation used in this paper to emphasize the similarity Observe that any single-qubit operation can be written in the box, and also that any single qubit operation can be inserted to the control and data lines. The control can be from top (as in the Figure 3b) or from the bottom. The composition of this kind of multiplexed operations allows to create arbitrary permutative gate of reversible logic [55,59]. Also, an arbitrary two-qubit quantum gate (described by a unitary matrix) can be constructed from such gates.

26. Generalized Ternary Feynman Gate f 1  A B P Q If f1 is reversible, gate is correct, what about non- reversible f1, please check if the gate is still reversible

27. Generalized Ternary 3*3 Toffoli Gate A B P f 2  C Q R Do the same exercise as in previous slide, this will help you get intuition in MV logic.

28. Generalized Ternary n*n Toffoli Gate A1A1 A n-1 f n-1  A n-1  f n-1 (A 1, …, A n-1 ) AnAn... Do the same exercise as in previous slide, this will help you get intuition in MV logic.

29. Generalized Ternary 4*4 Fredkin Gate Q P f 2 A C R B S 0 0 1 1 D Rewrite this part to quantum ternary notation with Galois Logic

30. Generalized Ternary n*n Fredkin Gate A n-1 f ‘ n-1 (A 1, …., A n-1 ) + A n f n-1 (A 1, …., A n-1 ) A n-1 f n-1 (A 1, …., A n-1 ) + A n f ‘ n-1 (A 1, …., A n-1 ). f 2 0 0 1 1 A1A1 A n-2 f n-1 A n A n-1..... Do the same exercise as in previous slide, this will help you get intuition in MV logic.

31. * + + AB (b) PQ * + A B C PRQ * + ABC PRQ 0 1 Kerntopf Gate Feynman Toffoli

32. The Kerntopf gate is described by equations: P = 1 @ A @ B @ C @ AB, Q = 1 @ AB @ B @ C @ BC, R = 1 @ A @ B @ AC. When C=1 then P = A + B, Q = A * B, R = !B, so AND/OR gate is realized on outputs P and Q with C as the controlling input value. When C = 0 then P = !A * ! B, Q = A + !B, R = A @ B. 18 different cofactors! Kerntopf Gate

33. 0110101101 1101011010 Conservative circuit = the same number of ones in inputs and outputs Examples of balanced functions = half of Kmap are ones Variable X3 xor3 Shannon DavioMajorityX2 xor2

34. Generalized Ternary 4*4 Kerntopf Gate f 2 A C Q R B P S 0 1 D *  Do the same exercise as in previous slide, this will help you get intuition in MV logic.

35. MV Quantum Design Structures and Approaches 1. GFSOP 2. Multiple-Valued Reed-Muller 3. Canonical Forms over Galois Logic (equivalents of PPRM, FPRM, GRM, etc) 4. Multiple-Valued Maitra Cascades and Wave Cascades. 5. Other cascades of specific type of elements 6. Cascades of general gates

36. Example 1: First method to realize MV quantum circuits Analogous to binary quantum circuits. As an example, consider two qutrits. When the two qutrits are considered to represent a state, that state is the superposition of all possible combinations of the original qutrits, where: MV Tensor Products This approach to multi-valued quantum circuits requires measurements with more than two basis states. Also, new gates should be defined as well as the synthesis methods for these gates.

37. Quantum MV Superposition The superposition property allows the qubit states to grow much faster in dimension than classical bits, and the qudits faster than qubits. In a classical system, n bits represent distinct states, whereas n qubits correspond to a superposition of 2 n states and n qutrits correspond to a superposition of 3 n states. Because in contemporary quantum technologies every qubit is costly, higher radices than 2 give an advantage of improved processing and storage power at the same realization cost. This is a strong argument for realization of multi-valued logic in quantum circuits. In addition to standard advantages of mv logic, quantum mv logic may be superior to binary one because of different nature of entanglement.

38. Bloch Sphere The normalization |  | 2 + |  | 2 = 1 admits the parametrization  = cos(  /2) e j ,  = sin(  /2) e j . |  = e j  (cos (  / 2) |0  + e j  sin (  / 2) |1  ). Since the global phase of |  has no observable effect, we may write |  = cos(  /2) |0  + e j  sin(  /2) |1 . The angles  and  define a point on the surface of a unit sphere – the Bloch sphere, see Fig. 1. The Bloch sphere provides an excellent tool to visualize the state vector of a qubit. This is a binary Bloch sphere, but a multi-valued counterpart of it can be also created. Example 2: Second Method to realize MV quantum circuits.

39. Second method to realize multi-valued logic using binary quantum computing (cont). Figure shows the location of 6 points, that may correspond to values of some multi- valued algebras. For binary logic we use |0  and |1 . For quaternary logic we use |0 , |1 , |0  +|1 , and |0  -|1 . For 6-valued logic we may use additionally |0  + j |1  and |0  - j|1 . A rotation or a combination of rotations leads from one value to any other value.

40. Second Method to realize MV quantum circuits (cont). Above we showed how multiple-valued logic can be encoded in binary quantum computing. Quaternary logic requires two binary measurements (readings). The first reading distinguishes states |0  and |1 , and the second reading uses additional rotation gates to distinguish between states |0  +|1 , and |0  -|1 . It can be shown that the logic with 2 n values requires n readings.

41. Example 3: Quantum Circuit Simulation Simulation of quantum circuits plays absolutely fundamental role in many areas of quantum physics and engineering. Simulation is used to: –verify correctness of the design, –analyze its properties and –find some interesting aspects that cannot be found by “hand and pencil” methods. –Fault simulation –Evolutionary algorithms Researchers routinely use quantum simulators to help them with inventions and verify their design guesses.

42. Fast simulation is extremely important Matrix methods are slow. Acceleration is attempted to be achieved by two fundamental methods: –(1) acceleration of standard operations by using special hardware emulators, parallel computers or processor networks, – (2) creating new advanced data structures to represent quantum data more efficiently using standard computers.

43. Example 4: Quantum Decision Diagrams New data structures, such as QUIDDs [Viamontes, Markov, Hayes] allow for implicit parallelism when executing Kronecker multiplications on them. QUIDDs are based on ADDs and MTBDDs, so hopefully in future other decision diagrams may be used to represent quantum circuits. It is also expected that basic software engines used successfully in classical CAD (such as for instance SAT or ATPG methods) may be used to deal with quantum circuits. Also, the fast simulators based on new types of decision diagrams should be in future parallelized and possibly accelerated in FPGA-based boards. Even before quantum computers will be available, their emulations on standard computers and ASIC/FPGA may prove useful to solve some practical problems.

44. Example 5 : Testing and diagnosis of quantum circuits Patel, Markov, and Hayes showed that reversible circuits are much better testable than irreversible circuits. –This is because every test covers half faults and every fault is covered by half tests. –The reversible circuits are then “transparent” to faults, making them well observable and controllable. We showed that fault localization in reversible circuits is easier. We presented preliminary results on testing binary quantum circuits and on fault localization of quantum circuits.

45. Notation for Fredkin Gates 01 A 0101 CB PQR A P BC QR A circuit from two multiplexers Its schematics This is a reversible gate, one of many Regular structures, especially for symmetric functions

46. Lattice Structure for Binary Logic 01 A B C 01 0 1 F = S 1,3 (A,B,C) S0S0 S1S1 S2S2 S3S3

47. 01 1010 - - 0 1 1 1 1001 f garbage g 1010 Z fg X garbage gf h i Y 1 garbage hfgfgh YZ X - - X YZ X 11 1 1 00 0 1 X 00 01 11 10 0101

48. What to remember? 1.Synthesis problems in quantum circuits that are related to technology, such as NMR constraints. 2.Linear Nearest Neighbor model 3.Other research issues related to technology of quantum circuit realization 4.A better design of large Toffoli gates 5.Adding SWAP gates to circuits for LNNM model. 6.The concept of binary quantum multiplexer 7.Generalization of Feynman, Toffoli and other binary quantum gates to ternary and multiple-valued quantum gates. 8.Generalized Fredkin and Kerntopf gates. 9.How to recognize balanced functions in Kmaps. Why balanced functions are useful and important? 10.States of MV quantum logic on the Bloch Sphere. 11.Lattice structure from Multiplexers versus Lattice Structure from Fredkin gates – synthesis methods.