1. Week 7.1Spring 2005 14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 7 [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

2. Week 7.2Spring 2005 MIPS arithmetic instructions InstructionExampleMeaningComments add add $1,$2,$3$1 = $2 + $33 operands; exception possible subtractsub $1,$2,$3$1 = $2 – $33 operands; exception possible add immediateaddi $1,$2,100$1 = $2 + 100+ constant; exception possible add unsignedaddu $1,$2,$3$1 = $2 + $33 operands; no exceptions subtract unsignedsubu $1,$2,$3$1 = $2 – $33 operands; no exceptions add imm. unsign.addiu $1,$2,100$1 = $2 + 100+ constant; no exceptions multiply mult $2,$3Hi, Lo = $2 x $364-bit signed product multiply unsignedmultu$2,$3Hi, Lo = $2 x $364-bit unsigned product divide div $2,$3Lo = $2 ÷ $3,Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3Lo = $2 ÷ $3,Unsigned quotient & remainder Hi = $2 mod $3 Move from Himfhi $1$1 = HiUsed to get copy of Hi Move from Lomflo $1$1 = LoUsed to get copy of Lo

3. Week 7.3Spring 2005 ALU VHDL Representation entity ALU is port(A, B: in std_logic_vector (31 downto 0); m: in std_logic_vector (3 downto 0); result: out std_logic_vector (31 downto 0); zero: out std_logic; ovf: out std_logic) end ALU; architecture process_behavior of ALU is... begin ALU: process begin... result := A + B;... end process ALU; end process_behavior;

4. Week 7.4Spring 2005 Number Representation  Bits are just bits (have no inherent meaning) l conventions define the relationships between bits and numbers  Binary numbers (base 2) - integers 0000  0001  0010  0011  0100  0101  0110  0111  1000  1001 ... l in decimal from 0 to 2 n -1 for n bits  Of course, it gets more complicated l storage locations (e.g., register file words) are finite, so have to worry about overflow (i.e., when the number is too big to fit into 32 bits) l have to be able to represent negative numbers, e.g., how do we specify -8 in addi$sp, $sp, -8#$sp = $sp - 8 l in real systems have to provide for more that just integers, e.g., fractions and real numbers (and floating point)

5. Week 7.5Spring 2005  32-bit signed numbers (2’s complement): 0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten 0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten 0000 0000 0000 0000 0000 0000 0000 0010 two = + 2 ten... 0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten 0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0000 two = – 2,147,483,648 ten 1000 0000 0000 0000 0000 0000 0000 0001 two = – 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0010 two = – 2,147,483,646 ten... 1111 1111 1111 1111 1111 1111 1111 1101 two = – 3 ten 1111 1111 1111 1111 1111 1111 1111 1110 two = – 2 ten 1111 1111 1111 1111 1111 1111 1111 1111 two = – 1 ten  What if the bit string represented addresses? l need operations that also deal with only positive (unsigned) integers maxint minint MIPS Representations

6. Week 7.6Spring 2005 Review: Signed Binary Representation 2’s compdecimal 1000-8 1001-7 1010-6 1011-5 1100-4 1101-3 1110-2 1111 00000 00011 00102 00113 01004 01015 01106 01117 2 3 - 1 = 1011 then add a 1 1010 complement all the bits -(2 3 - 1) = -2 3 =

7. Week 7.7Spring 2005  Negating a two's complement number: complement all the bits and add a 1 l remember: “negate” and “invert” are quite different!  Converting n-bit numbers into numbers with more than n bits: l MIPS 16-bit immediate gets converted to 32 bits for arithmetic copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 sign extension versus zero extend ( lb vs. lbu ) Two's Complement Operations

8. Week 7.8Spring 2005 Goal: Design an ALU for the MIPS ISA  Must support the Arithmetic/Logic operations of the ISA  Tradeoffs of cost and speed based on frequency of occurrence, hardware budget

9. Week 7.9Spring 2005 MIPS Arithmetic and Logic Instructions  Signed arithmetic generates overflow, but no carry out R-type: I-Type: 3125201550 opRsRtRdfunct opRsRtImmed 16 Type opfunct ADDI001000xx ADDIU001001xx SLTI001010xx SLTIU001011xx ANDI001100xx ORI001101xx XORI001110xx LUI001111xx Type op funct ADD000000100000 ADDU000000100001 SUB000000100010 SUBU000000100011 AND000000100100 OR000000100101 XOR000000100110 NOR000000100111 Type opfunct 000000101000 000000101001 SLT000000101010 SLTU000000101011 000000101100

10. Week 7.10Spring 2005  Just like in grade school (carry/borrow 1s) 0111 0111 0110 + 0110- 0110- 0101  Two's complement operations easy subtraction using addition of negative numbers 0111  0111 - 0110  + 1010  Overflow (result too large for finite computer word): e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 1000 Addition & Subtraction

11. Week 7.11Spring 2005  Just like in grade school (carry/borrow 1s) 0111 0111 0110 + 0110- 0110- 0101  Two's complement operations easy subtraction using addition of negative numbers 0111  0111 - 0110  + 1010  Overflow (result too large for finite computer word): e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 Addition & Subtraction 1101 0001 0001 0001 1 0001 1000

12. Week 7.12Spring 2005 Building a 1-bit Binary Adder 1 bit Full Adder A B S carry_in carry_out S = A xor B xor carry_in carry_out = A  B v A  carry_in v B  carry_in (majority function)  How can we use it to build a 32-bit adder?  How can we modify it easily to build an adder/subtractor? ABcarry_incarry_outS 00000 00101 01001 01110 10001 10110 11010 11111

13. Week 7.13Spring 2005 Building 32-bit Adder 1-bit FA A0A0 B0B0 S0S0 c 0 =carry_in c1c1 1-bit FA A1A1 B1B1 S1S1 c2c2 A2A2 B2B2 S2S2 c3c3 c 32 =carry_out 1-bit FA A 31 B 31 S 31 c 31...  Just connect the carry-out of the least significant bit FA to the carry-in of the next least significant bit and connect...

14. Week 7.14Spring 2005 Building 32-bit Adder/Subtractor  Remember 2’s complement is just complement all the bits add a 1 in the least significant bit A 0111  0111 B - 0110  + 1010 1-bit FA S0S0 c 0 =carry_in c1c1 1-bit FA S1S1 c2c2 S2S2 c3c3 c 32 =carry_out 1-bit FA S 31 c 31... A0A0 A1A1 A2A2 A 31 B0B0 B1B1 B2B2 B 31 add/subt B0B0 control (0=add,1=subt) B 0 if control = 0, !B 0 if control = 1

15. Week 7.15Spring 2005 Overflow Detection and Effects  Overflow: the result is too large to represent in the number of bits allocated  When adding operands with different signs, overflow cannot occur! Overflow occurs when l adding two positives yields a negative l or, adding two negatives gives a positive l or, subtract a negative from a positive gives a negative l or, subtract a positive from a negative gives a positive  On overflow, an exception (interrupt) occurs l Control jumps to predefined address for exception l Interrupted address (address of instruction causing the overflow) is saved for possible resumption  Don't always want to detect (interrupt on) overflow

16. Week 7.16Spring 2005 Overflow Detection  Overflow: the result is too large to represent in the number of bits allocated  Overflow occurs when l adding two positives yields a negative l or, adding two negatives gives a positive l or, subtract a negative from a positive gives a negative l or, subtract a positive from a negative gives a positive  On your own: Prove you can detect overflow by: l Carry into MSB xor Carry out of MSB 1 1 11 0 1 0 1 1 0 0111 0011+ 7 3 0 1 – 6 1100 1011+ –4 – 5 7 1 0

17. Week 7.17Spring 2005 A Simple ALU Cell 1-bit FA carry_in carry_out A B add/subt result op AND OR XOR NOR B or !B Mux A and B A and !B A or B A or !B A xor B A xor !B A nor B A nor !B A + B A - B

18. Week 7.18Spring 2005 A Simple 32-bit ALU + A1A1 B1B1 result 1 + A0A0 B0B0 result 0 + A 31 B 31 result 31... add/subop Add/ subt Opoperation 0000 1 0001 1 0010 1 0011 1 0100 1 A and B A and !B A or B A or !B A xor B A xor !B A nor B A nor !B A + B A - B

19. Week 7.19Spring 2005  Need to support the set-on-less-than instruction ( slt ) remember: slt is an arithmetic instruction l produces a 1 if rs < rt and 0 otherwise l use subtraction: (a - b) < 0 implies a < b  Need to support test for equality ( beq ) l use subtraction: (a - b) = 0 implies a = b  Need to add the overflow detection hardware Tailoring the ALU to the MIPS ISA

20. Week 7.20Spring 2005 Modifying the ALU Cell for slt 1-bit FA A B result carry_in carry_out add/subtop add/subt less

21. Week 7.21Spring 2005 Modifying the ALU for slt  First perform a subtraction  Make the result 1 if the subtraction yields a negative result  Make the result 0 if the subtraction yields a positive result

22. Week 7.22Spring 2005 Modifying the ALU for slt 0 0 set  First perform a subtraction  Make the result 1 if the subtraction yields a negative result  Make the result 0 if the subtraction yields a positive result tie the most significant sum bit (sign bit) to the low order less input

23. Week 7.23Spring 2005 Modifying the ALU for Zero + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less... 0 0 set  First perform subtraction  Insert additional logic to detect when all result bits are zero add/subt op

24. Week 7.24Spring 2005 Modifying the ALU for Zero + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less... 0 0 set  First perform subtraction  Insert additional logic to detect when all result bits are zero zero... add/subt op Note zero is a 1 when result is all zeros

25. Week 7.25Spring 2005 Review: Overflow Detection  Overflow: the result is too large to represent in the number of bits allocated  Overflow occurs when l adding two positives yields a negative l or, adding two negatives gives a positive l or, subtract a negative from a positive gives a negative l or, subtract a positive from a negative gives a positive  On your own: Prove you can detect overflow by: l Carry into MSB xor Carry out of MSB 1 1 11 0 1 0 1 1 0 0111 0011+ 7 3 0 1 – 6 1100 1011+ –4 – 5 7 1 0

26. Week 7.26Spring 2005 Modifying the ALU for Overflow + A1A1 B1B1 result 1 less + A0A0 B0B0 result 0 less + A 31 B 31 result 31 less... 0 0 set  Modify the most significant cell to determine overflow output setting  Disable overflow bit setting for unsigned arithmetic zero... add/subt op overflow

27. Week 7.27Spring 2005 MULTIPLY (unsigned)  Paper and pencil example (unsigned): Multiplicand 1000 Multiplier 1001 1000 0000 0000 1000 Product 01001000  m bits x n bits = m+n bit product  Binary makes it easy: l 0 => place 0 ( 0 x multiplicand) l 1 => place a copy ( 1 x multiplicand)  4 versions of multiply hardware & algorithm: l successive refinement

28. Week 7.28Spring 2005 Unsigned Combinational Multiplier  Stage i accumulates A * 2 i if B i == 1  Q: How much hardware for 32 bit multiplier? Critical path? B0B0 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000

29. Week 7.29Spring 2005 How does it work?  at each stage shift A left ( x 2)  use next bit of B to determine whether to add in shifted multiplicand  accumulate 2n bit partial product at each stage B0B0 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000 000

30. Week 7.30Spring 2005 Unisigned shift-add multiplier (version 1)  64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Product Multiplier Multiplicand 64-bit ALU Shift Left Shift Right Write Control 32 bits 64 bits Multiplier = datapath + control

31. Week 7.31Spring 2005 Multiply Algorithm Version 1  ProductMultiplierMultiplicand 0000 0000 00110000 0010  0000 001000010000 0100  0000 011000000000 1000  0000 0110 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Multiplicand register left 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to product & place the result in Product register 32nd repetition? Start

32. Week 7.32Spring 2005 Observations on Multiply Version 1  1 clock per cycle => ­ 100 clocks per multiply l Ratio of multiply to add 5:1 to 100:1  1/2 bits in multiplicand always 0 => 64-bit adder is wasted  0’s inserted in left of multiplicand as shifted => least significant bits of product never changed once formed  Instead of shifting multiplicand to left, shift product to right?

33. Week 7.33Spring 2005 MULTIPLY HARDWARE Version 2  32-bit Multiplicand reg, 32 -bit ALU, 64- bit Product reg, 32-bit Multiplier reg Product Multiplier Multiplican d 32-bit ALU Shift Right Write Control 32 bits 64 bits Shift Right

34. Week 7.34Spring 2005 Multiply Algorithm Version 2 MultiplierMultiplicandProduct 001100100000 0000 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start °ProductMultiplierMultiplicand 0000 0000 00110010

35. Week 7.35Spring 2005 What’s going on?  Multiplicand stay’s still and product moves right B0B0 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3

36. Week 7.36Spring 2005 Multiply Algorithm Version 2 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start  ProductMultiplierMultiplicand 0000 0000 00110010  0010 0000  0001 000000010010  0011 0000010010  0001 100000000010  0000 110000000010  0000 011000000010

37. Week 7.37Spring 2005 Observations on Multiply Version 2  Product register wastes space that exactly matches size of multiplier => combine Multiplier register and Product register

38. Week 7.38Spring 2005 MULTIPLY HARDWARE Version 3  32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Product (Multiplier) Multiplican d 32-bit ALU Write Control 32 bits 64 bits Shift Right

39. Week 7.39Spring 2005 Multiply Algorithm Version 3 MultiplicandProduct 00100000 0011 Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Product0 Product0 = 0 Product0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start

40. Week 7.40Spring 2005 Observations on Multiply Version 3  2 steps per bit because Multiplier & Product combined  MIPS registers Hi and Lo are left and right half of Product  Gives us MIPS instruction MultU  How can you make it faster?  What about signed multiplication? l easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps) l apply definition of 2’s complement -need to sign-extend partial products and subtract at the end l Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles -can handle multiple bits at a time

41. Week 7.41Spring 2005 Motivation for Booth’s Algorithm  Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000shift (0 in multiplier) + 0010 add (1 in multiplier) + 0100 add (1 in multiplier) +0000 shift (0 in multiplier) 00001100  ALU with add or subtract gets same result in more than one way: 6= – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000  For example  0010 x 0110 0000 shift (0 in multiplier) – 0010 sub (first 1 in multpl.). 0000 shift (mid string of 1s). +0010 add (prior step had last 1) 00001100

42. Week 7.42Spring 2005 Booth’s Algorithm Current BitBit to the RightExplanationExampleOp 10Begins run of 1s0001111000sub 11Middle of run of 1s0001111000none 01End of run of 1s0001111000add 00Middle of run of 0s0001111000none Originally for Speed (when shift was faster than add)  Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one –1 + 10000 01111

43. Week 7.43Spring 2005 Booths Example (2 x 7) 1a. P = P - m1110 +1110 1110 0111 0shift P (sign ext) 1b. 00101111 0011 111 -> nop, shift 2.00101111 1001 111 -> nop, shift 3.00101111 1100 101 -> add 4a.0010 +0010 0001 1100 1shift 4b.00100000 1110 0done OperationMultiplicandProductnext? 0. initial value00100000 0111 010 -> sub

44. Week 7.44Spring 2005 Booths Example (2 x -3) 1a. P = P - m1110 +1110 1110 1101 0shift P (sign ext) 1b. 00101111 0110 101 -> add + 0010 2a.0001 0110 1shift P 2b.00100000 1011 010 -> sub +1110 3a.00101110 1011 0shift 3b.0010 1111 0101 111 -> nop 4a1111 0101 1 shift 4b.00101111 1010 1 done OperationMultiplicandProductnext? 0. initial value00100000 1101 010 -> sub

45. Week 7.45Spring 2005 MIPS logical instructions InstructionExampleMeaningComment and and $1,$2,$3$1 = $2 & $33 reg. operands; Logical AND or or $1,$2,$3$1 = $2 | $33 reg. operands; Logical OR xor xor $1,$2,$3$1 = $2  $33 reg. operands; Logical XOR nor nor $1,$2,$3$1 = ~($2 |$3)3 reg. operands; Logical NOR and immediate andi $1,$2,10$1 = $2 & 10Logical AND reg, constant or immediate ori $1,$2,10$1 = $2 | 10Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10Logical XOR reg, constant shift left logical sll $1,$2,10$1 = $2 << 10Shift left by constant shift right logical srl $1,$2,10$1 = $2 >> 10Shift right by constant shift right arithm. sra $1,$2,10$1 = $2 >> 10Shift right (sign extend) shift left logical sllv $1,$2,$3$1 = $2 << $3 Shift left by variable shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

46. Week 7.46Spring 2005 Shifters Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend msblsb"0" msblsb"0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

47. Week 7.47Spring 2005 Combinational Shifter from MUXes  What comes in the MSBs?  How many levels for 32-bit shifter?  What if we use 4-1 Muxes ? 1 0 sel A B D Basic Building Block 8-bit right shifter 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 S 2 S 1 S 0 A0A0 A1A1 A2A2 A3A3 A4A4 A5A5 A6A6 A7A7 R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7

48. Week 7.48Spring 2005 General Shift Right Scheme using 16 bit example S 0 (0,1) S 1 (0, 2) If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs) S 3 (0, 8) S 2 (0, 4)

49. Week 7.49Spring 2005 Funnel Shifter XY R  Shift A by i bits (sa= shift right amount)  Logical: Y = 0, X=A, sa=i  Arithmetic? Y = _, X=_, sa=_  Rotate? Y = _, X=_, sa=_  Left shifts? Y = _, X=_, sa=_ Instead Extract 32 bits of 64. Shift Right 32 Y X R

50. Week 7.50Spring 2005 Barrel Shifter Technology-dependent solutions: transistor per switch D3 D2 D1 D0 A6 A5 A4 A3A2A1A0 SR0SR1SR2SR3

51. Week 7.51Spring 2005 Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend –1000 10 101 1010 –1000 10 Remainder (or Modulo result) See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or 0 * divisor Dividend = Quotient x Divisor + Remainder => | Dividend | = | Quotient | + | Divisor | 3 versions of divide, successive refinement

52. Week 7.52Spring 2005 DIVIDE HARDWARE Version 1  64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Remainder Quotient Divisor 64-bit ALU Shift Right Shift Left Write Control 32 bits 64 bits

53. Week 7.53Spring 2005 2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. Divide Algorithm Version 1  Takes n+1 steps for n-bit Quotient & Rem. Remainder QuotientDivisor 0000 0111 00000010 0000 Test Remainder Remainder < 0 Remainder  0 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. 2a. Shift the Quotient register to the left setting the new rightmost bit to 1. 3. Shift the Divisor register right1 bit. Done Yes: n+1 repetitions (n = 4 here) Start: Place Dividend in Remainder n+1 repetition? No: < n+1 repetitions

54. Week 7.54Spring 2005 Observations on Divide Version 1  1/2 bits in divisor always 0 => 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted  Instead of shifting divisor to right, shift remainder to left?  1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration

55. Week 7.55Spring 2005 DIVIDE HARDWARE Version 2  32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Remainder Quotient Divisor 32-bit ALU Shift Left Write Control 32 bits 64 bits Shift Left

56. Week 7.56Spring 2005 Divide Algorithm Version 2 RemainderQuotient Divisor 0000 011100000010 3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. Test Remainder Remainder < 0 Remainder  0 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3a. Shift the Quotient register to the left setting the new rightmost bit to 1. 1. Shift the Remainder register left 1 bit. Done Yes: n repetitions (n = 4 here) nth repetition? No: < n repetitions Start: Place Dividend in Remainder

57. Week 7.57Spring 2005 Observations on Divide Version 2  Eliminate Quotient register by combining with Remainder as shifted left l Start by shifting the Remainder left as before. l Thereafter loop contains only two steps because the shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half l The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many. l Thus the final correction step must shift back only the remainder in the left half of the register

58. Week 7.58Spring 2005 DIVIDE HARDWARE Version 3  32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg) Remainder (Quotient) Divisor 32-bit ALU Write Control 32 bits 64 bits Shift Left “HI”“LO”

59. Week 7.59Spring 2005 Divide Algorithm Version 3 Remainder Divisor 0000 01110010 3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0. Test Remainder Remainder < 0 Remainder  0 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3a. Shift the Remainder register to the left setting the new rightmost bit to 1. 1. Shift the Remainder register left 1 bit. Done. Shift left half of Remainder right 1 bit. Yes: n repetitions (n = 4 here) nth repetition? No: < n repetitions Start: Place Dividend in Remainder

60. Week 7.60Spring 2005 Observations on Divide Version 3  Same Hardware as Multiply: just need ALU to add or subtract, and 63-bit register to shift left or shift right  Hi and Lo registers in MIPS combine to act as 64-bit register for multiply and divide  Signed Divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary l Note: Dividend and Remainder must have same sign l Note: Quotient negated if Divisor sign & Dividend sign disagree e.g., –7 ÷ 2 = –3, remainder = –1  Possible for quotient to be too large: if divide 64-bit interger by 1, quotient is 64 bits (“called saturation”)