1. 12/10/2004EE 42 fall 2004 lecture 421 Lecture #42: Transistors, digital This week we will be reviewing the material learned during the course Today: review –CMOS transistors –Digital logic

2. 12/10/2004EE 42 fall 2004 lecture 422 Review Session When: Thursday, Dec. 16th; 3-6pm Where: Evans 0009 Format: Open, bring questions

3. 12/10/2004EE 42 fall 2004 lecture 423 Final Exam Date/Time: SATURDAY, DECEMBER 18, 2004 5-8PM Location: 150 GSPP (Goldman School of Public Policy) Format: Closed book One page, (two sides) of notes

4. 12/10/2004EE 42 fall 2004 lecture 424 n P oxide insulator n drain - + source gate MOS transistor Below threshold V GS < V t Below threshold, there are no electrons under the gate oxide, and the holes in the substrate are blocked from carrying current by reverse biased diode junctions

5. 12/10/2004EE 42 fall 2004 lecture 425 n P oxide insulator n drain - + source gate NMOS in the linear (Triode) region V GS > V t If the gate voltage is above threshold, but the source to drain voltage is small, the charge under the gate is uniform, and carries current much like a resistor The electrons move under the influence of the Electric field at a velocity: ν=μE where E=volts/distance And they must travel a distance L to cross the gate Since the total charge is Q=CV gs, we will have a current I d =μC gate V ds (V gs -V th )/L 2 = μ(ε ox /d ox )V ds (V gs -V th )W/L

6. 12/10/2004EE 42 fall 2004 lecture 426 n P oxide insulator n drain - + source gate NMOS with increasing V ds V GS > V t As the voltage from the source to the drain is increased, the current increases, but not by as much because the charge is attracted out from under the oxide, beginning to pinch off the channel

7. 12/10/2004EE 42 fall 2004 lecture 427 Saturation As the Source-Drain voltage is increased, there will be a significant change in the charge at different distances along the gate When the voltage across the device at the drain end goes below threshold, the current is pinched off. If there is no current out the drain end, however, the current due to the carriers which are available from the source cause the voltage to be closer to that of the source. These two effects cause a small region to form near the drain which limits the current. This is called saturation

8. 12/10/2004EE 42 fall 2004 lecture 428 A little more MOS “Theory” We have two regions: the resistive region at smaller V DS and the saturation region at higher V DS. IDID V DS V GS In the resistive region we start out like a simple resistor between source and drain (whose value depends on gate voltage) and gradually the curve “bends over” as we approach saturation In the saturation we have a small gradual increase of I with V DS V GS S G V DS iDiD +  +-+- D

9. 12/10/2004EE 42 fall 2004 lecture 429 Basic CMOS Inverter Inverter IN OUT V DD p-ch V DD OUT IN n-ch CMOS Inverter Example layout of CMOS Inverter

10. 12/10/2004EE 42 fall 2004 lecture 4210 GROUND IN OUT V DD N-WELL NMOS Gate PMOS Gate Al “wires”

11. 12/10/2004EE 42 fall 2004 lecture 4211 n-type metal oxide insulator metal p-type metal gate source drain n-type - + V GS - + V DS IDID IGIG G D S IDID IGIG - V DS + + V GS _ NMOS Transistor

12. 12/10/2004EE 42 fall 2004 lecture 4212 G D S IDID IGIG - V DS + + V GS _ NMOS I-V Characteristic Since the transistor is a 3-terminal device, there is no single I-V characteristic. Note that because of the insulator, I G = 0 A. We typically define the MOS I-V characteristic as I D vs. V DS for a fixed V GS. The I-V characteristic changes as V GS changes.

13. 12/10/2004EE 42 fall 2004 lecture 4213 triode mode cutoff mode (when V GS < V TH(N) ) saturation mode V DS IDID V GS = 3 V V GS = 2 V V GS = 1 V V DS = V GS - V TH(n) NMOS I-V Curves

14. 12/10/2004EE 42 fall 2004 lecture 4214 Saturation in a MOS transistor At low Source to drain voltages, a MOS transistor looks like a resistor which is “turned on” by the gate voltage If a more voltage is applied to the drain to pull more current through, the amount of current which flows stops increasing→ an effect called pinch-off. Think of water being sucked through a flexible wall tube. Dropping the pressure at the end in order to try to get more water to come through just collapses the tube. The current flow then just depends on the flow at the input: VGS This is often the desired operating range for a MOS transistor (in a linear circuit), as it gives a current source at the drain as a function of the voltage from the gate to the source.

15. 12/10/2004EE 42 fall 2004 lecture 4215 NAND gate AB A B Making a NAND gate: (NMOS pulls “down”, PMOS “up”) NMOS portion: both inputs need to be high for output to be low  series CMOS DIGITAL LOGIC 0 0 0 1 0 1 1 0 0 1 1 1 1 0 PMOS portion: either input can be low for output to be high  parallel C= B C A V DD

16. 12/10/2004EE 42 fall 2004 lecture 4216 These are circuits that accomplish a given logic function such as “OR”. We will shortly see how such circuits are constructed. Each of the basic logic gates has a unique symbol, and there are several additional logic gates that are regarded as important enough to have their own symbol. The set is: AND, OR, NOT, NAND, NOR, and EXCLUSIVE OR. Logic Gates A B C=A·B AND C = A B NAND C = NOR A B NOT A OR A B C=A+B EXCLUSIVE OR A B

17. 12/10/2004EE 42 fall 2004 lecture 4217 Transistor Inverter Example It may be simpler to just think of PMOS and NMOS transistors instead of a general 3 terminal pull-up or pull-down devices or networks. V IN-D Pull-Down Network V OUT I OUT Output V DD Pull-Up Network V IN-U V IN-D V IN-U V OUT I OUT Output V DD p-type MOS Transistor (PMOS) n-type MOS Transistor (NMOS)

18. 12/10/2004EE 42 fall 2004 lecture 4218 Complementary Networks If inputs A and B are connected to parallel NMOS, A and B must be connected to series PMOS. The reverse is also true. Determining the logic function from CMOS circuit is not hard: –Look at the NMOS half. It will tell you when the output is logic zero. –Parallel transistors: “like or” –Series transistors: “like and”

19. 12/10/2004EE 42 fall 2004 lecture 4219 Some Useful Theorems 1) 2) 3) 4) 5) 6) 7) 8) 9) } de Morgan’s Laws Each of these can be proved by writing out truth tables Communicative Associative Distributive Defined from truth tables

20. 12/10/2004EE 42 fall 2004 lecture 4220 Evaluation of Logical Expressions with “Truth Tables” The Truth Table completely describes a logic expression In fact, we will use the Truth Table as the fundamental meaning of a logic expression. Two logic expressions are equal if their truth tables are the same A truth table can be turned into a sum-of-products by writing each row which results in a “1” output as an “and” (the product), and then ORing them together (the sum)

21. 12/10/2004EE 42 fall 2004 lecture 4221 Going from a Boolean expression to gates Simply expand the Boolean expression into a SUM-OF-PRODUCTS expression: Y = ABC+DEF Then rewrite it by “inverting” with De Morgan: NAND GATE SYNTHESIS. Using De Morgan’s theorem we can turn any Boolean expression into NAND gates. The NAND realization, while based on DeMorgan’s theorem, is in fact much simpler: just look at the sum of products expression and use one NAND for each term and one to combine the terms. A B Y C D E F Clearly this expression is realized with three NAND gates: one three-input NAND for, one for, and one two-input gate to combine them:

22. 12/10/2004EE 42 fall 2004 lecture 4222 Synthesis Designing the combinatorial logic circuit, con’t Two Examples of SUM-OF-PRODUCTS expressions: Method 3: NAND GATE SYNTHESIS (CONTINUED). (X-OR function) A X B (No connection) A Y B C We could make the drawings simpler by just using a circle for the NOT function rather than showing a one- input NAND gate

23. 12/10/2004EE 42 fall 2004 lecture 4223 NMOS switches in series from output to ground; PMOS switches in parallel from output to the supply (Here we left out the A-A and B-B connection for clarity) CMOS NAND GATE v A v B v OUT V DD v A v B Behaves like 2 R n ’s in series when both A and B are high NAND: If either output is low then one of the bottom (pull down) series switches is open and one of the upper (pull up) switches are closed. Thus the output is pulled high.

24. 12/10/2004EE 42 fall 2004 lecture 4224 NAND Gate Pull-Up Model* v OUT V DD v A v B v A v B   = RC = R p C One or both switches closed (worse case: one switch) Output is loaded by the gate capacitance of the next stage: C= C Gn +C Gp

25. 12/10/2004EE 42 fall 2004 lecture 4225 B F A V DD C F A B NAND Gates with more inputs 2-input NAND Each input loads with C GN +C GP Output drives with 2R DN or R DP 3-input NAND Each input loads with C GN +C GP Output drives with 3R DN or R DP

26. 12/10/2004EE 42 fall 2004 lecture 4226 NOR function (two inputs) AB A +BC=A +B Output is low if either input is high  NMOS switches (between ground and the output) in parallel CMOS NOR GATE 0 0 0 1 0 1 1 0 1 0 1 1 1 0 BA Output is high only if both inputs are low  PMOS switches (between the supply and the output) in series V DD A B C

27. 12/10/2004EE 42 fall 2004 lecture 4227 “Complementary” configuration to the NAND gate CMOS NOR GATE v OUT V DD v A v B v OUT V DD v A v B NORNAND

28. 12/10/2004EE 42 fall 2004 lecture 4228 Definition of Fanout Fanout = number of gates that are connected to the driver Fanout leads to increased capacitive load (and higher delay)

29. 12/10/2004EE 42 fall 2004 lecture 4229 Clocked logic If we put two latches into every feedback path, and make sure both latches are never open at the same time, we can insure predicable results. ABCABC Outputs

30. 12/10/2004EE 42 fall 2004 lecture 4230 Edge trigger If we use an edge trigger, then a single phase clock can be used. An edge triggered flip flop will only change at a rising or falling edge of the clock, so that the new state will not feedback to its own value ABCABC Outputs

31. 12/10/2004EE 42 fall 2004 lecture 4231 Sequential logic The timing rules for sequential logic can be summarized: Only one transition of the latches are allowed per clock cycle, the change from one clock is not allowed to circulate back through the logic to effect itself. The clock speed will be limited by the slowest path The fastest path must not be allowed to change the state before changes have been latched out