1. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science Emery Berger University of Massachusetts, Amherst Operating Systems CMPSCI 377 Lecture 12: Paging

2. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 2 Last Time Memory Management Uniprogramming vs. Multiprogramming Segments Memory allocation First-fit, best-fit, worst-fit... Compaction Relocation

3. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 3 Today: Paging Motivation Fragmentation Page Tables Hardware Support Other Benefits

4. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 4 Segmentation, Revisited As processes enter system, grow & terminate, OS must track available and in-use memory Can leave holes OS must decide where to put new processes

5. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 5 Motivation: Problems with Segments Processes don’t (usually) use entire space in memory all the time Fragmentation problematic Internal & external Compaction expensive

6. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 6 Alternative: Paging Divide memory into fixed- sized pages (4K, 8K) Allocates pages to frames in memory OS manages pages Moves, removes, reallocates Pages copied to and from disk A

7. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 7 Example: Page Layout How does this help?

8. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 8 Paging Advantages Most programs obey 90/10 “rule” 90% of time spent accessing 10% of memory Exploiting this rule: Only keep “live” parts of process in memory A B A B

9. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 9 Paging Advantages “Hole-fitting problem” vanishes! Logical memory contiguous Physical memory not required to be Eliminates external fragmentation But not internal (why not?) But: Complicates address lookup...

10. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 10 Example: Page Layout So how do we resolve addresses?

11. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 11 Today: Paging Motivation Fragmentation Page Tables Hardware Support Other Benefits

12. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 12 Paging Hardware Processes use virtual addresses Addresses start at 0 or other known address OS lays process down on pages MMU (memory-management unit): Hardware support for paging Translates virtual to physical addresses Uses page table to keep track of frame assigned to memory page

13. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 13 Paging Hardware: Diagram

14. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 14 Paging Hardware: Intuition Paging: form of dynamic relocation Virtual address bound by paging hardware to physical address Page table ¼ set of relocation registers One per frame Mapping – invisible to process OS maintains mapping H/W does translation Protection – provided by same mechanisms as in dynamic relocation

15. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 15 Paging Hardware: Nitty-Gritty Page size (= frame size): Typically power of 2 between 512 & 8192 bytes Linux, Windows: 4K; Solaris: 8K Support for larger page sizes varies (e.g., 128K) Use of powers of 2 simplifies translation of virtual to physical addresses

16. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 16 Address Translation Powers of 2: Virtual address space: size 2 m Page size 2 n High-order m-n bits of virtual address select page Low order n bits select offset in page

17. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 17 Address Translation: Example How big is page table? How many bits per address? (assume 1 byte addressing) What part is p, d? Given virtual address 24, do virtual to physical translation

18. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 18 Address Translation: Example How many bits per address? (assume 4 byte addressing) What part is p, d? Given virtual address 13, do virtual to physical translation

19. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 19 Making Paging Efficient Where should the page table go? Registers: Pros? Cons? Memory: Pros? Cons?

20. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 20 Translation Lookaside Buffer (TLB) TLB: fast, fully associative memory Stores page numbers (key) and frame (value) in which they are stored Assumption: locality of reference Locality in memory accesses ) locality in address translation TLB sizes: 8 to 2048 entries

21. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 21 TLB: Diagram v = valid bit: entry is up-to-date

22. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 22 Cost of Using TLB Measure in terms of memory access cost What is cost if: Page table is in memory? Page table managed with TLB? Large TLB: Improves hit ratio Decreases average memory cost

23. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 23 Managing the TLB: Process Initialization & Execution Process arrives, needs k pages If k page frames free, allocate; else free frames that are no longer needed OS: puts pages in frames puts frame numbers into page table marks all TLB entries as invalid (flush) starts process loads TLB entries as pages are accessed, replaces entries when full

24. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 24 Managing the TLB: Context Switches Extend Process Control Block (PCB) with: Page table Copy of TLB (optional) Context switch: Copy page table base register value to PCB Copy TLB to PCB (optional) Flush TLB Restore page table base register Restore TLB (optional) Use multilevel paging if tables too big

25. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 25 Today: Paging Motivation Fragmentation Page Tables Hardware Support Other Benefits

26. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 26 Sharing Paging allows sharing of memory across processes Shared pages –different virtual addresses, point to same physical address Compiler marks “text” segment (i.e., code) of applications (e.g., emacs) - read-only OS: keeps track of such segments Reuses if another instance of app arrives Can greatly reduce memory requirements

27. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 27 Summary: Paging Advantages Paging: big improvement over segmentation Eliminates external fragmentation (thus avoiding need for compaction) Allows sharing of code pages across processes Reduces memory demands Enables processes to run when only partially loaded in main memory

28. U NIVERSITY OF M ASSACHUSETTS, A MHERST Department of Computer Science 28 Summary: Paging Disadvantages Paging: some costs Translating from virtual addresses to physical addresses efficiently requires hardware support Larger TLB ) more efficient, but more expensive More complex operating system required to maintain page table More expensive context switches Why?