1. 1 Industrial applications of ionizing radiation sources (Destructive Single Event Effects) Andrea Candelori Istituto Nazionale di Fisica Nucleare and Dipartimento di Fisica, Padova

2. 2 Material for study 1) F. W. Sexton, “Destructive Single-Event Effects in Semiconductor Devices and ICs", IEEE Trans. Nucl. Sci., vol 50, n.3, June 2003, pp. 603-621, and references therein.

3. 3 Single event effects (SEE) Definition: “Single event effects (SEE) are individual events which occur when a single incident ionising particle deposits in a sensitive volume of the device enough energy in form of ionization to cause an effect in a device”. Single event effects (SEE) can be: -destructive events:Single Event Burnout (SEB) in power MOSFET Single Event Gate Rupture (SEGR) power MOSFET Single Event Snapback (SES) in MOSFET Single Event Latch-up (SEL) in CMOS technologies -non destructive events:Single Event Upset (SEU) Single Event Drain Current Collapse (SEDC 2 ) Single Event Transient (SET) Single Event Disturb (SED) Single Event Functional Interrupt (SEFI)

4. 4 Ionization track: reminder An energetic ionizing particle going through a semiconductor material creates a track of ionization with a radius typically less than 1  m (i.e., higher than the minimum channel length of the current CMOS technologies) and within which the carrier density decreases from the center. 0.1  m

5. 5 Ion shunt effect Illustration of the ion shunt effect: the high charge density along a track can connect devices junctions.

6. 6 Charge funneling: reminder Microscopic mechanism If an ion track traverses a reversed biased p-n junction the density of ionization can be so high that the resulting current flow collapses the field across the junction and the collection charge from the track reaches father into the semiconductor than the original depletion region. Definition Charge funneling is the extension of the charge collection from an ionization track to a region beyond the original depletion depth: The charge funneling effect.

7. 7 Single Event Effects (SEE) cross section: reminder The cross section (  ) for Single Event Effects is:  =N SEE /  N SEE : Number of SEE observed  : Particle fluence A typical measured and ideal SEE cross section curve. WEIBUL FIT  =  sat  {1-exp[-(L-L th )/W] S }  sat : saturation value of the cross section L th : threshold value for LET W and s are fitting parameter

8. 8 Bipolar Junction Transistor (BJT): reminder P N+N+ N C E B P+P+ P N C E B PNP typeNPN type Condition base-emitter junctionbase-collector junction Cut-offreverse biasedreverse biased Active region (BE inverse)reverse biasedforward biased Active region (BE direct)forward biased reverse biased Saturationforward biased forward biased Equations in active regionEquations in saturation I C = I B  I C,max = I B, max  I C is the collector current, I B is the base current,  >>1 is the gain. I E = I B + I C

9. 9 Power MOSFET -Power MOSFETs are power devices capable of conducting large currents when turned in the ON state and withstanding large voltage when turned in the OFF state. -Current flow between the n-drain (substrate) and the n + -source in power n-MOSFET is turned ON and turned OFF for positive values of the drain-to-source voltage V DS by modulating the surface conductivity under the poly gate which is controlled by the gate-to-source voltage (V GS ) -The n + -source and the p-body contacts are short-circuited. Cross section of a typical n-channel power MOSFET Current flow in a n-channel power MOSFET

10. 10 Power n-MOSFET operation Cross section of a n-channel power MOSFET -V GS <0 V: the n-epi surface region at the SiO 2 /Si interface becomes depleted and then approach to strong inversion. The channel region (p-body surface region along the Si/SiO 2 interface) approach strong accumulation. The power n-MOSFET is turned OFF and no current flows. -V GS >0 V: the n-epi surface region at the SiO 2 /Si interface approaches strong accumulation. The channel region (p-body surface region along the Si/SiO 2 interface) becomes depleted and approach strong inversion, forming a n-type channel along the SiO 2 /Si surface that couples the drain (substrate) with the source. The power n-MOSFET turned ON and current flows. -The threshold voltage (V TH ) is the minimum gate source voltage (V GS ) to turn on the n- type channel at the SiO 2 /Si interface. Current flow in a n-channel power MOSFET

11. 11 Power MOSFET Advantages: -fast switching time; -high current capability; -low on resistance; -low gate current. Applications: -on-board space system; -battery charge assemblies; -power supply electronics; -power conditioning systems; -momentum wheels and controllers.

12. 12 Cross-section for parallel connections of n-channel power MOSFETs. Cross section of a n-channel power MOSFET Power MOSFET Power MOSFETs: large current capabilities are achieved by the parallel connection of thousands of smaller units cells.

13. 13 Power n-MOSFET: parasitic BJT (1) The parasitic npn Bipolar Junction Transistor (BJT) inherent to a power n-MOSFET. P N N+N+ C E B NPN type N+N+ N p IEIE ICIC IBIB V CE V BE

14. 14 Power n-MOSFET: Single Event Burnout (SEB) and BJT (2) -A single high-energy heavy ion is capable of destroying a power n-MOSFET. -the ion going through the voltage supporting layer of the device generates high density of electron-hole pairs along its track, which can induce high current density up to 10 4 A/cm 2 in presence of large drain-to-source voltages. -for V DS >0 (V BS =0 and V GS ≤0 can be varied) the hole current density flowing from the n-epi substrate (collector) through the p-body region (base) below the lateral channel region may cause a voltage drop exceeding 0.7 V for the base-emitter p-n junction, turning on the parasitic bipolar junction transistor (emitter=n-source, base=p-body, collector=n-epi layer) that is an inherent part of the power MOSFET, locally increasing the plasma current several order of magnitude. -the resulting very localized power density may be large enough to produce incandescent temperatures, which are able to lead the device burn-out. P N N+N+ C E B NPN type N+N+ N p IEIE ICIC IBIB V CE V BE D I D I D I

15. 15 Power n-MOSFET: Single Event Burnout (SEB) and epi-layer (3) The electric field intensity in the lightly doped n-epi region was the main contribution to SEB sensitivity in power n-MOSFET (V DS >0, V BS =0 and varying V GS  0): -a heavy ion strike close to the n-source (emitter) region generate a dense plasma of electrons and holes along the track of the ion strike. -electrons flow to the n-drain (collector) region while holes are swept to the p-body (base) diffusion. -As excess holes move through the p-body spreading resistance to the ground contact, a voltage drop develops that forward biases the parasitic base (p-body)-emitter (n-source) junction. -Forward biasing leads to further electron injection into the lightly doped n-epi region, which, under high field condition, then generates additional holes through avalanche multiplication. Current in the n-epi layer increases regeneratively until the device enters second breakdown and thermal runway. D I

16. 16 Power n-MOSFET: Single Event Burnout (SEB) and review 2-3 Electrons flow to the n-drain (collector) region Holes are swept to the p-body (base) diffusion As excess holes move through the p-body spreading resistance to the ground contact, a voltage drop develops that forward biases the parasitic base (p-body)-emitter (n-source) junction. Forward biasing leads to further electron injection into the lightly doped n-epi region, which, under high field condition, then generates additional holes through avalanche multiplication. Current in the n-epi layer increases regeneratively until the device enters second breakdown and thermal runway. Right side

17. 17 Photograph of a power MOSFET after SEB. Power MOSFET: Single Event Burnout (SEB)

18. 18 Power MOSFET: Single Event Burnout (SEB) [opzionale] Experimental set-up for SEB cross section measurements SEB cross section measurements are independent on I DS and V GS for a fixed V DS and V BS =0 SEB cross section measurements are independent on the load resistance Non destructive Destructive

19. 19 Power MOSFET: Single Event Burnout (SEB) [opzionale] SEB cross section data for the n-power MOSFET "2N6766" (drain-source breakdown voltage BV DSS =200 V) at V DS =200V and V GS =V BS =0V during irradiation What can be deduced by this plot?.............................

20. 20 Power MOSFET: Single Event Burnout (SEB) [opzionale] SEB cross section data for the n-power MOSFET "2N6766" (drain-source breakdown voltage BV DSS =200 V) at increasing V DS and V GS =V BS =0V during irradiation I, E=90 MeV LET=30-40 MeV·cm 2 /mg Range 15  m Cu, E=200 MeV LET=28 MeV·cm 2 /mg Range 40  m Cl, E=90 MeV LET=16 MeV·cm 2 /mg Range 25  m What can be deduced by this plot?.............................

21. 21 Power MOSFET: Single Event Burnout (SEB) [opzionale] I, E=90 MeV LET=30-40 MeV·cm 2 /mg Range 15  m Cu, E=200 MeV LET=28 MeV·cm 2 /mg Range 40  m Cl, E=90 MeV LET=16 MeV·cm 2 /mg Range 25  m What can be deduced by this plot?............................. SEB cross section data for the n-power MOSFET “IRF 130" (drain-source breakdown voltage BV DSS =100 V) at increasing V DS and V GS =V BS =0V during irradiation

22. 22 Power MOSFET: Single Event Burnout (SEB) Factors increasing SEB: -gain of the parasitic npn transistor; -spreading resistance in the base region; -avalanche multiplication in the drain region; -increase of the epitaxial layer thickness and decrease of the doping level (in presence of high electron-hole densities, the peak of the electric field can easily shift from the base-collector junction to the epi-substrate transition region); Power MOSFET can be hardened to SEB by reducing the distance from the p + plug to the body region.

23. 23 Power MOSFET: Single Event Burnout (SEB) and epi-layer (4) Increase of the epitaxial layer thickness and decrease of the doping level (in presence of high electron-hole densities, the peak of the electric field can easily shift from the base-collector junction to the epi-substrate transition region) increase the SEB sensitivity. -Power n-channel MOSFET failed at V DS equal to 20-90% of the rated breakdown voltage of the device (current induced avalanche in the epitaxial region). -Power p-channel MOSFET did not experience SEB up to their rated breakdown voltage. Current Induced Avalanche (CIA), due to electrons, in the epitaxial layer. Power n-MOSFET (left) and test structure (right) for studies on the Current Induced Avalanche (CIA), due to electrons, in the epitaxial layer.

24. 24 Power MOSFET: Single Event Burnout (SEB) (f) -In presence of high electron-hole densities, the peak of the electric field can easily shift from the base-collector junction to the epi-substrate transition region. Then by increasing the electron-hole densities the value of the electric field increases. -This effects in enhanced by increasing of the epitaxial layer thickness and by decreasing the doping level increase, taking into account that an ion generates high electron-hole density along its tracks whose densities can be higher than the doping levels. -High electric fields can induced Current Induced Avalanche (CIA), due to electrons, in the epitaxial layer increasing the elecrton-hole densities and the electric field. Electric field in the npn structure as a function of the current density

25. 25 Power MOSFET: Single Event Burnout (SEB) SEB depends on the charge distribution along the ion track and not just on the surface LET of the ion: the charge generation at least as deep as the epi-substrate junction contributes to SEB: -higher energy ions (higher range) have a lower threshold to SEB than low energy ion (lower range) with similar LET; -there is lower charge recombination at higher ion energies, due to the larger track diameter. Br 150 MeV Br 285 MeV Depth

26. 26 Power MOSFET: Single Event Burnout (SEB) For V DS values at 50% of the rate breakdown voltage, with V GS =0V and V BS =0V SEB occurs primarily for ion impacts in the channel region close to the p-base region Ion impact point

27. 27 Power MOSFET: Single Event Burnout (SEB) Drain current after ion impact Charge collected at the drain node after the ion impact: 1) first peak charge collection at the drain depletion region; 2) increasing LET or V DS a second peak appears: transistor action in the base-emitter junction of the vertical parasitic BJT. Both peaks moves gradually to higher charges by increasing LET or V DS ; 3) when SEB occurs a high charge peak appears corresponding to the runway avalanche current condition. The threshold charge Q TH depends on technology not on the operating conditions.

28. 28 Power MOSFET: Single Event Burnout (SEB) -Studies of SEB in power MOSFET by using techniques for preventing SEB, by limiting the current with a series resistor and removing the power within 1  s of detection of high current condition. Experimental set-up

29. 29 Power MOSFET: Single Event Burnout (SEB) -The SEB sensitivity decreases by increasing temperature because the impact ionization rate decreases by increasing temperature. -Difference between static and dynamic operation: the saturation cross section in dynamic mode can be 2 orders of magnitude lower than in static mode. -By tilting the sample, the 1/cos  dependence for LET can not be applied -By increasing the incidence angle the SEB sensitivity decreases. -SEB can be induced also by protons and neutrons. Note:

30. 30 Power MOSFET: Single Event Gate Rupture (SEGR) -Following an heavy ion strike in the center of the channel region of a power n-MOSFET, the dense plasma of electrons and holes along the ion track separate under the influence of the drain bias (V DS >0 and V GS =V BS =0V). -Electrons are rapidly sweep to the n + substrate (drain), while hole transport towards the oxide end of the plasma surface and then radially, thought the surface accumulation layer, to the p-body contact where they are collected. -These holes, pooling up against the Si/SiO 2 interface, induce an image charge on the gate electrode, leading to a transient increase of the electric field in the gate dielectric. -+-+-+-+-+-+--+-+-+-+-+-+- +-+-+-+-+-+-+-+-+-+-+-+- Electric field at the SiO 2 /Si interface as a function of the radial distance from the heavy ion strike and time following the strike.

31. 31 Power MOSFET: Single Event Gate Rupture (SEGR) Left: power MOSFET showing an ion strike at the center of the gate region, with holes moving upward and electrons downwards under the influence of the positive drain voltage. Right: The distributed RC-circuit model for the hole storage at the end of the strike filament (C IS capacitors) and the leakage path to the grounded body region (resistors). -A single high-energy heavy ion that does not cause SEB may produce Single Event Gate Rupture (SEGR) which is also capable of destroying the Power MOSFET. -After the ion strike at the center of the gate region holes are driven toward the oxide-end of the filament, at the interface between the n-epitaxial layer and the gate oxide, where they induce an image charge in the gate electrode increasing the oxide field. SEGR occurs when the ion strike far from the p-body region allows a considerable “pool” of holes to be collected at the Si/SiO 2 interface before diffusing to ground by the resistive path, locally increasing the oxide electric field beyond the breakdown value.

32. 32 Power MOSFET: Single Event Gate Rupture (SEGR) Oxide breakdown limit for V GS : -39V <V GS <0 V Breakdown limit for V DS: 0 V <V DS < 73V Maximum operating conditions specified by the manufacturer Power n-MOSFET test: fixed V DS,  V GS =-1V,  =4·10 4 ions/cm 2

33. 33 Power MOSFET: Single Event Gate Rupture (SEGR) Power n-MOSFET test: fixed V DS,  V GS =-1V,  =4·10 4 ions/cm 2 Response of the substrate Effect of the ion on the oxide. Increasing LET

34. 34 Power MOSFET: Single Event Gate Rupture (SEGR) Power n-MOSFET (t ox =50 e 150 nm, V DS =0 e 15 V) Response of the substrate Effect of the ion on the oxide. Increasing LET This expression is independent on the channel (n or p) type

35. 35 Power MOSFET: Single Event Gate Rupture (SEGR) 1998: measure of the current increase for SEGR detection and quick ion beam irradiation stop, for accurate reading of the fluence to SEGR: first measurements of the SEGR cross-section.

36. 36 Power MOSFET: SEB and SEGR Power n-MOSFET Region I: low V DS values SEGR. Region II: intermediate V DS values SEGR and SEB. Region III: high V DS values SEB. SEB can be prevented by limiting the drain current SEGR can not be prevented

37. 37 -SEGR sensitivity increase for ion impact in the center of the channel -SEB sensitivity decreases for ion impact in the center of the channel and on the p + body region. In source regions SEB occurs only at high LET values. Power MOSFET: SEB and SEGR Maximum SEGR Maximum SEB To decrease SEGR sensitivity, decrease the channel length To decrease SEB sensitivity, extend the p + plug under the source

38. 38 MOSFET: Single Event Snapback (SES) Heavy ion induces snapback in MOSFET: (a) ion injection into the depletion region; (b) movement of electrons and holes; (c) activation of the parasitic Bipolar Junction Transistor (BJT) inherent to a MOSFET. N+N+ P N CE B NPN type

39. 39 The inverter is the simplest CMOS logic gate. -When a low voltage (0 V) is applied at the input, the top p-type MOSFET is conducting (switch closed) while the bottom n-type MOSFET behaves like an open circuit: the supply voltage (5 V) appears at the output. -When a high voltage (5 V) is applied at the input, the bottom n-type MOSFET is conducting (switch closed) while the top p-type MOSFET behaves like an open circuit: the output voltage is low (0 V). -The function of this gate can be summarized by the following table: V IN V OUT HighLow High CMOS inverter V SS D S n-channel MOSFET S D p-channel MOSFET B B V DD V IN V OUT V IN V OUT CMOS inverter schematic (left) and standard symbol (right).

40. 40 CMOS inverter: Single Event Latch-up V SS DS n-channel MOSFET SD p-channel MOSFET BB V DD V IN V OUT CMOS inverter: schematic (left) and physical cross section view (right) showing the inherent p-n-p-n structure triggering the Single Event Latch-up (SEL). -A single high-energy heavy ion is capable of destroying a CMOS inverter by turning on the inherent p-n-p-n structure: Single Event Latch-up (SEL) P-MOSFETN-MOSFET BS D B D S

41. 41 CMOS inverter: the inherent p-n-p-n structure CMOS inverter: physical cross section view showing the inherent p-n-p-n structure triggering the Single Event Latch-up (up) and equivalent circuits of the p-n-p-n structure (down) implementing two parasitic BJT transistors. PMOS NMOS B n + DS p + DS n + B p + NPNNPN PNPPNP P-MOSFETN-MOSFET BS D B D S P N+N+ N C E B P+P+ P N C E B PNP type NPN type I E = I B + I C p n C E

42. 42 CMOS inverter: the inherent p-n-p-n structure Physical cross section (left) and equivalent circuits (right) of the p-n-p-n structure with the two parasitic BJT transistors.. P N N P P N V DD RSRS RWRW V SS C E B C E B P+P+ N+N+ N-Substrate P-Well RSRS V DD P P N N V SS N+N+ RWRW P+P+ P P N C E B C E B B n + S p + S n + B p + NPNNPNPNPPNP P-MOSFETN-MOSFET

43. 43 CMOS inverter: the inherent p-n-p-n structure Physical cross section (left) and equivalent circuits (right) of the p-n-p-n structure with the two parasitic BJT transistors.. P+P+ N+N+ N-Substrate P-Well RSRS V DD P P N N V SS N+N+ RWRW P+P+ P P N C E B C E B B n + S p + S n + B p + NPNNPNPNPPNP P-MOSFET N-MOSFET P N N P P N V DD RSRS RWRW V SS C E B C E B

44. 44 Physical cross section (left) and equivalent circuits (right) of the p-n-p-n structure. CMOS technology: Single Event Latchup (SEL) -In normal operating condition the two parasitic BJT are in high impedance state because the base and the emitter are shortened. -The collector of first BJT is connected to the base of the second BJT and viceversa: an unstable loop is thus inherent to the CMOS technology (I C =I B . -Under external excitation (electrical or radiation) one parasitic BJT may be forced into conduction activating the unstable loop condition. -A self-maintained low-impedance path is opened between the supply terminal V DD and V SS that may be followed by a permanent thermal failure. -This destructive effect for the CMOS technology is called Single Event Latchup (SEL)

45. 45 CMOS inverter: I-V characteristics of the p-n-p-n structure Equivalent circuit (left) and I-V characteristic of the p-n-p-n structure. -Once the break-over voltage is surpassed the devices leave the forward blocking region and passes through the negative resistance region to the ON region. -If the operating point is such that the device current is higher than the holding current I H and the device voltage is greater than the holding voltage V H, latchup is maintained. -In order to eliminate the latchup condition, it is necessary to disconnect the power supply. -Any condition that place the operating point to the ON region can trigger the latchup: an ion strike can turn on one or either the two parasitic BJTs and the resulting operation point may results in the latchup condition.

46. 46 SEL: n-well CMOS technology: p-MOSFET in n-well and n-MOSFET in p substrate with parasitic pnpn structure Test structure for Single Event Latchup studies Equivalent circuit for the pnpn structure

47. 47 Single Event Latchup Example of SEL cross section curve induced by ions: 1) the 1/cos(  ) law can be used for SEL; 2) the cross section in saturation is approximatively equal to the well area, i.e. SEL is related to the activation of the vertical parasitic BJT in the pnpn structure.

48. 48 Single Event Latchup -Latchup can be induced directly by ions and indirectly by protons and neutrons. -Latchup induced indirectly by protons and neutrons appear with the technology scaling down. -Latch-up sensitivity increases with temperature as a consequence of the bipolar gain increase with temperature. What can be deduced from the figure? By increasing the temperature the SEL threshold......... and the SEL saturation value..........

49. 49 Single Event Latchup The ion range is an important parameter for Single Event Latchup investigations. The saturation cross section is sligtly lower than the well area (dashed line) Ions with range higher than 25  m, ensuring a constant LET through a depth of 4 to 10  m Range  12 um

50. 50 ESA ESCC Basic Specification 25100

51. 51 Single Event Latchup: mitigation techniques Latch-up mitigation techniques: -SEL occurs if ß npn · ß pnp >1: reduce the gain of the parasitic bipolar transistors: for instance neutron irradiation of the silicon substrate (why neutron irradiation is better than proton irradiation?); -minimize the spreading resistance drop in the well and in the substrate (why?); -minimize the well area;

52. 52 Single Event Latchup Latch-up mitigation techniques: -instead of bulk CMOS technologies, use light doped epitaxial layers on heavily doped substrates; -use of n+ deep diffusions around the p-well to connect with the n+ buried layers. This reduces the parasitic pnp gain to virtually zero and eliminates all active four- layer paths. Charge collection in diodes fabricated on bulk and light doped epitaxial layers on heavily doped substrates

53. 53 Single Event Latchup Latch-up mitigation techniques: -instead of bulk or epitaxial CMOS technologies, use SOI technologies which avoid the pnpn structure; -the minimum holding voltage for Latchup is 1 V, so Latchup sensitivity is expected to vanish for deep submicron CMOS technologies; -removing the power supply when high current power supply is detected (this does not allow to avoid latent damage in metal traces on IC, which bring to electromigration failures). CMOS/epi Comparison of CMOS technologies: -on light doped epitaxial layers on heavily doped substrates; -on insulator.

54. 54 Single Event Drain Current Collapse (SEDC 2 ) W L W L

55. 55 Single Event Drain Current Collapse (SEDC 2 ) W L

56. 56 Single Event Drain Current Collapse (SEDC 2 ) W L

57. 57 Origin of the Single Event Drain Current Collapse (SEDC 2 )

58. 58 Other non-destructive single event effects -Single Event Upset (SEU): bit flip in a digital element A SEU is a logic state transaction of a single bit, i.e. the changed of the stored information from 1 to 0 or from 0 to 1 in a memory cell, induced by the collections at a sensitive node of the charge generated by a single event. The SEU is characteristic of the storage memory elements: SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memories) -Single Event Disturb (SED): bit unstable equilibrium A SED is an error characteristic of Static Random Access Memories (SRAM) cells which is initiated or disturbed by a single event, such that it will return to its original state by itself. The disturb state can last for milliseconds and a reading of the bit during that time will be erroneous.

59. 59 Other non-destructive single event effects -Single Event Transient (SET): signal transient in digital or analog electronics The charge collection due to a single event at a location of a digital or analog circuit may cause a voltage or current transient, which propagates down a path such that a temporary errors in the circuit functionality occurs at a location at some distance from the original charge collection site. -Single Event Functional Interrupt (SEFI): device failure A SEFI is a single event characteristics of complex digital electronics such as Filed Gate Programmable Array (FPGA) causing the device to stop from normal functions, and usually requires a power reset to resume normal operations. It is a special case of SEU changing an internal control signal.

60. 60 Single Event Transient (SET) in digital electronics When the transient on a data line occurs during the setup ad hold times for a latch, it can produce a SET errors (TNS vol.55, n.4, pp.1903-1925)

61. 61 CMOS SRAM cell Schematic of a CMOS SRAM cell: the inverters on each half of the cell are biased in opposite direction, so that in each case one n-channel transistor and one p-channel transistor is ON and the other is OFF (up). Layout top view: green regions are the gate polysilicon lines, the blue lines show the interconnections within the unit cell (left). 3D- view during an ion strike (left).

62. 62 SEU in CMOS SRAM cells Evolution of the SEU sensitive area as a function of the ion LET, including initially only the reverse biased NMOS drain and then also the reverse biased PMOS drain. Mesh for the 3D-simulation Davinci.

63. 63 SEU and SEL charge collection regions in CMOS technologies Charge collection regions for Single Event Upset (SEU) and Single Event Latchup.

64. 64 Cross section of a typical EPROM floating gate transistor (left). Erase mode and programming mode (right) Electrical Programmable Read Only Memories (EPROM)

65. 65 -Failure mechanism in Flash memories irradiated by heavy ions: charge loss from the floating gate by Positive charge Assisted Leakage Current (PALC) Positive charge Assisted Leakage Current (PALC) in E 2 PROM Threshold voltage distribution of the E 2 PROM cells before and after irradiation. Positive charge assisted leakage current mechanism.

66. 66 Single event effects (SEE) experience by astronauts -Apollo 13 is the first space mission leading the man on the moon in 1969. -Skylab was the first USA space station, launched into orbit in 1973. -Apollo and Skylab astronauts reported frequent small flashes. These star-like flashes were induced by cosmic rays and/or individual proton-induced spallation reactions in or near the summation units of the retina. Cosmic ray ion traversing the vitreous of the eye and a spallation reaction at the peripherical retina.

67. 67 Test

68. 68 1) Dopo aver realizzato lo schema di un MOSFET di potenza a canale n in cui evidenzi la presenza del BJT parassita, descrivi il meccanismo fisico che porta alla rottura del dispositivo tramite burn-out (SEB). Quali dati sperimentali vengono considerati per studiare il burn-out nei MOSFET di potenza a canale n? 2) Quale è la regione più sensibile al burn-out (SEB) di un MOSFET di potenza a causa dell’impatto da uno ione? Quali sono le tecniche utilizzate per diminuire la sensibilità al burn-out? Perchè ai fini dello studio del burn-out è rilevante il range dello ione? 3) Dopo aver realizzato lo schema di un MOSFET di potenza a canale n, descrivi il meccanismo fisico che porta alla rottura del dispositivo per rottura dell’ossido di gate (SEGR). Quali dati sperimentali vengono considerati per studiare il SEGR nei MOSFET di potenza a canale n? 4) Al variare del LET dello ione incidente e della Vds del MOSFET di potenza a canale n, quando diventa predominante il SEB ed il SEGR? Il SEB si può prevenire nei test sperimentali? Il SEGR si può prevenire nei test sperimentali? Test: domande 1-4

69. 69 5) Che cos’è il Latch-up (SEL) ed in quali dispositivi è rivelante? Quale è la struttura parassita la cui attivazione può indurre il Latch-up? Quali tecniche di layout possono essere utilizzate per prevenire il Latch-up? 6) Che cosa si intende per SEDC 2, SET, SEFI, PALC? Test: domande 5-6

70. 70 Note -Il materiale, la cui raccolta e organizzazione ha richiesto un notevole impegno, può essere utilizzato liberamente per fini di studio e ricerca, se possibile citandone la fonte e le referenze. -Ringrazio tutti coloro che mi segnaleranno parti da correggere/migliorare.